CN110024116A - 堆叠管芯腔封装 - Google Patents

堆叠管芯腔封装 Download PDF

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Publication number
CN110024116A
CN110024116A CN201680091161.3A CN201680091161A CN110024116A CN 110024116 A CN110024116 A CN 110024116A CN 201680091161 A CN201680091161 A CN 201680091161A CN 110024116 A CN110024116 A CN 110024116A
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CN
China
Prior art keywords
integrated circuit
chamber
coupled
substrate
electrically conducting
Prior art date
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Pending
Application number
CN201680091161.3A
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English (en)
Inventor
M.莫迪
R.L.桑克曼
D.马利克
R.V.马哈詹
A.P.阿卢尔
邓一康
E.J.李
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Intel Corp
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Intel Corp
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Publication date
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Publication of CN110024116A publication Critical patent/CN110024116A/zh
Pending legal-status Critical Current

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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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Abstract

提供了一种装置，其包括：形成衬底的多个介电层；所述衬底的第一表面上的多个第一导电接触部；所述衬底的第一表面中的腔，限定与所述第一表面平行的第二表面；所述衬底的第二表面上的多个第二导电接触部；与所述第二导电接触部耦合的一个或多个集成电路管芯；以及模塑材料，至少部分地覆盖所述一个或多个集成电路管芯和所述第一导电接触部。还公开且要求保护其他实施例。

Description

堆叠管芯腔封装
背景技术
随着计算设备（诸如，智能电话）在大小方面缩小的同时持续在性能和能力方面增长，堆叠封装（PoP）架构的使用已经扩充。针对PoP架构而设计的衬底不仅要求附着设备的空间，而且要求用于路由互连件和通孔的空间，以便于与设备通信。
附图说明
将从下面给出的详细描述以及从本公开的各种实施例的附图更充分地理解本公开的实施例，然而，附图不应当被理解成将本公开限于具体实施例，而是仅用于解释和理解。
图1图示了根据一些实施例的堆叠管芯腔封装的横截面视图，
图2A-2I图示了根据一些实施例的堆叠管芯腔封装的制造步骤的横截面视图，
图3图示了根据一些实施例的形成堆叠管芯腔封装的方法的流程图，以及
图4图示了根据一些实施例的包括堆叠管芯腔封装的智能设备或计算机系统或SoC（片上系统）。
具体实施方式
总体上呈现了堆叠管芯腔封装。在这点上，本发明的实施例实现了关于大管芯和管芯堆叠的传统顶侧球附着、模塑和穿塑互连（TMI）钻孔。本领域技术人员将领会，这些封装可以避免形状因子增长、PoP管脚减小和非常高的穿塑互连接点，诸如双顶侧焊料球。
在以下描述中，讨论了许多细节以提供本公开的实施例的更透彻解释。然而，对本领域技术人员来说应当明显的是，可以在没有这些具体细节的情况下实践本公开的实施例。在其他实例中，以框图形式而不是详细地示出公知结构和设备，以便避免使本公开的实施例模糊。
注意，在实施例的对应图中，利用线表示信号。一些线可能较粗以指示更多组成信号路径，和/或在一个或多个端部处具有箭头以指示主要信息流动方向。这种指示不意在进行限制。相反，结合一个或多个示例性实施例使用该线，以便于更容易地理解电路或逻辑单元。如设计需要或偏好所规定，任何所表示的信号实际上可以包括可在两个方向中的任一个方向上行进且可利用任何合适类型的信号方案实现的一个或多个信号。
遍及本说明书并且在权利要求中，术语“连接”意指没有任何中间设备的直接连接，诸如，所连接的事物之间的电、机械或磁连接。术语“耦合”意指：直接或间接连接，诸如，所连接的事物之间的直接电、机械或磁连接；或者通过一个或多个无源或有源中间设备的间接连接。术语“电路”或“模块”可以指代被布置成彼此协作以提供期望功能的一个或多个无源和/或有源部件。术语“信号”可以指代至少一个电流信号、电压信号、磁信号或数据/时钟信号。“一”、“一个”和“该”的含义包括复数引用。“在……中”的含义包括“在……中”和“在……上”。
除非以其他方式指定，为了描述公共对象而对序数形容词“第一”、“第二”和“第三”等的使用仅仅指示正在指代相似对象的不同实例，而不意在暗示如此描述的对象必须在时间方面、在空间方面、在等级方面或以任何其他方式按给定顺序。
出于本公开的目的，短语“A和/或B”和“A或B”意指（A）、（B）或（A和B）。出于本公开的目的，短语“A、B和/或C”意指（A）、（B）、（C）、（A和B）、（A和C）、（B和C）或（A、B和C）。描述中和权利要求中的术语“左”、“右”、“前”、“后”、“顶”、“底”、“在……之上”、“在……之下”等等（如果有的话）用于描述性目的，而不必然用于描述永久相对位置。
图1图示了根据一些实施例的堆叠管芯腔封装的横截面视图。如所示的那样，封装100包括腔衬底102、管芯堆叠104、模塑化合物106、设备108、穿塑通孔110和封装接触部112。可以使用下文中关于各种实施例而描述的方法来形成封装100，然而，对本领域技术人员来说在不脱离本发明的范围的情况下可以想到其他变型和可替换方案。
腔衬底102可以由点缀有导电材料的介电材料的多个层形成。在一些实施例中，腔衬底102包括已利用树脂系统（通常称作预浸料）预浸渍的加强结构的多个层。尽管为了易于描绘而未示出，但多个导电迹线和通孔将很可能存在于腔衬底102中，以向和/或从管芯堆叠104和设备108提供功率和/或数据。尽管被示作包括一个中央定位的腔103，但腔衬底102可以包括任何布置中的任何数目的腔。
管芯堆叠104可以表示可能受益于本发明的教导的相对大的管芯或管芯堆叠。在一些实施例中，管芯堆叠104表示原位耦合的两个或更多个管芯，然而，任何数目的管芯可以被使用且可以作为另一制造过程的一部分而预耦合。在一些实施例中，管芯堆叠104可以包括一个或多个处理器、现场可编程门阵列（FPGA）、协处理器、控制器、存储器和/或其他集成电路设备。管芯堆叠104的管芯105、107和109可以以任何可想到的方式物理和/或电耦合，该可想到方式包括但不限于下文中呈现的示例。
模塑化合物106可以提供针对管芯堆叠104的稳定性和/或绝缘。在一些实施例中，模塑化合物106包含可能要求或可能不要求固化步骤的环氧树脂。模塑化合物106可以是基于各种因素来构造的，该各种因素包括但不限于流速率、固化时间、热膨胀和易于激光钻孔。
设备108可以是可受益于本发明的教导的任何类型的设备封装。在一些实施例中，设备108是存储器设备。尽管被示作跨越管芯堆叠104上面的腔衬底102中的腔的单个设备，但设备108可以是多个设备封装。在一些实施例中，设备108通过穿塑通孔110与腔衬底102耦合，穿塑通孔110可以包括模塑化合物106中的经激光钻孔的开口，以在腔衬底102的表面上暴露焊料球体111或其他形式，在一些实施例中，相同设备108与腔衬底102中的腔的相反侧上的焊料球体耦合。
封装接触部112可以包括凸块或其他导电接触部，以允许封装100与印刷电路板耦合，例如作为集成系统的一部分。在一些实施例中，可以使用管脚、焊盘或垫。
图2A-2I图示了根据一些实施例的堆叠管芯腔封装的制造步骤的横截面视图。如图2A中所示，组件200包括介电层202、金属层204、顶表面206和底表面208。
介电层202可以表示使金属迹线和通孔（未示出）绝缘的迭代形成的介电材料。在一些实施例中，介电层202是预浸料材料的层。介电层202可以在厚度方面一致或者可以在厚度方面不同。
金属层204可以将信号和功率路由通过衬底。在一些实施例中，金属层204是铜，尽管可以使用其他金属。在一些实施例中，一个或多个金属层204可以被包括以提供结构稳定性以便充当衬底芯。
在一些实施例中，顶表面206和底表面208是阻焊剂或焊罩，用于保护铜迹线免于氧化且防止焊接桥在紧密间隔的焊垫之间形成。在一些实施例中，顶表面206和底表面208表示被喷洒或丝网印刷到邻近金属层204上且然后被固化的液体环氧的层。
图2B示出了通过顶表面206、腔表面214和腔接触部216而形成的可包括腔212的组件210。在一些实施例中，通过移除介电层202的长方体部分向下一直到邻近金属层204来形成腔212。在一些实施例中，通过激光释放或通过机械路由来形成腔212。在一些实施例中，腔212具有约100 um和300 um之间的深度，尽管可以使用其他深度。
腔212的形成可以创建与顶表面206平行的腔表面214。在一些实施例中，在腔表面214内或之上形成腔接触部216。在一些实施例中，被设计成提供腔表面214的金属层204具有先前在其上形成的腔接触部216，并且腔212的创建暴露了腔接触部216。
如图2C中所示，组件220已经具有与腔接触部216耦合的第一设备222。在一些实施例中，第一设备222包括用于与腔接触部216中的一些或可能全部耦合的焊料球224。在其他实施例中，除焊料球外，可以使用其他接触装置。
现在转至图2D，组件230可以包括与第一设备222耦合的第二设备232。在一些实施例中，第二设备232包括与第一设备222内的硅通孔236耦合的焊料球234或其他导电配件（fitting）。硅通孔可以将第二设备232与腔接触部216中的一些导电耦合。
图2E示出了可包括附着到第二设备232的第三设备242的组件240。在一些实施例中，第三设备242通过粘合剂246与第二设备232机械接合。在一些实施例中，与第三设备242的电连接由线接合部244提供，线接合部244可以与腔接触部216中的一些耦合。
如图2F中所示，对于组件250，可能已经在顶表面206上形成焊料球体252。在一些实施例中，焊料球体252不如管芯堆叠（例如，第三设备242）的顶部那样远离于顶表面206而延伸。焊料球体252可以由锡基焊料、铅基焊料或其他导电材料制成。尽管基于一般形状而提到，但焊料球体252可能不是完全地或完美地球状的。本领域技术人员将领会，术语“球体”是非正式使用的，并且可以使用其他形状/形式。
现在转至图2G，组件260可以包括在顶表面206和填充腔212上面形成的模塑化合物262。尽管被示作具有完全覆盖焊料球体252的平坦上表面，但模塑化合物262可以是非均匀沉积的，例如以符合其他表面（诸如，焊料球体252和第三设备242的表面）的方式沉积的。在其他实施例中，防止模塑化合物262完全覆盖焊料球体252，例如通过使用暂时阻挡层。
图2H示出了组件270，其可以包括已在模塑化合物262中形成以暴露焊料球体252的穿塑通孔272。穿塑通孔272可以是通过模塑化合物262的激光消融来形成的。穿塑通孔272可以具有暴露焊料球体252中的每一个的近似顶半部的平行或有角度的边。
如图2I中所示，组件280包括已附着到底表面208的凸块282。在一些实施例中，凸块282表示焊料球，然而，可以使用其他导电装置，诸如管脚或焊盘，例如以将所组装的封装附着到插座、电路板或其他封装。
图3图示了根据一些实施例的形成具有壁侧电容器的封装的方法的流程图。尽管参考图3的流程图中的框是按特定次序示出的，但可以修改动作的次序。因此，可以按不同的次序执行所图示的实施例，并且可以并行地执行一些动作/框。根据某些实施例，图3中列出的框和/或操作中的一些是可选的。所呈现的框的编号是为了清楚的目的，而不意在规定各种框必须出现的操作次序。附加地，可以以多种组合利用来自各种流程的操作。
方法300开始于在衬底（诸如，腔衬底102）中形成（302）腔。在一些实施例中，通过预浸料材料的长方体部分的激光释放或机械路由来形成腔212。在一些实施例中，当腔被形成时，预浸料材料（诸如，介电层202）尚未被固化。在一些实施例中，所形成的腔大于约100um深且具有金属层之上的底表面。
接着，将管芯堆叠（诸如，管芯堆叠104）附着（304）到腔表面。在一些实施例中，管芯堆叠包括与衬底腔原位机械耦合以及可能原位电耦合的两个或更多个设备。在其他实施例中，管芯堆叠被预组装且作为单个单元而附着到腔衬底。在一些实施例中，管芯堆叠内的设备通过硅通孔而电耦合。在一些实施例中，管芯堆叠内的设备线接合到腔衬底表面上的接触部。
然后，在上衬底表面206上形成（306）焊料球体，诸如焊料球体252。接着，在一些实施例中，利用模塑化合物262对腔212和焊料球体252进行超模塑（overmold）（308）。
在一些实施例中，该方法继续形成（310）穿塑通孔272，以暴露焊料球体252。在一些实施例中，使用激光钻孔以移除模塑化合物262的部分。接着，在一些实施例中，在底表面208上形成（312）凸块282。最后，可以将设备108与（所填充的）腔和管芯堆叠的相反侧上的焊料球体耦合（314）。
图4图示了根据一些实施例的包括堆叠管芯腔封装的智能设备或计算机系统或SoC（片上系统）400。在一些实施例中，计算设备400表示移动计算设备（诸如，计算平板、移动电话或智能电话）、无线使能电子阅读器或其他无线移动设备。应当理解，总体上示出了某些部件，并且不是这种设备的所有部件都在计算设备400中示出。在一些实施例中，计算设备400的一个或多个部件（例如，处理器410和/或存储器子系统460）被包括在如上所描述的具有壁侧电容器的封装中。
出于实施例的目的，这里描述的各种电路和逻辑块中的晶体管是金属氧化物半导体（MOS）晶体管或其衍生物，其中MOS晶体管包括漏极、源极、栅极和块体端子。晶体管和/或MOS晶体管衍生物还包括Tri-Gate（三栅极）和FinFET（鳍式FET）晶体管、环绕栅极圆柱晶体管、隧穿FET（TFET）、方形线或矩形带晶体管、铁电FET（FeFET）、或者实现晶体管功能的其他设备（像碳纳米管或电子自旋设备）。MOSFET对称源极和漏极端子即为相同端子且在这里可互换地使用。另一方面，TFET设备具有非对称源极和漏极端子。本领域技术人员应当领会，在不脱离本公开的范围的情况下，可以使用其他晶体管，例如双极结型晶体管——BJTPNP/NPN、BiCMOS、CMOS等。
在一些实施例中，计算设备400包括第一处理器410。本公开的各种实施例还可以包括470内的网络接口（诸如，无线接口），使得系统实施例可以被并入到无线设备（例如，蜂窝电话或个人数字助理）中。
在一个实施例中，处理器410可以包括一个或多个物理设备，诸如微处理器、应用处理器、微控制器、可编程逻辑设备或其他处理装置。由处理器410执行的处理操作包括在其上执行应用和/或设备功能的操作平台或操作系统的执行。该处理操作包括关于与人类用户或与其他设备的I/O（输入/输出）的操作、关于功率管理的操作和/或关于将计算设备400连接到另一设备的操作。该处理操作还可以包括关于音频I/O和/或显示I/O的操作。
在一个实施例中，计算设备400包括：音频子系统420，其表示与将音频功能提供给计算设备相关联的硬件（例如，音频硬件和音频电路）和软件（例如，驱动器、编解码器）部件。音频功能可以包括扬声器和/或头戴式耳机输出以及麦克风输入。用于这种功能的设备可以集成到计算设备400中或者连接到计算设备400。在一个实施例中，用户通过提供由处理器410接收到且处理的音频命令来与计算设备400交互。
显示子系统430表示提供视觉和/或触觉显示以供用户与计算设备400交互的硬件（例如，显示设备）和软件（例如，驱动器）部件。显示子系统430包括显示接口432，显示接口432包括用于将显示提供给用户的特定屏幕或硬件设备。在一个实施例中，显示接口432包括与处理器410分离的执行与显示相关的至少一些处理的逻辑。在一个实施例中，显示子系统430包括将输出和输入两者提供给用户的触摸屏（或触摸板）设备。
I/O控制器440表示关于与用户的交互的硬件设备和软件部件。I/O控制器440可操作成管理作为音频子系统420和/或显示子系统430的一部分的硬件。附加地，I/O控制器440图示了连接到用户可能通过其而与系统交互的计算设备400的附加设备的连接点。例如，可附着到计算设备400的设备可能包括麦克风设备、扬声器或立体声系统、视频系统或其他显示设备、键盘或键区设备、或者供具体应用使用的其他I/O设备（诸如，读卡器或其他设备）。
如上所提及，I/O控制器440可以与音频子系统420和/或显示子系统430交互。例如，通过麦克风或其他音频设备的输入可以提供针对计算设备400的一个或多个应用或功能的输入或命令。附加地，取代显示输出或者除显示输出外，可以提供音频输出。在另一示例中，如果显示子系统430包括触摸屏，则显示设备还充当输入设备，其可以至少部分地由I/O控制器440管理。在计算设备400上还可以存在附加按钮或开关，以提供由I/O控制器440管理的I/O功能。
在一个实施例中，I/O控制器440管理诸如加速度计、相机、光传感器或其他环境传感器之类的设备或者可被包括在计算设备400中的其他硬件。输入可以是直接用户交互的一部分以及将环境输入提供给系统以影响其操作（诸如，针对噪声进行滤波、针对亮度检测而调整显示器、应用相机的闪光灯或其他特征）。
在一个实施例中，计算设备400包括功率管理450，功率管理450管理电池功率使用率、电池的充电和关于功率节约操作的特征。存储器子系统460包括用于将信息存储在计算设备400中的存储器设备。存储器可以包括非易失性（如果对存储器设备的功率被中断，状态不改变）和/或易失性（如果对存储器设备的功率被中断，状态不确定）存储器设备。存储器子系统460可以存储应用数据、用户数据、音乐、照片、文档或其他数据、以及与计算设备400的应用和功能的执行相关的系统数据（不论是长期的还是暂时的）。
实施例的元件还作为用于存储计算机可执行指令的机器可读介质（例如，存储器460）而提供。机器可读介质（例如，存储器460）可以包括但不限于闪速存储器、光盘、CD-ROM、DVD ROM、RAM、EPROM、EEPROM、磁或光卡、相变存储器（PCM）、或者适于存储电子或计算机可执行指令的其他类型的机器可读介质。例如，本公开的实施例可以作为计算机程序（例如，BIOS）而下载，该计算机程序可以经由通信链路（例如，调制解调器或网络连接）凭借数据信号而从远程计算机（例如，服务器）传送到请求计算机（例如，客户端）。
连接470包括使计算设备400能够与外部设备通信的硬件设备（例如，无线和/或有线连接器和通信硬件）和软件部件（例如，驱动器、协议栈）。计算设备400可以是分离的设备（诸如其他计算设备、无线接入点或基站）以及外设（诸如，耳机、打印机或其他设备）。
连接470可以包括多种不同类型的连接。概括地说，计算设备400是利用蜂窝连接472和无线连接474图示的。蜂窝连接472一般指代由无线运营商提供（诸如，经由GSM（全球移动通信系统）或变型或衍生物、CDMA（码分多址）或变型或衍生物、TDM（时分复用）或变型或衍生物、或者其他蜂窝服务标准而提供）的蜂窝网络连接。无线连接（或无线接口）474指代非蜂窝的无线连接，且可以包括个域网（诸如蓝牙、近场等）、局域网（诸如Wi-Fi）和/或广域网（诸如WiMax）或其他无线通信。
外围连接480包括作出外围连接的硬件接口和连接器以及软件部件（例如，驱动器、协议栈）。应当理解，计算设备400可以既是对其他计算设备来说（“去往”482）的外围设备，又使外围设备（“来自”484）连接到它。计算设备400通常具有用于出于诸如管理（例如，下载和/或上传、改变、同步）计算设备400上的内容之类的目的而连接到其他计算设备的“对接（docking）”连接器。附加地，对接连接器可以允许计算设备400连接到某些外设，这些外设允许计算设备400控制例如到视听或其他系统的内容输出。
除了专有对接连接器或其他专有连接硬件外，计算设备400还可以经由常见的或基于标准的连接器来作出外围连接480。常见类型可以包括：通用串行总线（USB）连接器（其可以包括多个不同硬件接口中的任一个）；包括MiniDisplayPort（MDP）的DisplayPort；高清多媒体接口（HDMI）；火线；或其他类型。
在说明书中对“一实施例”、“一个实施例”、“一些实施例”或“其他实施例”的引用意味着：结合该实施例而描述的特定特征、结构或特性被包括在至少一些实施例但不必然是所有实施例中。“一实施例”、“一个实施例”或“一些实施例”的各种出现不必然全部指代相同实施例。如果说明书声明部件、特征、结构或特性“可以”、“可能”或“可”被包括，则该特定部件、特征、结构或特性不必须被包括。如果说明书或权利要求提到“一”或“一个”元件，则这不意味着存在仅一个该元件。如果说明书或权利要求提到“附加”元件，则这不排除存在多于一个该附加元件。
此外，在一个或多个实施例中，可以以任何合适方式组合特定特征、结构、功能或特性。例如，在与这两个实施例相关联的特定特征、结构、功能或特性不互斥的任何地方，可以将第一实施例与第二实施例进行组合。
尽管本公开已经结合其具体实施例加以描述，但这种实施例的许多可替换方案、修改和变型对本领域普通技术人员来说考虑到以上描述将是明显的。本公开的实施例意在涵盖所有这样的可替换方案、修改和变型以至于落在所附权利要求的宽范围内。
附加地，可以或可以不在所呈现的图内示出到集成电路（IC）芯片和其他部件的公知功率/接地连接，以用于简化图示和讨论且以免使本公开模糊。进一步地，可以以框图形式示出布置，以便避免使本公开模糊且还考虑到下述事实：关于这种框图布置的实现的细节非常依赖于要在其内实现本公开的平台（即，这种细节应当完全处于本领域技术人员的视界内）。在阐述了具体细节（例如，电路）以便描述本公开的示例实施例的情况下，对本领域技术人员来说应当明显的是，可以在没有这些具体细节的情况下或者在这些具体细节的变化下实践本公开。因此，该描述应被视为说明性的而不是进行限制。
以下示例涉及进一步的实施例。可以在一个或多个实施例中的任何地方使用示例中的细节。还可以关于方法或过程实现本文描述的装置的所有可选特征。
在一个示例中，提供了一种装置，包括：形成衬底的多个介电层；所述衬底的第一表面上的多个第一导电接触部；所述衬底的第一表面中的腔，限定与所述第一表面平行的第二表面；所述衬底的第二表面上的多个第二导电接触部；与所述第二导电接触部耦合的一个或多个集成电路管芯；以及模塑材料，至少部分地覆盖所述一个或多个集成电路管芯和所述第一导电接触部。
一些实施例还包括所述衬底内的芯层。一些实施例还包括与所述第一导电接触部耦合的存储器设备，所述存储器设备跨越所述腔。在一些实施例中，所述腔包括大于约100um的深度。在一些实施例中，所述第一导电接触部包括焊料形式。
在一些实施例中，所述一个或多个集成电路管芯包括：第一集成电路管芯，与所述第二导电接触部耦合；以及第二集成电路管芯，通过硅通孔与所述第一集成电路管芯耦合。
在另一示例中，提供了一种集成电路封装，包括：衬底，包括：第一表面；所述第一表面中的腔，限定与所述第一表面平行的第二表面；所述第一表面上的焊料形式，处于所述腔的相反侧上；以及所述第二表面上的导电接触部；一个或多个集成电路管芯，与所述第二表面上的导电接触部耦合；模塑材料，覆盖所述一个或多个集成电路管芯；以及集成电路设备，与所述腔的相反侧上的焊料形式耦合。
在一些实施例中，所述一个或多个集成电路设备包括：第一集成电路管芯，与所述第二表面上的导电接触部耦合；以及第二集成电路管芯，与所述第一集成电路管芯的顶表面耦合。一些实施例还包括：通过线接合与所述第二表面上的导电接触部导电耦合的所述第二集成电路管芯。在一些实施例中，所述腔包括大于约100 um的深度。在一些实施例中，所述一个或多个集成电路管芯包括处理器。在一些实施例中，与所述焊料形式耦合的集成电路设备包括存储器设备。
在另一示例中，提供了一种系统，包括：显示子系统；无线通信接口；以及集成电路封装，所述集成电路封装包括：衬底，包括：第一表面；所述第一表面中的腔，限定与所述第一表面平行的第二表面；所述第一表面上的焊料形式，处于所述腔的相反侧上；以及所述第二表面上的导电接触部；一个或多个集成电路管芯，与所述第二表面上的导电接触部耦合；以及存储器设备，与所述腔的相反侧上的焊料形式耦合。
一些实施例还包括：模塑材料，覆盖所述一个或多个集成电路管芯和所述焊料形式，其中所述存储器设备通过穿塑通孔与所述焊料形式耦合。在一些实施例中，所述腔包括大于约100 um的深度。在一些实施例中，所述一个或多个集成电路设备包括处理器。在一些实施例中，所述一个或多个集成电路设备包括：第一集成电路管芯，与所述第二表面上的导电接触部耦合；以及第二集成电路管芯，与所述第一集成电路管芯的顶表面耦合。在一些实施例中，所述第二集成电路管芯通过硅通孔与所述第一集成电路管芯导电耦合。
在另一示例中，提供了一种方法，包括：形成具有腔的衬底，所述腔限定下表面和与所述下表面平行的上表面；在所述上表面上形成焊料形式；将一个或多个管芯附着到所述衬底的下表面；对所述一个或多个管芯和所述焊料形式进行超模塑；以及形成穿塑通孔以暴露所述焊料形式。
在一些实施例中，形成具有腔的衬底包括：将预浸料和铜的层进行组合；移除从所述衬底的上表面延伸到铜层的预浸料的长方体部分；以及对所述预浸料进行固化。在一些实施例中，移除预浸料的长方体部分包括激光释放。在一些实施例中，附着一个或多个管芯包括：将第一集成电路管芯耦合到所述下表面上的接触部；以及将第二集成电路管芯耦合到所述第一集成电路管芯的表面。
一些实施例还包括：将设备附着到所述衬底的上表面上的焊料形式，其中所述设备跨越所述腔。在一些实施例中，所述设备包括存储器设备。在一些实施例中，附着一个或多个管芯包括：将集成电路管芯的接触部与硅通孔耦合。
在另一示例中，提供了一种堆叠管芯腔集成电路设备封装，包括：形成衬底的装置；所述衬底的第一表面上的多个第一导电装置；所述衬底的第一表面中的腔，限定与所述第一表面平行的第二表面；所述衬底的第二表面上的多个第二导电装置；与第二导电接触部耦合的一个或多个集成电路管芯；以及绝缘装置，至少部分地覆盖所述一个或多个集成电路管芯和第一导电接触部。
在一些实施例中，所述用于形成衬底的装置包括衬底芯。一些实施例还包括与第一导电接触部耦合的存储器设备，所述存储器设备跨越所述腔。在一些实施例中，所述腔包括大于约100 um的深度。在一些实施例中，所述第一导电装置包括焊料形式。在一些实施例中，所述一个或多个集成电路管芯包括：第一集成电路管芯，与所述第二导电装置耦合；以及第二集成电路管芯，通过硅通孔与所述第一集成电路管芯耦合。
提供了将允许读者弄清技术公开内容的性质和要点的摘要。该摘要是在理解其不会用于限制权利要求的范围或含义的情况下提交的。所附权利要求特此被并入到详细描述中，其中每一个权利要求独立自主地作为单独的实施例。

Claims (25)

1.一种装置，包括：
形成衬底的多个介电层；
所述衬底的第一表面上的多个第一导电接触部；
所述衬底的第一表面中的腔，限定与所述第一表面平行的第二表面；
所述衬底的第二表面上的多个第二导电接触部；
与所述第二导电接触部耦合的一个或多个集成电路管芯；以及
模塑材料，至少部分地覆盖所述一个或多个集成电路管芯和所述第一导电接触部。
2.如权利要求1所述的装置，进一步包括所述衬底内的芯层。
3.如权利要求1所述的装置，进一步包括与所述第一导电接触部耦合的存储器设备，所述存储器设备跨越所述腔。
4.如权利要求1所述的装置，其中所述腔包括大于约100 um的深度。
5.如权利要求1至4中任一项所述的装置，其中所述第一导电接触部包括焊料形式。
6.如权利要求1至4中任一项所述的装置，其中所述一个或多个集成电路管芯包括：
第一集成电路管芯，与所述第二导电接触部耦合；以及
第二集成电路管芯，通过硅通孔与所述第一集成电路管芯耦合。
7.一种集成电路封装，包括：
衬底，包括：
第一表面；
所述第一表面中的腔，限定与所述第一表面平行的第二表面；
所述第一表面上的焊料形式，处于所述腔的相反侧上；以及
所述第二表面上的导电接触部；
一个或多个集成电路管芯，与所述第二表面上的导电接触部耦合；
模塑材料，覆盖所述一个或多个集成电路管芯；以及
集成电路设备，与所述腔的相反侧上的焊料形式耦合。
8.如权利要求7所述的装置，其中所述一个或多个集成电路设备包括：
第一集成电路管芯，与所述第二表面上的导电接触部耦合；以及
第二集成电路管芯，与所述第一集成电路管芯的顶表面耦合。
9.如权利要求8所述的装置，进一步包括：通过线接合与所述第二表面上的导电接触部导电耦合的所述第二集成电路管芯。
10.如权利要求7所述的装置，其中所述腔包括大于约100 um的深度。
11.如权利要求7至10中任一项所述的装置，其中所述一个或多个集成电路管芯包括处理器。
12.如权利要求7至10中任一项所述的装置，其中与所述焊料形式耦合的集成电路设备包括存储器设备。
13.一种系统，包括：
显示子系统；
无线通信接口；以及
集成电路封装，所述集成电路封装包括：
衬底，包括：
第一表面；
所述第一表面中的腔，限定与所述第一表面平行的第二表面；
所述第一表面上的焊料形式，处于所述腔的相反侧上；以及
所述第二表面上的导电接触部；
一个或多个集成电路管芯，与所述第二表面上的导电接触部耦合；以及
存储器设备，与所述腔的相反侧上的焊料形式耦合。
14.如权利要求13所述的系统，进一步包括：模塑材料，覆盖所述一个或多个集成电路管芯和所述焊料形式，其中所述存储器设备通过穿塑通孔与所述焊料形式耦合。
15.如权利要求13所述的系统，其中所述腔包括大于约100 um的深度。
16.如权利要求13所述的系统，其中所述一个或多个集成电路设备包括处理器。
17.如权利要求13至16中任一项所述的系统，其中所述一个或多个集成电路设备包括：
第一集成电路管芯，与所述第二表面上的导电接触部耦合；以及
第二集成电路管芯，与所述第一集成电路管芯的顶表面耦合。
18.如权利要求17所述的系统，其中所述第二集成电路管芯通过硅通孔与所述第一集成电路管芯导电耦合。
19.一种方法，包括：
形成具有腔的衬底，所述腔限定下表面和与所述下表面平行的上表面；
在所述上表面上形成焊料球体；
将一个或多个管芯附着到所述衬底的下表面；
对所述一个或多个管芯和所述焊料球体进行超模塑；以及
形成穿塑通孔以暴露所述焊料球体。
20.如权利要求19所述的方法，其中形成具有腔的衬底包括：
将预浸料和铜的层进行组合；
移除从所述衬底的上表面延伸到铜层的预浸料的长方体部分；以及
对所述预浸料进行固化。
21.如权利要求20所述的方法，其中移除预浸料的长方体部分包括激光释放。
22.如权利要求19所述的方法，其中附着一个或多个管芯包括：
将第一集成电路管芯耦合到所述下表面上的接触部；以及
将第二集成电路管芯耦合到所述第一集成电路管芯的表面。
23.如权利要求19至22中任一项所述的方法，进一步包括：将设备附着到所述衬底的上表面上的焊料球体，其中所述设备跨越所述腔。
24.如权利要求23所述的方法，其中所述设备包括存储器设备。
25.如权利要求19至22中任一项所述的方法，其中附着一个或多个管芯包括：将集成电路管芯的接触部与硅通孔耦合。
CN201680091161.3A 2016-12-27 2016-12-27 堆叠管芯腔封装 Pending CN110024116A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022016470A1 (zh) * 2020-07-23 2022-01-27 华为技术有限公司 一种芯片封装结构、电子设备

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210070439A (ko) * 2019-12-04 2021-06-15 주식회사 심텍 딥 캐비티 구조의 다층 인쇄회로기판 및 그 제조 방법과, 그 반도체 패키지
US11948920B2 (en) * 2021-08-30 2024-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method for manufacturing the same, and semiconductor package

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250916A (ja) * 2006-03-17 2007-09-27 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US20110317381A1 (en) * 2010-06-29 2011-12-29 Samsung Electronics Co., Ltd. Embedded chip-on-chip package and package-on-package comprising same
KR20130042936A (ko) * 2011-10-19 2013-04-29 에스케이하이닉스 주식회사 칩 캐리어, 이를 이용한 반도체 칩, 반도체 패키지, 및 그 제조방법들
CN103219324A (zh) * 2012-01-18 2013-07-24 刘胜 堆叠式半导体芯片封装结构及工艺
US20140103527A1 (en) * 2012-03-23 2014-04-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units
US20150206848A1 (en) * 2014-01-23 2015-07-23 Nvidia Corporation System, method, and computer program product for a cavity package-on-package structure
US20160099205A1 (en) * 2014-10-06 2016-04-07 Heung Kyu Kwon Package on package and computing device including the same
US20160338202A1 (en) * 2015-05-11 2016-11-17 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8536695B2 (en) * 2011-03-08 2013-09-17 Georgia Tech Research Corporation Chip-last embedded interconnect structures
US9698123B2 (en) * 2011-09-16 2017-07-04 Altera Corporation Apparatus for stacked electronic circuitry and associated methods
KR101514539B1 (ko) * 2013-08-29 2015-04-22 삼성전기주식회사 전자부품 내장기판
KR102154039B1 (ko) 2013-12-23 2020-09-09 에스케이하이닉스 주식회사 접속 조인트부의 크랙이 억제된 칩 내장형 패키지
SG11201704027PA (en) * 2014-12-16 2017-06-29 Intel Corp Electronic assembly that includes stacked electronic devices

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250916A (ja) * 2006-03-17 2007-09-27 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US20110317381A1 (en) * 2010-06-29 2011-12-29 Samsung Electronics Co., Ltd. Embedded chip-on-chip package and package-on-package comprising same
KR20130042936A (ko) * 2011-10-19 2013-04-29 에스케이하이닉스 주식회사 칩 캐리어, 이를 이용한 반도체 칩, 반도체 패키지, 및 그 제조방법들
CN103219324A (zh) * 2012-01-18 2013-07-24 刘胜 堆叠式半导体芯片封装结构及工艺
US20140103527A1 (en) * 2012-03-23 2014-04-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units
US20150206848A1 (en) * 2014-01-23 2015-07-23 Nvidia Corporation System, method, and computer program product for a cavity package-on-package structure
US20160099205A1 (en) * 2014-10-06 2016-04-07 Heung Kyu Kwon Package on package and computing device including the same
US20160338202A1 (en) * 2015-05-11 2016-11-17 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022016470A1 (zh) * 2020-07-23 2022-01-27 华为技术有限公司 一种芯片封装结构、电子设备

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