CN109390315A - 电路板和使用其的半导体封装 - Google Patents
电路板和使用其的半导体封装 Download PDFInfo
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- CN109390315A CN109390315A CN201810908328.1A CN201810908328A CN109390315A CN 109390315 A CN109390315 A CN 109390315A CN 201810908328 A CN201810908328 A CN 201810908328A CN 109390315 A CN109390315 A CN 109390315A
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
公开电路板和使用其的半导体封装。所述电路板包括:包括纤维层的至少一个预浸料,所述纤维层是用排列在第一方向上的多根第一纤维和排列在与所述第一方向基本上垂直的第二方向上的多根第二纤维编织的;和在所述至少一个预浸料的相反的表面的至少一个上的电路层。所述至少一个预浸料具有比在所述第二方向上的长度大的在所述第一方向上的长度,所述多根第一纤维各自由纬纱形成或包括纬纱,和所述多根第二纤维各自由经纱形成或包括经纱。
Description
对相关申请的交叉引用
本申请要求对韩国知识产权局于2017年8月14日提交的韩国专利申请No.10-2017-0103228的优先权,将其公开内容全部引入本文中作为参考。
背景技术
本发明构思涉及电路板和使用其的半导体封装(封装体,package)。
通常,半导体封装可通过将安装在印刷电路板(PCB)上的半导体芯片用密封剂包围和将所述半导体芯片切割成单独的封装单元而获得。由于在PCB、半导体芯片、和密封剂的热膨胀系数之间的差异,在半导体封装的制造过程中施加的热可导致半导体封装的翘曲(warpage)。近来,随着PCB和密封剂在厚度方面已经减小,在PCB中可发生的翘曲程度可显著增加。
发明内容
本发明构思的一个方面可提供具有减小的翘曲的电路板、和使用其的半导体封装。
根据本发明构思的一个方面,电路板可包括:包括纤维层的至少一个预浸料(预浸料坯,预制板,prepreg),所述纤维层是用排列在第一方向上的多根第一纤维和排列在与所述第一方向基本上垂直的第二方向上的多根第二纤维编织(织成,weave)的;和在所述至少一个预浸料的相反的表面的至少一个上的电路层,其中所述至少一个预浸料可具有比在所述第二方向上的长度大的在所述第一方向上的长度,所述多根第一纤维各自可由纬纱形成或包括纬纱,和所述多根第二纤维各自可由经纱形成或包括经纱。
根据本发明构思的一个方面,电路板可包括:包括第一纤维层的至少一个第一预浸料,所述第一纤维层是用排列在第一方向上的多根第一纤维和排列在与所述第一方向基本上垂直的第二方向上的多根第二纤维编织的;包括第二纤维层的至少一个第二预浸料,所述第二纤维层是用排列在所述第一方向上的多根第三纤维和排列在所述第二方向上的多根第四纤维编织的;在所述至少一个第一预浸料或所述至少一个第二预浸料的相反的表面的至少一个上的电路层,其中所述至少一个第一预浸料或所述至少一个第二预浸料可具有比在所述第二方向上的长度大的在所述第一方向上的长度,所述多根第一纤维各自可由纬纱形成或包括纬纱,所述多根第二纤维各自可由经纱形成或包括经纱,所述多根第三纤维各自可由经纱形成或包括经纱,和所述多根第四纤维各自可由纬纱形成或包括纬纱。
根据本发明构思的一个方面,半导体封装可包括:至少一个半导体芯片;具有第一表面和相反的第二表面的封装基板,所述第一表面具有所述至少一个半导体芯片安装在其中的第一区域和在所述第一区域外部的第二区域;和将在所述封装基板的所述第一表面上的所述至少一个半导体芯片包封的模制品(molding),其中所述封装基板可包括:包括纤维层的至少一个预浸料,所述纤维层是用排列在第一方向上的多根第一纤维和排列在与所述第一方向基本上垂直的第二方向上的多根第二纤维编织的;和设置在所述至少一个预浸料的相反的表面的至少一个上的电路层,其中所述多根第一纤维各自可由纬纱形成或包括纬纱,所述多根第二纤维各自可由经纱形成或包括经纱,和所述第一区域具有在所述第一方向上延伸的(细长的,elongated)形状。
根据本发明构思的一个方面,半导体封装可包括:至少一个半导体芯片,和具有所述至少一个半导体芯片安装在其中的区域的封装基板,其中所述封装基板包括包含纤维层的至少一个预浸料,所述纤维层是用各自由纬纱形成或包括纬纱的多根第一纤维和各自由经纱形成或包括经纱的多根第二纤维编织的,和所述至少一个半导体芯片安装在其中的所述区域可具有在所述多根第一纤维的长度方向上延伸的形状。
附图说明
由当结合附图考虑时的以下详细描述,将更清楚地理解本公开内容的以上和其它方面、特征和优点,其中:
图1为根据实例实施方式的半导体封装的示意性透视图;
图2为所述半导体封装在图1的方向I上的投影平面图;
图3为沿着图2的线II-II'所取的横截面图;
图4为图3的区域A的放大图;
图5为说明根据实例实施方式的预浸料(PPG)的编织方向的图;
图6A和6B为说明在基板上半导体芯片可安装在其中的区域的图;
图7A为说明根据实例实施方式的PPG的堆叠方向的图;
图7B为图7A的变型实例;
图8A和8B为根据实例实施方式和对比例实施方式的半导体封装的平面图;
图9A和9B为说明根据实例实施方式和对比例实施方式的半导体封装的翘曲的形状的图;
图10A和10B为说明根据实例实施方式和对比例实施方式的半导体封装的翘曲的方向的横截面图;
图11为其中比较根据实例实施方式和对比例实施方式的半导体封装的翘曲的程度的图;
图12为其中比较根据实例实施方式和对比例实施方式的半导体封装的翘曲的尺寸(大小)的图;和
图13和14为说明根据实例实施方式的使用电路板制造图1的半导体封装的主要(primary)制造过程的示意性平面图。
具体实施方式
在下文中,将参照附图详细地描述本发明构思的实例实施方式。如本文中使用的,表述“和/或”包括相关列举项目的一个或多个的任意和全部组合。
图1为根据实例实施方式的半导体封装的示意性透视图。图2为所述半导体封装在图1的方向I上的投影平面图。图3为沿着图2的线II-II'所取的横截面图。图4为图3的区域A的放大图。图5为说明根据实例实施方式的预浸料(PPG)的编织方向的图。
参照图1,根据实例实施方式的半导体封装10可包括封装基板100、安装在封装基板100上的第一和第二半导体芯片堆200和300、和覆盖第一和第二半导体芯片堆200和300的模制品600。半导体封装10可进一步包括设置在其下表面上的外部连接端子700。一种实例实施方式说明通过电线501至504(图2)连接至封装基板100的第一和第二半导体芯片堆200和300作为实例。然而,本发明构思不限于此。第一和第二半导体芯片堆200和300也可在没有电线的情况下直接连接至封装基板100。此外,外部连接端子700可包括焊球、焊垫(solder pad)、焊盘(solder land)、金属凸起、或柱子的任一种。在本实例实施方式中,外部连接端子700可为焊球。
参照图2至4,封装基板100可包括电路层130以及与电路层130形成堆叠结构的第一和第二预浸料110和120。封装基板100可具有设置在其至少一个表面上以保护封装基板100的外部表面的绝缘树脂层140,和可进一步包括用于将电线501至504结合到第一和第二半导体芯片堆200和300的连接垫(pad)131a。
参照图3,封装基板100可具有第一和第二半导体芯片堆200和300可安装在其上的第一表面S1、和与第一表面S1相反的第二表面S2。参照图6A,封装基板100的第一表面S1可具有第一和第二半导体芯片堆200和300可安装在其中的第一区域CA1和CA2、以及在第一区域CA1和CA2外部或者围绕第一区域CA1和CA2的第二区域PA1。封装基板100可为刚性印刷电路板、柔性印刷电路板、或刚性-柔性印刷电路板。封装基板100可包括单层印刷电路板或多层印刷电路板。
电路层130可由导电材料例如铜箔形成或者包括导电材料例如铜箔,且可包括分别设置在第一和第二预浸料110和120上的外部电路层131和133、以及设置在第一和第二预浸料110和120之间的内部电路层132。
第一和第二预浸料110和120可通过如下形成:用环氧树脂等浸渍具有织物片形状的纤维层,例如用玻璃纤维纱编织的玻璃纤维织物,和将所述纤维层与环氧树脂一起热压。然而,本发明构思不限于此。根据实例实施方式,也可应用用碳纤维纱编织的具有织物片形状的纤维层。所述预浸料可包括多个预浸料,所述多个预浸料可在封装基板100的厚度方向上堆叠。在一种实例实施方式中,所述预浸料可包括第一和第二预浸料110和120。然而,本发明构思不限于此。所述预浸料可包括单层的预浸料,且也可包括三层或更多层的预浸料。此外,第一和第二预浸料110和120的环氧树脂可包括填料例如氧化铝或二氧化硅,以调节封装基板100的热膨胀系数(CTE)。
图5为第一预浸料110中包括的玻璃织物的编织排列或类型的图。所述玻璃织物可通过编织排列在第一方向D1上的多根第一纤维111和排列在第二方向D2上的多根第二纤维112而形成。第一和第二纤维111和112可为以上描述的玻璃纤维纱,其各自可包括一束或多根丝(filament)111a或112a,例如,长玻璃纤维。如图5中所示,第一和第二纤维111和112可在一对一(one-on-one)的基础上向上和向下彼此交叉。例如,第一纤维111之一可在如下之间交替:在第二纤维112之一上方和在第二纤维112的相邻的一根下方。同样地,第二纤维112之一可在如下之间交替:在第一纤维111之一上方和在第一纤维111的相邻的一根下方。然而,本发明构思不限于此。第一和第二纤维111和112也可以成组的第一和第二纤维111和112来彼此交叉。
第一纤维111可由纬纱形成或包括纬纱且第二纤维112可由经纱形成或包括经纱,使得纬纱可排列在玻璃织物的第一方向D1上且经纱可排列在玻璃织物的第二方向D2上。在下文中,纬纱可排列在其上的方向可被定义为纬纱方向TD且经纱可排列在其上的方向可被定义为经纱方向MD。
第一和第二纤维111和112可被编织成具有以矩阵排列的多个交叉区域IA。在编织过程中,第二纤维112例如经纱可在被比对于第一纤维111例如纬纱所使用的拉伸力大的拉伸力牵拉(拉拽)的同时被编织。因此,第二纤维112各自的宽度W2可小于第一纤维111各自的宽度W1。此外,经纱可被与对于纬纱所使用的拉伸力相比相对高的拉伸力牵拉。因此,即使当经纱被加热时,经纱各自的宽度的增加也可小于纬纱各自的宽度的增加。这可导致纬纱的CTE大于经纱的CTE。因此,当将包括用所述纬纱和经纱编织的玻璃织物的所述预浸料加热至高温时,所述预浸料在纬纱可排列在其上的方向上的宽度的增加可大于所述预浸料在经纱可排列在其上的方向上的宽度的增加。
在半导体封装10中可发生的翘曲可受封装基板100的在纬纱方向TD和经纱方向MD上的CTE之间的这样的差异影响。通常,半导体封装可经历加热和冷却例如模塑和固化、在附着焊球之后的冷却、或在安装半导体芯片之后的冷却。当所述半导体封装经历这样的过程时,由于其CTE非均匀性,翘曲可发生在所述半导体封装中。此外,在所述半导体封装的制造过程期间,所述半导体芯片可被安装在所述半导体封装中,同时翘曲。当所述半导体封装和所述半导体芯片在不同的方向上翘曲时,所述半导体封装的耐久性可劣化。因此,为了改善或提高所述半导体封装的耐久性,即使当翘曲发生时也容许所述半导体封装和所述半导体芯片在相同的方向上翘曲可为有利的。在一种实例实施方式中,可调节半导体封装10的封装基板100的纬纱方向TD和经纱方向MD的布置以减小半导体封装10的翘曲和进一步地即使当翘曲发生时也容许半导体封装10和半导体芯片在相同的方向上翘曲。在下文中,将主要描述用于在形成模制品的过程中减小在所述半导体封装中可发生的翘曲的构造。减小在其它过程中可发生的翘曲也可通过与在减小在形成模制品的过程中可发生的翘曲时使用的构造类似的构造进行。为了简洁,将省略在这样的其它过程中的构造的描述以避免重复描述。
第一和第二纤维111和112可设置成使得在交叉区域IA中的第一纤维111的宽度W1可为在交叉区域IA中的第二纤维112的宽度W2的1.1或更多倍大。结果,在纬纱方向TD上的CTE可大于在经纱方向MD上的CTE。在另一实例实施方式中,第一和第二纤维111和112可设置成使得其宽度W1和W2可基本上相同。因此,交叉区域IA可为正方形的或基本上为正方形的。这样的布置也可通过调节分别形成第一和第二纤维111和112的第一和第二丝111a和112a的数量而获得。例如,形成第二纤维112的第二丝112a的数量可大于形成第一纤维111的第一丝111a的数量,且因此第一和第二纤维111和112可设置成使得第一纤维111的宽度W1可与第二纤维112的宽度W2基本上相同。结果,在纬纱方向TD和经纱方向MD上的CTE之间的差异可减小。
第一纤维111可以第一距离W3彼此间隔开且可彼此平行地延伸,和第二纤维112可以第二距离W4彼此间隔开且可彼此平行地延伸。第一和第二纤维111和112可也可设置成使得第一距离W3可小于或短于第二距离W4。
当所述预浸料包括多个预浸料时,所述预浸料各自的纬纱方向TD和经纱方向MD可彼此相同或者可为不同的。图7A和7B说明预浸料各自包括第一和第二预浸料110和120(或120a)作为实例。图7A说明其纬纱方向TD和经纱方向MD可彼此相同的第一和第二预浸料110和120。第一和第二预浸料110和120可设置成使得其对应区域可具有基本上相同的CTE。图7B说明其纬纱方向TD和经纱方向MD可彼此不同的第一和第二预浸料110和120a。在第一和第二预浸料110和120a的CTE之间的差异可被补偿,因此减小封装基板100的CTE非均匀性。
参照图2和3,安装在封装基板100上的第一半导体芯片堆200可通过堆叠多个半导体芯片210和220而形成,和安装在封装基板100上的第二半导体芯片堆300可通过堆叠多个半导体芯片310和320而形成。第一和第二半导体芯片堆200和300可通过裸片(管芯,die)粘合膜(DAF)401结合至封装基板100。此外,包括在第一半导体芯片堆200中的半导体芯片210和220以及包括在第二半导体芯片堆300中的半导体芯片310和320各自可通过DAF 402结合。
半导体芯片210、220、310、和320各自可包括存储(存储器)芯片或应用处理器。在一种实例实施方式中,第一或第二半导体芯片堆200或300可包括其中存储芯片可堆叠在应用处理器上的构造。半导体芯片210、220、310、和320可例如使用电线501至504电连接至封装基板100的连接垫131a。电线501至504可包括铜(Cu)、金(Au)、或铝(Al)。
参照图6A,封装基板100可具有第一和第二半导体芯片堆200和300可安装在其中的第一区域CA1和CA2、以及在第一区域CA1和CA2外部或者围绕第一区域CA1和CA2的第二区域PA1。根据第一和第二半导体芯片堆200和300的数量,第一和第二半导体芯片堆200和300可安装在其中的第一区域CA1和CA2可包括多个分割的区域CA1和CA2。分割的区域CA1和CA2可具有彼此基本上相同的面积,和可在第二方向D2上延伸成彼此平行的。在一种实例实施方式中,第一区域CA1和CA2可包括两个分割的区域。
第一区域CA1和CA2可设置成使得总的区域CA1+CA2的长度方向WB1+WB2可与封装基板100的纬纱方向TD相同。总的区域CA1+CA2的长度尺寸WB1+WB2可在封装基板100的纬纱方向TD上延伸。第一区域CA1和CA2的总的区域的长度方向或尺寸可指的是第一区域CA1和CA2的组合的长度方向或尺寸WB1+WB2,而不是半导体芯片210、220、310、和320可安装在其中的第一区域CA1和CA2各自的长度方向或尺寸。如图6A中所示,第一和第二半导体芯片堆200和300可安装在其中的第一区域CA1和CA2的一个方向或尺寸WD可小于其它方向或尺寸WB1和WB2之和。因此,所述其它方向或尺寸WB1和WB2可对应于第一和第二半导体芯片堆200和300可安装在其中的第一区域CA1和CA2的长度方向或尺寸,且所述一个方向或尺寸WD可对应于第一区域CA1和CA2的宽度方向或尺寸。
封装基板100的第一和第二半导体芯片堆200和300可安装在其中的第一区域CA1和CA2可由于第一和第二半导体芯片堆200和300而具有比第二区域PA1的CTE相对小的CTE。因此,其中具有安装在其中的第一和第二半导体芯片堆200和300的第一区域CA1和CA2的比率在封装基板100的第一和第二方向D1和D2两者上都可为高的封装基板100的一部分的CTE可比剩余部分的CTE相对小。
因此,封装基板100的纬纱方向TD可被定义为在其上具有安装在其中的第一和第二半导体芯片堆200和300的区域的比率可为高的方向,且封装基板100的经纱方向MD可被定义为在其上具有安装在其中的第一和第二半导体芯片堆200和300的区域的比率可为低的方向。结果,由于第一区域CA1和CA2具有比第二区域PA1的CTE相对小的CTE而可发生的半导体封装10的CTE非均匀性可减小。此外,由于半导体封装10的CTE非均匀性而可发生的半导体封装10的翘曲也可减小。图6B为图6A的变型实例,且说明安装在封装基板100a上的半导体芯片堆200a作为实例。封装基板100a的纬纱方向TD可对应于或被定义为半导体芯片堆200a可安装在其中的区域CA3的长度方向或尺寸WCL,且封装基板100a的经纱方向MD可对应于或被定义为半导体芯片堆200a可安装在其中的区域CA3的宽度方向或尺寸WCS,以减小半导体封装的CTE非均匀性,因此减小所述半导体封装的翘曲。
参照图1,模制品600可设置在封装基板100上以覆盖第一和第二半导体芯片堆200和300各自的上表面和侧表面。模制品600可覆盖电线501至504。在一种实例实施方式中,模制品600可由包括环氧模塑料(EMC)的材料形成或者包含包括环氧模塑料(EMC)的材料。
在形成和固化模制品600的过程中,由于在模制品600的CTE和封装基板100的CTE之间的差异,翘曲可发生在半导体封装10中。通常,在将半导体封装10冷却用于固化半导体封装10的过程中,模制品600收缩的尺寸(或模制品600收缩的量)可大于封装基板100收缩的尺寸(或封装基板100收缩的量)。因此,半导体封装10的周边区域可向下弯曲。在一种实例实施方式中,可减小在模制品600和封装基板100的CTE之间的差异以减少半导体封装10的翘曲,和即使当翘曲发生在半导体封装10中时,模制品600也可被容许在与半导体芯片可翘曲的方向相同的方向上翘曲,因此提高半导体封装10的耐久性。这将在下面描述。
在具有上述结构的半导体封装10中,第一和第二半导体芯片堆200和300可安装在其中的整个区域的长度方向或尺寸可对应于或被定义为封装基板100的纬纱方向TD。封装基板100的第一和第二半导体芯片堆200和300可安装在其中的部分可具有比封装基板100的剩余部分相对小的CTE。因此,第一和第二半导体芯片堆200和300可安装在其中的所述整个区域的延伸部分可设置在其中CTE可相对高的纬纱方向TD上,以提高在半导体封装10的各区域的CTE之间的平衡,因此降低可发生在半导体封装10中的翘曲的尺寸。在下文中,将描述与对比例实施方式形成对照的根据实例实施方式的半导体封装的效果。
参照图8A至12,可比较根据实例实施方式和对比例实施方式的半导体封装在高温下的翘曲。
图8A和8B为根据实例实施方式和对比例实施方式的半导体封装的平面图。图9A和9B为说明根据实例实施方式和对比例实施方式的半导体封装的翘曲的形状的图。图10A和10B为说明根据实例实施方式和对比例实施方式的半导体封装的翘曲的方向的横截面图。图11为其中比较根据实例实施方式和对比例实施方式的半导体封装的翘曲的程度的图。图12为其中比较根据实例实施方式和对比例实施方式的半导体封装的翘曲的尺寸的图。
对比例实施方式可在如下方面与实例实施方式不同:可采用其中根据实例实施方式的封装基板100的纬纱方向TD和经纱方向MD可被颠倒的封装基板100REF。
因此,如图8B中所示,在根据实例实施方式的半导体封装中,封装基板100的经纱方向MD可被定义为具有安装在其上的第一和第二半导体芯片堆200和300的封装基板100的部分在其上可相对小的方向,例如,在其上CTE可相对高的方向CTEa,且封装基板100的纬纱方向TD可被定义为在其上CTE可相对小的方向CTEb。相反,如图8A中所示,对比例实施方式可在如下方面与实例实施方式不同:封装基板100的纬纱方向TD可被定义为具有安装在其上的第一和第二半导体芯片堆200和300的封装基板100的部分在其上可相对小的方向,例如,在其上CTE可相对高的方向CTEa上。
参照图9A和10A,在根据对比例实施方式的半导体封装中,封装基板100REF的纬纱方向TD可被定义为在其上CTE可相对高的方向CTEa上,使得在其上CTE可相对高的方向可相当于封装基板100REF的在其上CTE可相对高的部分。因此,如图10A中所示,在冷却模制品600的过程中,封装基板100REF可通过其收缩的力F1可大于或超过模制品600可通过其收缩的力F2,使得翘曲WD2可从整个半导体封装10a向下发生。翘曲WD2可在与可发生在第一半导体芯片堆200中的翘曲WD1的方向相反的方向上发生,这可导致半导体封装10a的耐久性劣化。参考符号CL为表示其中翘曲不发生的半导体封装10a的参考线。
相反,参照图9B和10B,在根据实例实施方式的半导体封装中,封装基板100的经纱方向MD可被定义为在其上CTE可相对高的方向CTEa,使得在其上CTE可相对高的方向可不相当于封装基板100的在其上CTE可相对高的部分。因此,如图10B中所示,模制品600可通过其收缩的力F2可大于或超过封装基板100可通过其收缩的力F1,使得翘曲WD3可从整个半导体封装10向上发生。翘曲WD3可在与可发生在第一半导体芯片堆200中的翘曲WD1的方向相同的方向上发生,这可导致与对比例实施方式相比,半导体封装10的耐久性改善。
图11为其中施加至实例实施方式G1和对比例实施方式REF的温度和在所述温度下的翘曲的平均值(μm)可按制造过程顺序而排列的图。在对比例实施方式REF中,当温度从240℃升高至260℃时,翘曲可快速增加,且直至温度降至室温(30℃),翘曲可继续被保持。相反,在相同的温度下,实例实施方式G1的翘曲可减小。下表1说明图11的在实例实施方式G1和对比例实施方式REF中在各温度下的翘曲的平均值。与对比例实施方式REF的翘曲相比,实例实施方式G1的翘曲可减小。
[表1]
图12为其中在高温状态下的施加至实例实施方式G1和对比例实施方式REF的温度和在所述温度下显著增加的翘曲值可按制造过程顺序而排列的图。在整个高温范围内,对比例实施方式REF的翘曲的绝对值可大于实例实施方式G1的翘曲的绝对值,且特别地,从260℃起,可保持在实例实施方式G1和对比例实施方式REF中的翘曲的绝对值之间的约20μm的差异。下表2说明在整个制造过程中在图12的实例实施方式G1和对比例实施方式REF中在各温度处的显著增加的翘曲值。与对比例实施方式REF的显著增加的翘曲值相比,实例实施方式G1的显著增加的翘曲值可减小。
[表2]
温度(℃) | REF(μm) | G1(μm) |
30 | 55 | 44 |
100 | 43 | 49 |
150 | 45 | 63 |
180 | 43 | 53 |
200 | 43 | 50 |
220 | 47 | 52 |
240 | 56 | 48 |
260 | 72 | 53 |
240 | 59 | 38 |
220 | 50 | 31 |
200 | 41 | 25 |
180 | 37 | 27 |
150 | 40 | 38 |
100 | 44 | 44 |
30 | 111 | 75 |
在下文中,将描述根据实例实施方式的电路板和使用其的半导体封装的制造过程。图13和14为说明根据实例实施方式的使用电路板制造图1的半导体封装的主要制造过程的示意性平面图。可提供根据实例实施方式的电路板以制造以上描述的封装基板。所述半导体封装可通过如下制造:在电路板上安装半导体芯片堆,在其上形成模制品,和将所述半导体芯片堆分割成单独的半导体芯片。上述封装基板可对应于所述电路板的分割部分(division)。因此,将省略与电路板的描述的封装基板的描述相同的描述以避免重复描述。
首先参照图13,可提供电路板P以制造半导体封装的封装基板。电路板P可具有其中可堆叠至少一个预浸料和电路层的结构。所述预浸料可通过如下形成:用环氧树脂等浸渍具有织物片形状的纤维层例如用玻璃纤维纱编织的玻璃纤维织物,和将所述纤维层与所述环氧树脂一起热压。
详细地,如图13中所示,电路板P可具有在长度方向PL上延伸的板的形状。如以上对于封装基板所描述的,电路板P可包括至少一个预浸料,所述预浸料可包括用排列在电路板P的长度方向PL上的多根第一纤维111和排列在电路板P的与长度方向PL基本上垂直的宽度方向PS上的多根第二纤维112编织的纤维层。第一纤维111各自可由纬纱形成或包括纬纱,和第二纤维112各自可由经纱形成或包括经纱。因此,在电路板P中,长度方向PL可对应于或被定义为纬纱方向TD,且宽度方向PS可对应于或被定义为经纱方向MD。
与以上对于封装基板描述的那些类似,第一纤维111和第二纤维112可被编织成具有以矩阵排列的多个交叉区域IA。由于第一纤维111可由纬纱形成或包括纬纱且第二纤维112可由经纱形成或包括经纱,因此第一纤维111的宽度W1可大于第二纤维112的宽度W2。因此,在交叉区域IA的每一个中,交叉区域IA在长度方向PL上的尺寸可对应于第二纤维112的宽度W2,且交叉区域IA在宽度方向PS上的尺寸可对应于第一纤维111的宽度W1,使得交叉区域IA在长度方向PL上的尺寸可小于交叉区域IA在宽度方向PS上的尺寸。
此外,如以上对于封装基板所描述的,电路层可设置在预浸料的相反的表面的至少一个上。
随后,如图14中所示,第一和第二半导体芯片堆200和300可安装在电路板P的单独的半导体芯片安装区域P2的每一个中,使得第一和第二半导体芯片堆200和300可安装在其中的区域的组合的长度方向CTEb可对应于或被定义为电路板P的纬纱方向TD。如上所述,第一和第二半导体芯片堆200和300可安装在其中的区域可具有比在所述区域外面的剩余区域的CTE相对小的CTE。因此,当第一和第二半导体芯片堆200和300可安装在其中的所述区域的组合的长度方向CTEb被定义为纬纱方向TD时,在其上电路板P的CTE可相对高的纬纱方向TD上增加的电路板P的宽度可减小。
在半导体封装制造过程期间,在加热和冷却例如模塑和固化、在附着焊球之后的冷却、或在安装半导体芯片之后的冷却的过程中,电路板可暴露于高温。因此,电路板可热膨胀。与在其上电路板的CTE可相对低的方向上的电路板的宽度相比,在其上电路板的CTE可相对高的方向上的电路板的宽度可进一步增加。因此,较大量的翘曲可发生于在其上电路板的CTE可相对高的方向上。在一种实例实施方式中,较大量的具有相对低的CTE的半导体芯片安装区域可设置在具有相对高的CTE的纬纱方向TD上,因此减小在具有相对高的CTE的方向和具有相对低的CTE的方向上的CTE之间的差异。此外,即使当翘曲发生在所述半导体封装中时,所述半导体封装也可被容许如对于半导体芯片那样向上翘曲,因此减小可发生在半导体芯片堆中的翘曲的非均匀性。
随后,可将模制品施加至第一和第二半导体芯片堆200和300可安装在其上的封装基板100的表面以覆盖所述表面,且可将电路板P划片(dice)成单独的半导体芯片安装区域P2。结果,可制造图1的半导体封装。
如以上所阐述的,根据本发明构思的实例实施方式,电路板和使用其的半导体封装可减小可在其制造过程中发生的翘曲。
尽管已经在上面展示和描述了实例实施方式,但是本领域技术人员将明晰,在不背离如由所附权利要求所限定的本发明构思的范围的情况下,可进行修改和变型。
Claims (23)
1.电路板,包括:
包括纤维层的至少一个预浸料,所述纤维层是由排列在第一方向上的多根第一纤维和排列在与所述第一方向基本上垂直的第二方向上的多根第二纤维编织的;和
在所述至少一个预浸料的相反的表面的至少一个上的电路层,
其中所述至少一个预浸料具有比在所述第二方向上的长度大的在所述第一方向上的长度,所述多根第一纤维各自包括纬纱,和所述多根第二纤维各自包括经纱。
2.如权利要求1所述的电路板,其中所述至少一个预浸料在所述第一方向上的热膨胀系数大于所述至少一个预浸料在所述第二方向上的热膨胀系数。
3.如权利要求1所述的电路板,其中所述多根第一纤维和所述多根第二纤维各自包括玻璃纤维纱。
4.如权利要求1所述的电路板,其中所述至少一个预浸料包括多个预浸料,所述多个预浸料各自的所述多根第一纤维各自包括纬纱,和所述多个预浸料各自的所述多根第二纤维各自包括经纱。
5.如权利要求1所述的电路板,其中所述多根第一纤维和所述多根第二纤维被编织成具有以矩阵排列的多个交叉区域,和所述多个交叉区域各自具有比在所述第二方向上的尺寸小的在所述第一方向上的尺寸。
6.如权利要求1所述的电路板,其中所述多根第一纤维各自的宽度大于所述多根第二纤维各自的宽度。
7.如权利要求6所述的电路板,其中所述多根第一纤维各自的宽度为所述多根第二纤维各自的宽度的1.1或更多倍大。
8.如权利要求1所述的电路板,其中所述多根第一纤维各自和所述多根第二纤维各自包括多根丝,和所述多根第二纤维各自的所述多根丝的数量大于所述多根第一纤维各自的所述多根丝的数量。
9.如权利要求1所述的电路板,其中所述多根第一纤维以第一距离相互间隔开并且彼此平行延伸,所述多根第二纤维以第二距离相互间隔开并且彼此平行延伸,和所述第一距离小于所述第二距离。
10.电路板,包括:
包括第一纤维层的至少一个第一预浸料,所述第一纤维层是用排列在第一方向上的多根第一纤维和排列在与所述第一方向基本上垂直的第二方向上的多根第二纤维编织的;
包括第二纤维层的至少一个第二预浸料,所述第二纤维层是用排列在所述第一方向上的多根第三纤维和排列在所述第二方向上的多根第四纤维编织的;
在所述至少一个第一预浸料或所述至少一个第二预浸料的相反的表面的至少一个上的电路层,
其中所述至少一个第一预浸料或所述至少一个第二预浸料具有比在所述第二方向上的长度大的在所述第一方向上的长度,所述多根第一纤维各自包括纬纱,所述多根第二纤维各自包括经纱,所述多根第三纤维各自包括经纱,和所述多根第四纤维各自包括纬纱。
11.半导体封装,包括:
至少一个半导体芯片;
具有第一表面和相反的第二表面的封装基板,所述第一表面具有所述至少一个半导体芯片安装在其中的第一区域和与所述第一区域不同的第二区域;和
将在所述封装基板的所述第一表面上的所述至少一个半导体芯片包封的模制品,
其中所述封装基板包括:
包括纤维层的至少一个预浸料,所述纤维层是用排列在第一方向上的多根第一纤维和排列在与所述第一方向基本上垂直的第二方向上的多根第二纤维编织的;和
设置在所述至少一个预浸料的相反的表面的至少一个上的电路层,
其中所述多根第一纤维各自包括纬纱,所述多根第二纤维各自包括经纱,和所述第一区域具有在所述第一方向上延伸的形状。
12.如权利要求11所述的半导体封装,其中所述至少一个预浸料在所述第一方向上的热膨胀系数大于所述至少一个预浸料在所述第二方向上的热膨胀系数。
13.如权利要求11所述的半导体封装,其中所述第一区域包括在所述第一方向上间隔开的多个区域。
14.如权利要求13所述的半导体封装,其中所述多个区域各自具有基本上相同的面积。
15.如权利要求13所述的半导体封装,其中所述多个区域在所述第二方向上彼此平行。
16.如权利要求11所述的半导体封装,其中所述至少一个预浸料包括具有在所述多根第一纤维和所述多根第二纤维之间涂覆和固化的树脂的具有织物片形状的纤维层,和所述纤维层是与所述树脂一起热压的。
17.如权利要求11所述的半导体封装,其中所述至少一个预浸料包括多个预浸料,和所述多个预浸料的对应区域具有基本上相同的热膨胀系数。
18.如权利要求11所述的半导体封装,其中所述至少一个预浸料包括多个预浸料,和所述多个预浸料在所述封装基板的厚度方向上堆叠。
19.如权利要求11所述的半导体封装,其中所述模制品包括环氧模塑料。
20.如权利要求11所述的半导体封装,其中:
所述多根第一纤维各自的宽度大于所述多根第二纤维各自的宽度;
所述多根第一纤维各自和所述多根第二纤维各自包括多根丝,和所述多根第二纤维各自的所述多根丝的数量大于所述多根第一纤维各自的所述多根丝的数量;和/或
所述多根第一纤维以第一距离相互间隔开和所述多根第二纤维以第二距离相互间隔开,且所述第一距离小于所述第二距离。
21.半导体封装,包括:
至少一个半导体芯片;
具有所述至少一个半导体芯片安装在其中的区域的封装基板,
其中所述封装基板包括包含纤维层的至少一个预浸料,所述纤维层是用各自包括纬纱的多根第一纤维和各自包括经纱的多根第二纤维编织的,所述至少一个半导体芯片安装在其中的所述区域具有在所述多根第一纤维的长度方向延伸的形状。
22.如权利要求21所述的半导体封装,其中
所述至少一个半导体芯片安装在其中的所述区域包括多个分割的区域,和所述多个分割的区域在所述多根第二纤维的长度方向上彼此平行。
23.如权利要求21所述的半导体封装,其中所述多根第一纤维在所述多根第一纤维的长度方向上的热膨胀系数大于所述多根第二纤维在所述多根第二纤维的长度方向上的热膨胀系数。
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SG10201805407XA (en) | 2019-03-28 |
US20200236778A1 (en) | 2020-07-23 |
DE102018116265A1 (de) | 2019-02-14 |
JP7193930B2 (ja) | 2022-12-21 |
KR20190018590A (ko) | 2019-02-25 |
CN109390315B (zh) | 2024-03-08 |
US20190053371A1 (en) | 2019-02-14 |
KR102419891B1 (ko) | 2022-07-13 |
US10616998B2 (en) | 2020-04-07 |
JP2019036710A (ja) | 2019-03-07 |
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