CN1087492C - 一种半导体器件及其制造工艺 - Google Patents

一种半导体器件及其制造工艺 Download PDF

Info

Publication number
CN1087492C
CN1087492C CN96105708A CN96105708A CN1087492C CN 1087492 C CN1087492 C CN 1087492C CN 96105708 A CN96105708 A CN 96105708A CN 96105708 A CN96105708 A CN 96105708A CN 1087492 C CN1087492 C CN 1087492C
Authority
CN
China
Prior art keywords
mentioned
layer
region
contact
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN96105708A
Other languages
English (en)
Chinese (zh)
Other versions
CN1141510A (zh
Inventor
松本明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1141510A publication Critical patent/CN1141510A/zh
Application granted granted Critical
Publication of CN1087492C publication Critical patent/CN1087492C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CN96105708A 1995-02-21 1996-02-21 一种半导体器件及其制造工艺 Expired - Fee Related CN1087492C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP32226/95 1995-02-21
JP7032226A JP3022744B2 (ja) 1995-02-21 1995-02-21 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
CN1141510A CN1141510A (zh) 1997-01-29
CN1087492C true CN1087492C (zh) 2002-07-10

Family

ID=12353060

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96105708A Expired - Fee Related CN1087492C (zh) 1995-02-21 1996-02-21 一种半导体器件及其制造工艺

Country Status (5)

Country Link
US (2) US5804862A (https=)
JP (1) JP3022744B2 (https=)
KR (1) KR100255412B1 (https=)
CN (1) CN1087492C (https=)
TW (1) TW303491B (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281562B1 (en) * 1995-07-27 2001-08-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device which reduces the minimum distance requirements between active areas
JP3058112B2 (ja) * 1997-02-27 2000-07-04 日本電気株式会社 半導体装置およびその製造方法
JP3641342B2 (ja) * 1997-03-07 2005-04-20 Ｔｄｋ株式会社 半導体装置及び有機ｅｌディスプレイ装置
JP3120750B2 (ja) * 1997-03-14 2000-12-25 日本電気株式会社 半導体装置およびその製造方法
US6146978A (en) * 1998-05-06 2000-11-14 Advanced Micro Devices, Inc. Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance
JP2000012687A (ja) * 1998-06-23 2000-01-14 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6406987B1 (en) * 1998-09-08 2002-06-18 Taiwan Semiconductor Manufacturing Company Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions
US6133105A (en) * 1999-04-27 2000-10-17 United Microelectronics Corp. Method of manufacturing borderless contact hole including a silicide layer on source/drain and sidewall of trench isolation structure
KR100518530B1 (ko) * 1999-06-17 2005-10-04 삼성전자주식회사 보더리스 콘택홀을 갖는 반도체 소자 및 그 제조방법
US6211021B1 (en) * 1999-07-26 2001-04-03 United Microelectronics Corp. Method for forming a borderless contact
JP2001196380A (ja) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6462417B1 (en) * 2000-12-18 2002-10-08 Advanced Micro Devices, Inc. Coherent alloy diffusion barrier for integrated circuit interconnects
KR20030001972A (ko) * 2001-06-28 2003-01-08 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP2003017555A (ja) 2001-06-29 2003-01-17 Hitachi Ltd 半導体集積回路装置およびその製造方法
KR100421048B1 (ko) * 2001-09-07 2004-03-04 삼성전자주식회사 국부배선층을 갖는 반도체 소자 및 그 제조방법
JP2009065176A (ja) * 2008-10-02 2009-03-26 Renesas Technology Corp 半導体装置及びその製造方法
CN103367148B (zh) * 2012-03-29 2016-07-06 中芯国际集成电路制造(上海)有限公司 晶体管及其制造方法
CN103594417A (zh) * 2012-08-13 2014-02-19 中芯国际集成电路制造(上海)有限公司 互连结构的制作方法
JP2015122471A (ja) * 2013-11-20 2015-07-02 マイクロン テクノロジー， インク． 半導体装置およびその製造方法
US9443772B2 (en) 2014-03-19 2016-09-13 Globalfoundries Inc. Diffusion-controlled semiconductor contact creation
US9397181B2 (en) 2014-03-19 2016-07-19 International Business Machines Corporation Diffusion-controlled oxygen depletion of semiconductor contact interface
CN105225944A (zh) * 2014-06-06 2016-01-06 北大方正集团有限公司 一种金属层去除方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224414A (ja) * 1985-03-29 1986-10-06 Toshiba Corp 半導体装置の製造方法
EP0513639A2 (en) * 1991-05-16 1992-11-19 International Business Machines Corporation Semiconductor field effect transistor device and fabrication thereof

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4505333A (en) * 1981-09-02 1985-03-19 Ricks Sr Tom E Methods of and means for low volume wellhead compression hydrocarbon _gas
JPS59204236A (ja) * 1983-05-06 1984-11-19 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS62190847A (ja) * 1986-02-18 1987-08-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
NL8701032A (nl) * 1987-05-01 1988-12-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met interconnecties die zowel boven een halfgeleidergebied als boven een daaraan grenzend isolatiegebied liggen.
US5162262A (en) * 1989-03-14 1992-11-10 Mitsubishi Denki Kabushiki Kaisha Multi-layered interconnection structure for a semiconductor device and manufactured method thereof
JPH03285344A (ja) * 1990-03-31 1991-12-16 Toshiba Corp 半導体装置およびその製造方法
JP3018383B2 (ja) * 1990-04-03 2000-03-13 ソニー株式会社 配線形成方法
US5268329A (en) * 1990-05-31 1993-12-07 At&T Bell Laboratories Method of fabricating an integrated circuit interconnection
JP2570473B2 (ja) * 1990-07-13 1997-01-08 三菱電機株式会社 半導体装置における素子分離方法
EP0469215B1 (en) * 1990-07-31 1995-11-22 International Business Machines Corporation Method of forming stacked tungsten gate PFET devices and structures resulting therefrom
JP3285934B2 (ja) * 1991-07-16 2002-05-27 株式会社東芝 半導体装置の製造方法
EP0529717A3 (en) * 1991-08-23 1993-09-22 N.V. Philips' Gloeilampenfabrieken Method of manufacturing a semiconductor device having overlapping contacts
KR960005248B1 (ko) * 1991-10-24 1996-04-23 마쯔시다덴기산교 가부시기가이샤 반도체기억장치 및 그 제조방법
US5244827A (en) * 1991-10-31 1993-09-14 Sgs-Thomson Microelectronics, Inc. Method for planarized isolation for cmos devices
JP2934353B2 (ja) * 1992-06-24 1999-08-16 三菱電機株式会社 半導体装置およびその製造方法
US5268330A (en) * 1992-12-11 1993-12-07 International Business Machines Corporation Process for improving sheet resistance of an integrated circuit device gate
US5244837A (en) * 1993-03-19 1993-09-14 Micron Semiconductor, Inc. Semiconductor electrical interconnection methods
JPH0714918A (ja) * 1993-06-17 1995-01-17 Oki Electric Ind Co Ltd 半導体素子の製造方法
US5604159A (en) * 1994-01-31 1997-02-18 Motorola, Inc. Method of making a contact structure
US5380671A (en) * 1994-06-13 1995-01-10 United Microelectronics Corporation Method of making non-trenched buried contact for VLSI devices
US5428240A (en) * 1994-07-07 1995-06-27 United Microelectronics Corp. Source/drain structural configuration for MOSFET integrated circuit devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224414A (ja) * 1985-03-29 1986-10-06 Toshiba Corp 半導体装置の製造方法
EP0513639A2 (en) * 1991-05-16 1992-11-19 International Business Machines Corporation Semiconductor field effect transistor device and fabrication thereof

Also Published As

Publication number Publication date
TW303491B (https=) 1997-04-21
JP3022744B2 (ja) 2000-03-21
CN1141510A (zh) 1997-01-29
JPH08227938A (ja) 1996-09-03
US5804862A (en) 1998-09-08
US5972774A (en) 1999-10-26
KR100255412B1 (ko) 2000-05-01

Similar Documents

Publication Publication Date Title
CN1087492C (zh) 一种半导体器件及其制造工艺
KR890004463B1 (ko) 금속 전극 배선막을 가진 반도체 장치
JP4917246B2 (ja) 半導体装置およびその製造方法
US7808019B2 (en) Gate structure
US6274452B1 (en) Semiconductor device having multilayer interconnection structure and method for manufacturing the same
JP4397537B2 (ja) 垂直方向ゲートトランジスタを形成する方法
KR0138914B1 (ko) 박막 저항 소자를 가진 반도체 장치 제조 방법
KR100446459B1 (ko) 반도체 장치 및 그의 제조방법
KR0173458B1 (ko) 반도체집적회로 및 그 제조방법
US5254867A (en) Semiconductor devices having an improved gate
US4916084A (en) Method for manufacturing MOS semiconductor devices
US6504220B2 (en) Semiconductor device
KR100527673B1 (ko) 반도체 소자의 금속배선 형성방법
US6103608A (en) Method of forming a contact window
JP2006339558A (ja) 半導体装置の製造方法
KR100230731B1 (ko) 반도체 디바이스의 콘택 구조 및 그 제조방법
KR970005729B1 (ko) 반도체 장치의 제조방법
JPH1041505A (ja) 半導体装置の製造方法
KR100713927B1 (ko) 반도체 소자의 제조방법
KR100246625B1 (ko) 커패시터와 자기 정렬된 이중 게이트 전극을 갖는 반도체 소자의 제조 방법
JPH05217942A (ja) 半導体装置の製造方法
US20030160282A1 (en) Semiconductor device
KR100367741B1 (ko) 개선된 보더리스 콘택 구조 및 그 제조방법
KR100318273B1 (ko) 반도체 소자의 비트라인 형성방법
US7550372B2 (en) Method of fabricating conductive lines with silicide layer

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: NEC ELECTRONICS TAIWAN LTD.

Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD.

Effective date: 20030328

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20030328

Address after: Kawasaki, Kanagawa, Japan

Patentee after: NEC Corp.

Address before: Tokyo, Japan

Patentee before: NEC Corp.

REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1029164

Country of ref document: HK

C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee