CN108735603A - 晶体管装置及其制造方法 - Google Patents

晶体管装置及其制造方法 Download PDF

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Publication number
CN108735603A
CN108735603A CN201710581416.0A CN201710581416A CN108735603A CN 108735603 A CN108735603 A CN 108735603A CN 201710581416 A CN201710581416 A CN 201710581416A CN 108735603 A CN108735603 A CN 108735603A
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hard mask
interlayer dielectric
metal gates
gate
dielectric
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CN108735603B (zh
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李凱璿
赖柏宇
王圣祯
杨世海
陈燕铭
徐志安
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种晶体管装置及其制造方法。晶体管装置的制造方法包含形成金属栅极在第一层间介电质内、在金属栅极及第一层间介电质上进行处理、选择性成长硬遮罩在金属栅极上，且不从第一层间介电质成长硬遮罩、沉积第二层间介电质在硬遮罩及第一层间介电质上、平坦化第二层间介电质及硬遮罩，以及形成栅极接触插塞穿过硬遮罩，以电性耦合金属栅极。

Description

晶体管装置及其制造方法
技术领域
本揭露是关于一种晶体管及其制造方法，特别是关于一种晶体管的自对准栅极硬遮罩及其制造方法。
背景技术
在鳍式场效晶体管的金属栅极及各自的金属接触插塞的形成中，金属栅极通常为内缩，且由于金属栅极的凹陷而填充硬遮罩至凹陷内。接着，移除硬遮罩的一些部分，以形成接触开口，穿过暴露的金属栅极。形成栅极接触插塞，以连接至金属栅极。
硬遮罩的凹陷导致金属栅极的流失，故须要形成高于最后高度的金属栅极，以补偿失去的高度。金属栅极增加的高度导致用以形成金属栅极的间隙填充的困难。再者，在硬遮罩的蚀刻中，硬遮罩的凹陷受到图案负载效应的困扰，且图案负载效应(pattern-loading effect)导致金属栅极的一些部分较其他金属栅极内缩。
发明内容
本揭露的一态样为一种方法，其是包含形成金属栅极在第一层间介电质内、在金属栅极及第一层间介电质上进行处理、选择性成长硬遮罩在金属栅极上，且不从第一层间介电质成长硬遮罩、沉积第二层间介电质在硬遮罩及第一层间介电质上、平坦化第二层间介电质及硬遮罩，以及形成栅极接触插塞穿过硬遮罩，以电性耦合金属栅极。
本揭露的另一态样为一种方法，其是包含形成金属栅极在第一层间介电质内、内缩第一层间介电质，以使第一层间介电质的顶表面低于金属栅极的顶表面、选择性成长硬遮罩在金属栅极上。硬遮罩包含向上成长的顶部部分，及水平成长的侧壁部分。方法还包含沉积第二层间介电质在硬遮罩及第一层间介电质上、平坦化硬遮罩，使硬遮罩的底部部分维持在覆盖金属栅极。形成栅极接触插塞穿过第二层间介电质，以电性耦合金属栅极。
本揭露的再一态样为一种装置，其是包含第一层间介电质、具有在第一层间介电质内的金属栅极的栅极堆叠、包含与栅极堆叠交叠的第一部分及与第一层间介电质的第一部分交叠的第二部分的硬遮罩。第二层间介电质具有与硬遮罩的侧壁接触的侧壁。第二层间介电质与第一层间介电质的第二部分交叠。栅极接触插塞，穿过硬遮罩，以与栅极堆叠接触。
附图说明
根据以下详细说明并配合附图阅读，使本揭露的态样获致较佳的理解。需注意的是，如同业界的标准作法，许多特征并不是按照比例绘示的。事实上，为了进行清楚讨论，许多特征的尺寸可以经过任意缩放。
图1至图17是绘示根据本揭露一些实施例的在晶体管的形成的中间阶段的透视视图及剖面视图；
图18是绘示根据本揭露一些实施例的形成晶体管及接触插塞的流程图。
具体实施方式
以下揭露提供许多不同实施例或例示，以实施发明的不同特征。以下叙述的成份和排列方式的特定例示是为了简化本揭露。这些当然仅是做为例示，其目的不在构成限制。举例而言，第一特征形成在第二特征之上或上方的描述包含第一特征和第二特征有直接接触的实施例，也包含有其他特征形成在第一特征和第二特征之间，以致第一特征和第二特征没有直接接触的实施例。许多特征的尺寸可以不同比例绘示，以使其简化且清晰。除此之外，本揭露在各种例示中会重复元件符号及/或字母。此重复的目的是为了简化和明确，并不表示所讨论的各种实施例及/或配置之间有任何关系。
再者，空间相对性用语，例如“下方(underlying)”、“在…之下(below)”、“低于(lower)”、“上方(overlying)”、“高于(upper)”等，是为了易于描述附图中所绘示的元素或特征和其他元素或特征的关系。空间相对性用语除了附图中所描绘的方向外，还包含元件在使用或操作时的不同方向。装置可以其他方式定向(旋转90度或在其他方向)，而本文所用的空间相对性描述也可以如此解读。
根据各种例示实施例提供晶体管及其制造方法。根据一些实施例绘示制造晶体管的中间阶段。讨论一些实施例的一些变化。透过各种视图及说明的实施例，类似的参考数字是用于标示类似的元件。在绘示的例示实施例中，鳍式场效晶体管(Fin Field-EffectTransistors，FinFETs)是用以做为解释本揭露的概念的具体例。平面晶体管也可采用本揭露的概念。
图1至图17是绘示根据本揭露一些实施例的在鳍式场效晶体管的形成的中间阶段的剖面视图及透视视图。图1至图16所示的步骤也在图18所示的流程图200中以图表式表现。
图1绘示起始结构的透视视图。起始结构包含晶圆10，其中晶圆10还包含基材20。基材20可为半导体基材，其可为硅基材、硅锗基材或由其他半导体材料形成的基材。基材20可被p型杂质或n型杂质掺杂。形成例如浅沟渠隔离(Shallow Trench Isolation，STI)区域的隔离区域22，以自基材20的顶表面延伸至基材20内。在相邻的浅沟渠隔离区域22之间的基材20的部分是当作半导体条24。根据一些例示实施例，半导体条24的顶表面及浅沟渠隔离区域22的顶表面是实质为与彼此在同一高度。根据本揭露一些实施例，半导体条24是原基材20的部分，因此，半导体条24的材料是与基材20的材料相同。根据本揭露另一些实施例，半导体条24是通过蚀刻在浅沟渠隔离区域22之间的基材20的部分，以形成凹陷，而形成的取代条，并进行磊晶，以在凹陷内再成长其他半导体材料。因此，半导体条24是由与基材20不同的半导体材料所形成。根据一些例示实施例，半导体条24是由硅锗、碳化硅或III-V族化合物半导体材料所形成。
浅沟渠隔离区域22可包含衬氧化层(图未绘示)，其中衬氧化层可为透过基材20的表面层的热氧化所形成的热氧化物。衬氧化层也可为沉积氧化硅层，其是利用例如原子层沉积(Atomic Layer Deposition，ALD)、高密度等离子化学气相沉积(High-DensityPlasma Chemical Vapor Deposition，HDPCVD)或化学气相沉积(Chemical VaporDepostion，CVD)所形成。浅沟渠隔离区域22也可包含在衬氧化层上的介电材料，其中介电材料可为利用流动式化学气相沉积(Flowable Chemical Vapor Deposition，FCVD)、旋转涂布(spin-on coating)或类似方式所形成。
请参阅图2，浅沟渠隔离区域22是内缩，以使半导体条24的顶部部分凸出至高于浅沟渠隔离区域22的剩余部分的顶表面22A，以形成凸出鳍片24’。相应的步骤是绘示于如图18所示的流程图200中的步骤202。可利用干式蚀刻制程进行蚀刻，其中三氟化氮(NF3)及氨(NH3)是被使用为蚀刻气体。在蚀刻制程中，可产生等离子。也可包含氩气。根据本揭露另一些实施例，利用湿式蚀刻制程进行浅沟渠隔离区域22的内缩。蚀刻化学品可包含例如氢氟酸。
请参阅图3，形成虚拟栅极堆叠30在(凸出)鳍片24’的顶表面及侧壁上。相应的步骤是绘示于如图18所示的流程图200中的步骤204。虚拟栅极堆叠30可包含虚拟栅极介电质32及在虚拟栅极介电质上的虚拟栅极电极34。可利用例如多晶硅及其他可使用的材料形成虚拟栅极电极34。每一个虚拟栅极堆叠30也可包含一个(或复数个)在虚拟栅极电极34上的硬遮罩层36。硬遮罩层36可由氮化硅、氮化硅、碳氮化硅或其中的多层所形成。虚拟栅极堆叠30可穿过单一个或复数个凸出鳍片24’及/或浅沟渠隔离区域22。虚拟栅极堆叠30亦具有垂直于凸出鳍片24’的纵向方向的纵向方向。
接着，形成栅极间隙壁38在虚拟栅极堆叠30的侧壁上。根据本揭露一些实施例，栅极间隙壁38是由介电材料(例如氮化硅、碳氮化硅或类似物)所形成，且栅极间隙壁38可具有单一层结构或包含复数个介电层的多层结构。根据本揭露一些实施例，栅极间隙壁38之中是不具有氧原子。
然后，进行蚀刻步骤(之后表示为源极/漏极内缩步骤)，以蚀刻凸出鳍片24’的未被虚拟栅极堆叠30及栅极间隙壁38覆盖的部分，以制得图4所示的结构。内缩步骤可为非等向性蚀刻，因此，直接在鳍片24’的部分下方的虚拟栅极堆叠30及栅极间隙壁38是被保护而不被蚀刻。根据一些实施例，内缩半导体条24的顶表面是低于浅沟渠隔离区域22的顶表面22A。因此，形成凹陷40在浅沟渠隔离区域22之间。凹陷40是位于虚拟栅极堆叠30的相反侧上。
接着，磊晶区域(源极/漏极区域)42是通过选择性成长半导体材料在凹陷40内所形成，以制得图5A所示的结构。相应的步骤是绘示于如图18所示的流程图200中的步骤206。根据一些例示实施例，磊晶区域42包含硅锗或硅。根据制成的鳍式场效晶体管为p型鳍式场效晶体管或n型鳍式场效晶体管，可继续进行磊晶，以原位掺杂p型杂质或n型杂质。举例而言，当制成的鳍式场效晶体管为p型鳍式场效晶体管，可成长硅锗硼(silicon germaniumboron，SiGeB)。相反地，当制成的鳍式场效晶体管为n型鳍式场效晶体管，可成长磷化硅(silicon phosphorous，SiP)或碳磷化硅(silicon carbon phosphorous，SiCP)。根据本揭露另一些实施例，磊晶区域42是由III-V族化合物半导体(例如：GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、前述的组合或其中的多层)所形成。在磊晶区域42完全填充凹陷40后，磊晶区域42开始水平地膨胀，并形成晶面。
在磊晶步骤后，磊晶区域42可进一步布植p型杂质或n型杂质，以形成源极及漏极区域，其可使用类似的数字42表示。根据本揭露另一些实施例，当磊晶区域42已在磊晶以形成源极/漏极区域时原位掺杂p型杂质或n型杂质，则可省略布植步骤。磊晶源极/漏极区域42包含下部分及上部分，其中下部分是形成在浅沟渠隔离区域22内，而上部分是形成在浅沟渠隔离区域22的顶表面上。
图5B是绘示根据本揭露另一些实施例的源极/漏极区域42的形成。根据这些实施例，图3所示的凸出鳍片24’并未内缩，且磊晶区域41是成长在凸出鳍片24’上。磊晶区域41的材料是与图5A所示的磊晶半导体材料42的材料相似，其是取决于制成的鳍式场效晶体管为p型鳍式场效晶体管或n型鳍式场效晶体管。因此，源极/漏极区域42包含凸出鳍片24’及磊晶区域41。进行布植，以布植n型杂质或p型杂质。
图6是绘示接触蚀刻中止层(Contact Etch Stop Layer，CESL)47及层间介电质(Inter-Layer Dielectric，ILD)46形成后的结构的透视视图。相应的步骤是绘示于如图18所示的流程图200中的步骤208。根据一些实施例，可省略接触蚀刻中止层47，而当形成接触蚀刻中止层47，其是由氮化硅、碳氮化硅或类似物所形成。根据本揭露一些实施例，接触蚀刻中止层47的内是不具有氧。接触蚀刻中止层47是利用共形沉积法(例如原子层沉积或化学气相沉积)所形成。层间介电质46可包含介电材料，其是利用例如流动式化学气相沉积、旋转涂布、化学气相沉积或其他沉积方法所形成。层间介电质46也可由含氧介电材料形成，其中含氧介电材料可为以氧化硅为基础的四乙氧基硅烷(tetraethyl orthosilicate，TEOS)氧化物、等离子辅助化学气相沉积(Plasma-Enhanced CVD，PECVD)氧化物(SiO2)、磷硅玻璃(Phospho-Silicate Glass，PSG)、硼硅玻璃(Boro-Silicate Glass，BSG)、硼掺杂磷硅玻璃(Boron-Doped Phospho-Silicate Glass，BPSG)或类似物。可进行例如化学机械研磨(Chemical Mechanical Polish，CMP)或机械研磨(mechanical grinding)的平坦化步骤，以使层间介电质46、虚拟栅极堆叠30及栅极间隙壁38的顶表面彼此在同一高度。
图6所示的结构的剖面视图是绘示于图7，其中剖面视图是从包含图6中的线A-A的垂直面所获得。
接着，如图8及图9所示，包含硬遮罩层36、虚拟栅极电极34及虚拟栅极介电质32的虚拟栅极堆叠是被包含金属栅极及取代栅极介电质的取代栅极堆叠所取代。图8及图9示的剖面视图及后续的剖面视图是同样从包含图6中的线A-A的垂直面所获得。在剖面视图中，绘示浅沟渠隔离区域22的顶表面22A的高度，且半导体鳍片24’是在顶表面22A上。
当形成取代栅极堆叠，首先，以一或复数个蚀刻步骤移除如图7所示的硬遮罩层36、虚拟栅极电极34及虚拟栅极介电质32，以形成图8所示的沟渠/开口48。相应的步骤是绘示于如图18所示的流程图200中的步骤210。凸出半导体鳍片24’的顶表面及侧壁是暴露至沟渠48。
接着，请参阅图9，形成(取代)栅极介电层52，其是延伸至沟渠48(图8)内。根据本揭露一些实施例，栅极介电层52是包含当作是下部分的界面层(Interfacial Layer，IL)54。界面层54是形成在凸出鳍片24’的暴露的表面上。界面层54可包含例如氧化硅层的氧化层，其是透过对凸出鳍片24’进行热氧化、化学氧化制程或沉积制程所形成。栅极介电层52也可包含形成在界面层54上的高k介电层56。高k介电层56包含高k介电材料，例如二氧化铪、氧化镧、氧化铝、二氧化锆、氮化硅或类似物。高k介电材料的介电常数(k值)是高于3.9，且可高于7.0。高k介电层56是在界面层54之上，且可接触界面层54。高k介电层56是形成为共形层，并延伸至凸出鳍片24’的侧壁及栅极间隙壁38的侧壁上。根据本揭露一些实施例，高k介电层56是利用原子层沉积或化学气相沉积所形成。
请继续参阅图9，沉积堆叠层58。堆叠层58内的子层并未分开绘示，在现实状况下，子层彼此是可分辨的。沉积是利用共形沉积法(例如原子层沉积或化学气相沉积)进行，以使堆叠层58(及每一个子层)的垂直部分的厚度与水平部分的厚度是实质上与彼此相等。沉积的栅极介电层52及堆叠层58延伸至沟渠48(图8)内，且是包含在层间介电质46上的一些部分。
堆叠层58可包含扩散阻障层及在扩散阻障层上的一个(或多个)功函数层。扩散阻障层是由氮化钛(titanium nitride，TiN)所形成，其中氮化钛可(或可不)被硅掺杂。功函数层决定栅极的功函数，且包含至少一层或由不同材料所形成的多层。功函数层的材料是根据对应的鳍式场效晶体管为n型鳍式场效晶体管或p型鳍式场效晶体管以进行选择。举例而言，当鳍式场效晶体管为n型鳍式场效晶体管时，功函数层可包含氮化钽(TaN)层及在氮化钽层上的钛铝(TiAl)层。当鳍式场效晶体管为p型鳍式场效晶体管时，功函数层可包含氮化钽层、在氮化钽层上的氮化钛层及在氮化钛层上的钛铝层。在功函数层的沉积后，形成阻障层，其可为另外的氮化钛层。
接着，沉积金属材料60，金属材料60可为由例如钨或钴所形成。金属材料60完全填充剩余的沟渠48(图8)。在图9所示的后续步骤中，进行如化学机械研磨或机械研磨的平坦化步骤，以移除在层间介电质46上的层56、层58及层60的部分。因此，形成金属栅极电极62，其是包含层58及层60的剩余部分。层52、层58及层60的剩余部分在之后是当作取代栅极堆叠64。如图9所示，金属栅极62、栅极间隙壁38、接触蚀刻中止层47及层间介电质46在此时为实质上共平面。
图10至图12A是绘示根据一些实施例的自对准硬遮罩的形成。层间介电质46的材料是与接触蚀刻中止层47、栅极间隙壁38及栅极电极62的材料不同。举例而言，层间介电质46可为含氧介电质，例如氧化物，而接触蚀刻中止层47、栅极间隙壁38及栅极电极62是不具有氧。因此，在图10至图12A中，对层间介电质46、接触蚀刻中止层47、栅极间隙壁38及栅极电极62的表面进行处理，以使后续硬遮罩的选择性沉积得以进行。
请参阅图10，进行前处理，例如使用酸，其可为稀释氢氟酸水溶液。相应的步骤是绘示于如图18所示的流程图200中的步骤212。前处理在图中是利用箭头65表示。前处理也可利用氨(NH3)及三氟化氮(NF3)的混合气体进行。
根据一些实施例，前处理会影响蚀刻，其是造成层间介电质46的凹陷。凹陷深度D1可为约10纳米至约50纳米。因此，暴露出接触蚀刻中止层47的侧壁(或栅极间隙壁38的侧壁，若没有形成接触蚀刻中止层47时)。
接着，如图11所示，进一步处理晶圆10，且在层间介电质46的表面上产生的键结(在前处理时)是被终止，以产生抑制层63。相应的步骤是绘示于如图18所示的流程图200中的步骤214。举例而言，可进行处理，以使在层间介电质46中与氧原子产生一些疏水性键结。根据一些实施例，连接至氧原子的键结可包含Si(CH3)3。连接键结的对应制程可包含硅烷化(silylation)制程，其中对应制程气体可包含双(三甲基硅基)胺[bis(trimethylsilyl)amine]、六甲基二硅氮烷(hexamethyldisilazane，HMDS)、四甲基二硅氮烷(tetramethyldisilazane，TMDS)、三甲基氯硅烷(trimethylchlorosilane，TMCS)、二甲基二氯硅烷(dimethyldichlorosilane，DMDCS)、甲基三氯硅烷(methyltrichlorosilane，MTCS)或类似物。根据其他实施例，因为层间介电质46的材料是与接触蚀刻中止层47、栅极间隙壁38及栅极电极62的材料不同，可选择性沉积有机薄膜(也可表示为薄膜63)在层间介电质46的表面上，但不在接触蚀刻中止层47、栅极间隙壁38及栅极电极62的暴露表面上。因此，无论是透过终止键结或透过选择性沉积，层间介电质46的表面的性质是转变成与接触蚀刻中止层47、栅极间隙壁38及栅极电极62的性质不同。
然后，如图12A所示，选择性沉积自对准硬遮罩66在取代栅极堆叠64上。相应的步骤是绘示于如图18所示的流程图200中的步骤216。硬遮罩66是当作自对准硬遮罩，由于其是自对准至接触蚀刻中止层47、栅极间隙壁38及栅极电极62的位置。硬遮罩66是由介电材料(例如氮化硅、碳氮化硅或类似物)所形成。在沉积中，由于层间介电质46的表面已被改变，难以在层间介电质46的表面上成核，因而硬遮罩66是不会从层间介电质46开始形成。另外，沉积硬遮罩66在接触蚀刻中止层47、栅极间隙壁38及栅极电极62的表面上。直接在栅极电极62上的硬遮罩66的部分主要是向上成长，且从接触蚀刻中止层47(或栅极间隙壁38，若接触蚀刻中止层47没有形成)的侧壁成长的硬遮罩66的部分主要是水平地成长。
在栅极介电质56含有氧的实施例中，根据栅极介电质56的组成，硬遮罩66可或可不从栅极介电质56的顶表面成长。然而，由于栅极介电质56是薄的，且栅极介电质56的暴露表面是窄的，即使硬遮罩66未从栅极介电质56成长地很好，从栅极电极62及栅极间隙壁38成长的硬遮罩66的部分会彼此结合，以形成主体硬遮罩66。根据一些实施例，孔隙(图未绘示)可(或可不)被形成在区域67A及/或区域67B，由于这些区域的成长不佳，且根据一些例示实施例，孔隙可造成硬遮罩66与层间介电质46及/或栅极介电质56些微地物理性分离。
图12B是绘示如图12A所示的晶圆10的透视视图。图12B是绘示硬遮罩66形成覆盖栅极电极62、栅极间隙壁38及接触蚀刻中止层47的长条。如图12A所示，硬遮罩66侧向扩散至超出接触蚀刻中止层47的外部边缘，借此硬遮罩66可具有宽度W2是大于距离W1，其中距离W1是在接触蚀刻中止层47的相邻的垂直部分的外部边缘之间。硬遮罩66还具有圆形的(弧状的)侧壁及顶表面。根据本揭露的一些实施例，硬遮罩66的厚度T1是大于约10纳米，且厚度T1的范围是介于为约10纳米至约100纳米。
在硬遮罩66的形成之后，进行后处理，以优化硬遮罩66的膜品质。根据一些例示实施例，透过温度介于约800℃及约1200℃之间的快速热退火(Rapid Thermal Anneal，RTA)进行后处理。根据另一些实施例，透过等离子处理进行后处理，其中等离子处理的制程气体是包含例如氮气、氢气、氩气、氦气及/或类似物。后处理是移除硬遮罩66的悬浮键(dangling bond)，使其成为较少孔洞且较能抵抗后续的清洗制程。
根据后处理的方法及抑制膜63的组成，后处理可或可不导致抑制膜63的移除。若抑制膜63未因为后处理而被移除，在硬遮罩66的形成之后，且在后处理之前或之后，进行额外的制程，以移除抑制膜63，使在层间介电质上方的沉积可进行。根据一些实施例，在蚀刻气体或蚀刻溶液中移除抑制膜63，取决于抑制膜的类型。根据另一些实施例，利用等离子移除抑制膜，其中等离子可具有轻微的碰撞效应。
接着，如图13所示，形成层间介电质68。相应的步骤是绘示于如图18所示的流程图200中的步骤218。形成层间介电质68的材料是选自于层间介电质46的候选材料的相同族群，且层间介电质68的材料可与层间介电质46的材料相同或不同。层间介电质68具有的顶表面是高于硬遮罩66的顶表面，以使硬遮罩66是埋入层间介电质68内。在层间介电质46及层间介电质68之间可具有或不具有可视的界面。
图14A及图14B是分别绘示晶圆10在平坦化步骤之后的剖面视图及透视视图，其中平坦化步骤可利用化学机械研磨或机械研磨来进行。图14B是绘示图14A所示的晶圆10的透视视图。相应的步骤是绘示于如图18所示的流程图200中的步骤220。因为平坦化步骤，硬遮罩66的顶表面是被平坦化的，且硬遮罩66的顶表面是与层间介电质68的顶表面共平面。剩下的硬遮罩66仍具有与层间介电质68接触的曲面侧壁。
在平坦化之后，可进行额外的后处理，以更优化硬遮罩66的膜品质。额外的后处理与在层间介电质68形成之前所进行的先前的后处理具有类似的功用，且可移除由于平坦化而暴露的硬遮罩66新暴露出的悬浮键，且更使硬遮罩66成为较少孔洞且较能抵抗后续的清洗制程。进行额外的后处理的方法是选自于与进行先前处理的候选材料及方法的相同族群。
图15至图17是绘示源极/漏极接触插塞及栅极接触插塞的形成。在绘示的例示实施例中，所示为三个源极/漏极区域42，且绘示的制程是显示一个源极/漏极接触插塞连接至最左边的源极/漏极区域42的形成。在现实制程中，也形成源极/漏极接触插塞，以连接至中心及最右边的源极/漏极区域42。然而，这些源极/漏极插塞是形成在绘示的不同平面上，且未于绘示的平面中显示。同样地，虽然一个栅极接触插塞是绘示为形成直接在附图右侧的取代栅极堆叠64上，也可形成栅极接触插塞直接在左边的栅极堆叠64上，其是与绘示的不同平面，且图未绘示。
图15绘示源极/漏极硅化物区域70、金属层72、导电阻障层74及金属区域76的形成。相应的步骤是绘示于如图18所示的流程图200中的步骤222。根据一些实施例，金属层72(例如钛金属层)是沉积为毯覆层，接着在金属层72的顶部部分上进行氮化制程，以形成金属氮化物层(例如74)。金属层72的底部部分是未被氮化。接着，进行退火(可为快速热退火)，以使金属层72与源极/漏极区域42的顶部部分反应，以形成硅化物区域70。在层间介电质46的侧壁上的金属层72的部分未发生反应。然后，可留下先前形成的金属氮化物层74，以做为绘示的导电阻障层74，或移除先前形成的金属氮化物层74，再接着沉积新的金属氮化物层(例如氮化钛，亦利用参考数值74表示)，且其是较被移除的金属氮化物层薄。然后，形成金属区域76，其是例如通过填充钨、钴或类似物，接着，进行平坦化，以移除多余的材料，以制成较低的源极/漏极接触插塞78。
请参阅图16，根据本揭露的一些实施例，形成蚀刻中止层80。根据一些实施例，蚀刻中止层是由氮化硅(SiN)、碳氮化硅(SiCN)、碳化硅(SiC)、氮碳氧化硅(SiOCN)或其他介电材料所形成。蚀刻中止层80的厚度的范围可为约2纳米至约4纳米。形成方法可包含等离子辅助化学气相沉积、原子层沉积、化学气相沉积或类似方法。接着，形成层间介电质82在蚀刻中止层80上。层间介电质82的材料是可选自于与形成层间介电质46及层间介电质68相同的候选材料(及方法)，且层间介电质46、层间介电质68及层间介电质82是由相同或不同的介电材料所形成。根据一些实施例，层间介电质82是使用等离子辅助化学气相沉积、流动式化学气相沉积、旋转涂布或类似方法所形成，且可包含氧化硅(SiO2)。层间介电质82的厚度的范围是介于约和约之间。
蚀刻层间介电质82及蚀刻中止层80，以形成开口83及开口84。可利用例如反应性离子蚀刻(Reactive Ion Etch，RIE)进行蚀刻。在后续步骤中，如图17所示，形成插塞/介层窗86及插塞/介层窗88。相应的步骤是绘示于如图18所示的流程图200中的步骤224。根据本揭露的一些实施例，插塞/介层窗86及插塞/介层窗88包含阻障层90及在阻障层90上的含金属材料92。根据本揭露的一些实施例，插塞/介层窗86及插塞/介层窗88的形成包含形成毯覆阻障层90及在毯覆阻障层90上的含金属材料92，并进行平坦化，以移除毯覆阻障层90及含金属材料92的多余部分。阻障层90可由金属氮化物(例如氮化钛或氮化钽)所形成。含金属材料92可由钨、钴、铜或类似物所形成。
在最终鳍式场效晶体管100中，栅极接触插塞88穿过对应的硬遮罩，剩下的硬遮罩66具有在栅极接触插塞88的相反侧上的部分。硬遮罩66侧向延伸至超过对应的取代栅极64及接触蚀刻中止层47，并具有与层间介电质68接触的曲面(或可为圆形的)侧壁。
本揭露的实施例具有一些优势的特征。通过利用选择性沉积在金属栅极上，而非以内缩金属栅极的方式形成硬遮罩，接着形成硬遮罩在凹陷内，金属栅极不须在内缩制程时考量高度损失，且可不用形成较高的高度。因此，孔隙填充在金属栅极的形成中变得较容易。也可减少金属栅极内缩的图案负载效应，其中图案负载效应是造成最终金属栅极具有不同高度。
根据本揭露的一些实施例，一种方法包含形成金属栅极在第一层间介电质内、在金属栅极及第一层间介电质上进行处理、选择性成长硬遮罩在金属栅极上，且不从第一层间介电质成长硬遮罩、沉积第二层间介电质在硬遮罩及第一层间介电质上、平坦化第二层间介电质及硬遮罩，以及形成栅极接触插塞穿过硬遮罩，以电性耦合金属栅极。
在一实施例中，栅极间隙壁是在金属栅极的侧壁上，接触蚀刻中止层的垂直部分是在栅极间隙壁的侧壁上，且自接触蚀刻中止层的垂直部分的侧壁中再成长硬遮罩。
在一实施例中，硬遮罩是成长为具有曲面侧壁及曲面顶表面。
在一实施例中，上述处理是包含以酸预处理金属栅极及第一层间介电质，以及形成抑制膜在第一层间介电质的暴露表面上，而不形成抑制膜在金属栅极上。
在一实施例中，上述方法还包含在选择性成长硬遮罩的操作后，对硬遮罩进行后处理。
在一实施例中，后处理包含热退火。
在一实施例中，在平坦化第二层间介电质及硬遮罩的操作后，对硬遮罩进行额外后处理。
根据本揭露的一些实施例，一种方法包含形成金属栅极在第一层间介电质内、内缩第一层间介电质，以使第一层间介电质的顶表面低于金属栅极的顶表面、选择性成长硬遮罩在金属栅极上。硬遮罩包含向上成长的顶部部分，及水平成长的侧壁部分。方法还包含沉积第二层间介电质在硬遮罩及第一层间介电质上、平坦化硬遮罩，使硬遮罩的底部部分维持在覆盖金属栅极。形成栅极接触插塞穿过第二层间介电质，以电性耦合金属栅极。
在一实施例中，栅极接触插塞还穿过硬遮罩，且硬遮罩包含仍在栅极接触插塞的一侧上的部分。
在一实施例中，栅极间隙壁是在金属栅极的侧壁上，且自栅极间隙壁的侧壁成长硬遮罩的侧壁部分。
在一实施例中，硬遮罩是成长为具有曲面侧壁及曲面顶表面。
在一实施例中，上述方法还包含以酸预处理金属栅极及第一层间介电质，以及形成抑制膜在第一层间介电质的顶表面上，而不形成抑制膜在金属栅极上。
在一实施例中，在选择性成长硬遮罩的操作后，对硬遮罩进行后处理。
在一实施例中，后处理包含热退火。
在一实施例中，后处理包含等离子处理。
根据本揭露的一些实施例，一种装置包含第一层间介电质、具有在第一层间介电质内的金属栅极的栅极堆叠、包含与栅极堆叠交叠的第一部分及与第一层间介电质的第一部分交叠的第二部分的硬遮罩。第二层间介电质具有与硬遮罩的侧壁接触的侧壁。第二层间介电质与第一层间介电质的第二部分交叠。栅极接触插塞是穿过硬遮罩，以与栅极堆叠接触。
在一实施例中，硬遮罩的侧壁为曲面。
在一实施例中，栅极堆叠包含栅极介电质，栅极介电质包含垂直部分，且装置还包含孔隙，孔隙在栅极介电质的垂直部分的顶部。
在一实施例中，第一层间介电质的顶表面是低于栅极堆叠的顶表面，且硬遮罩的第二部分是低于栅极堆叠的顶表面。
在一实施例中，上述装置还包含接触蚀刻中止层，接触蚀刻中止层包含与第一层间介电质交叠的底部部分以及具有侧壁且与第一层间介电质接触的垂直部分，其中硬遮罩的第二部分还与接触蚀刻中止层的垂直部分的侧壁接触。
上述摘要许多实施例的特征，因此本领域具有通常知识者可更了解本揭露的态样。本领域具有通常知识者应理解利用本揭露为基础可以设计或修饰其他制程和结构以实现和所述实施例相同的目的及/或达成相同优势。本领域具有通常知识者也应了解与此同等的架构并没有偏离本揭露的精神和范围，且可以在不偏离本揭露的精神和范围下做出各种变化、交换和取代。

Claims (10)

1.一种晶体管装置的制造方法，其特征在于，包含：
形成一金属栅极在一第一层间介电质内；
在该金属栅极及该第一层间介电质上进行一处理；
选择性成长一硬遮罩在该金属栅极上，且不从该第一层间介电质成长该硬遮罩；
沉积一第二层间介电质在该硬遮罩及该第一层间介电质上；
平坦化该第二层间介电质及该硬遮罩；以及
形成一栅极接触插塞，其中该栅极接触插塞穿过该硬遮罩，以电性耦合该金属栅极。
2.根据权利要求1所述的晶体管装置的制造方法，其特征在于，一栅极间隙壁是在该金属栅极的一侧壁上，一接触蚀刻中止层的一垂直部分是在该栅极间隙壁的一侧壁上，且自该接触蚀刻中止层的该垂直部分的一侧壁中再成长该硬遮罩，该硬遮罩是成长为具有一曲面侧壁及一曲面顶表面。
3.根据权利要求1所述的晶体管装置的制造方法，其特征在于，该处理包含：
以一酸预处理该金属栅极及该第一层间介电质；以及
形成一抑制膜在该第一层间介电质的一暴露表面上，而不形成该抑制膜在该金属栅极上。
4.根据权利要求1所述的晶体管装置的制造方法，其特征在于，还包含，
在该选择性成长该硬遮罩的操作后，对该硬遮罩进行一后处理；以及
在该平坦化该第二层间介电质及该硬遮罩的操作后，对该硬遮罩进行一额外后处理。
5.一种晶体管装置的制造方法，其特征在于，其特征在于，包含：
形成一金属栅极在一第一层间介电质内；
内缩该第一层间介电质，以使该第一层间介电质的一顶表面低于该金属栅极的一顶表面；
选择性成长一硬遮罩在该金属栅极上，其中该硬遮罩包含向上成长的一顶部部分，及水平成长的一侧壁部分；
沉积一第二层间介电质在该硬遮罩及该第一层间介电质上；
平坦化该硬遮罩，使该硬遮罩的一底部部分仍覆盖该金属栅极；以及
形成一栅极接触插塞穿过该第二层间介电质，以电性耦合该金属栅极。
6.根据权利要求5所述的晶体管装置的制造方法，其特征在于，该栅极接触插塞还穿过该硬遮罩，且该硬遮罩包含仍在该栅极接触插塞的一侧上的一部分。
7.根据权利要求5所述的晶体管装置的制造方法，其特征在于，还包含，在该选择性成长该硬遮罩的操作后，对该硬遮罩进行一后处理，且该后处理包含一热退火或一等离子处理。
8.一种晶体管装置，其特征在于，包含：
一第一层间介电质；
一栅极堆叠，包含在该第一层间介电质内的一金属栅极；
一硬遮罩，包含与该栅极堆叠交叠的一第一部分，及与该第一层间介电质的一第一部分交叠的一第二部分；
一第二层间介电质，具有一侧壁，该侧壁与该硬遮罩的一侧壁接触，且该第二层间介电质与该第一层间介电质的一第二部分交叠；以及
一栅极接触插塞，穿过该硬遮罩，以接触该栅极堆叠。
9.根据权利要求8所述的晶体管装置，其特征在于，该栅极堆叠包含一栅极介电质，该栅极介电质包含一垂直部分，该装置还包含一孔隙，该孔隙在该栅极介电质的该垂直部分的一顶部，该第一层间介电质的一顶表面是低于该栅极堆叠的一顶表面，该硬遮罩的该第二部分是低于该栅极堆叠的该顶表面，且该硬遮罩的该侧壁为曲面。
10.根据权利要求8所述的晶体管装置，其特征在于，还包含一接触蚀刻中止层，该接触蚀刻中止层包含与该第一层间介电质交叠的一底部部分以及具有一侧壁且与该第一层间介电质接触的一垂直部分，其中该硬遮罩的该第二部分还与该接触蚀刻中止层的该垂直部分的该侧壁接触。
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