CN108701691A - 用于微驱动器和微led的底板结构和方法 - Google Patents
用于微驱动器和微led的底板结构和方法 Download PDFInfo
- Publication number
- CN108701691A CN108701691A CN201780011825.5A CN201780011825A CN108701691A CN 108701691 A CN108701691 A CN 108701691A CN 201780011825 A CN201780011825 A CN 201780011825A CN 108701691 A CN108701691 A CN 108701691A
- Authority
- CN
- China
- Prior art keywords
- layer
- led
- chip
- passivation
- micro
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title description 15
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 238000002161 passivation Methods 0.000 claims description 79
- 239000000463 material Substances 0.000 claims description 46
- 229910000679 solder Inorganic materials 0.000 claims description 32
- 230000004888 barrier function Effects 0.000 claims description 27
- 239000010410 layer Substances 0.000 description 184
- 238000010586 diagram Methods 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 11
- 238000000151 deposition Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000008021 deposition Effects 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000010992 reflux Methods 0.000 description 5
- 229910004205 SiNX Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 238000009736 wetting Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- JEIPFZHSYJVQDO-UHFFFAOYSA-N ferric oxide Chemical compound O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 2
- 238000007306 functionalization reaction Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000005622 photoelectricity Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000001374 small-angle light scattering Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- -1 InGaN Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000011243 crosslinked material Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000004438 eyesight Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10145—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11464—Electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1601—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16112—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/384—Bump effects
- H01L2924/3841—Solder bridging
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Led Device Packages (AREA)
Abstract
描述了微LED和微驱动器芯片集成方案。在一个实施方案中,微驱动器芯片包括形成在所述微驱动器芯片的底表面中的多个沟槽,其中每个沟槽围绕在所述微驱动器芯片主体的底表面下方延伸的导电立柱。另外,描述了用于提供与导电端子触点和微LED的电连接的集成方案,所述导电端子触点和所述微LED键合到显示器衬底且与微驱动器芯片相邻。
Description
背景技术
技术领域
本文所述的实施方案涉及显示器底板。更具体地讲,实施方案涉及用于微LED显示器的微型器件集成技术。
背景技术
用于电话、平板电脑、计算机和电视的现有技术显示器利用具有薄膜晶体管(TFT)的玻璃衬底来控制基于液晶而穿过像素的背光传输。最近,已经引入了诸如基于有机发光二极管(OLED)的发射显示器作为更高功效的发射显示器,并且当显示黑色时允许每个像素完全关闭。更最近,已经提出将基于发射无机半导体的微LED结合到高分辨率显示器中。与OLED相比,基于无机半导体的微LED可能更节能,并且也可能不容易寿命降低且对湿气极度敏感。
发明内容
实施方案描述了微驱动器芯片和显示器底板集成方案。在实施方案中,微驱动器芯片包括器件层和在器件层下方的钝化层。钝化层包括底表面。在钝化层中形成多个沟槽,并且多个导电立柱位于多个沟槽内。每个导电立柱可从钝化层下方的着落垫延伸。每个导电立柱由对应沟槽的侧壁围绕,使得在导电立柱与对应沟槽的侧壁之间形成贮存器。根据实施方案,每个导电立柱包括在钝化层的底表面下方的底表面。
可在钝化层的底表面上以及在多个沟槽的侧壁上形成阻挡层。也可在多个着落垫上形成阻挡层。在实施方案中,阻挡层比钝化层薄。
在实施方案中,显示器衬底包括接触垫阵列。LED阵列键合到显示器衬底,并且芯片阵列键合到显示器衬底,并且每个芯片电连接到一个或多个LED以驱动一个或多个LED。在实施方案中,每个芯片包括钝化层,该钝化层包括多个沟槽和多个导电立柱,该多个导电立柱在多个沟槽内并且在钝化层的底表面下方延伸。每个导电立柱利用回流到对应沟槽中的焊料材料键合到接触垫。在实施方案中,导电端子线阵列在显示器衬底上,并且顶部接触层在LED阵列上且与其电连接,以及在导电端子线阵列上且与其电连接。在实施方案中,导电端子柱阵列在显示器衬底上,并且顶部接触层在LED阵列上且与其电连接,以及在导电端子柱阵列上且与其电连接。另外,图案化的绝缘层可覆盖接触垫阵列的边缘,其中每个芯片键合到在图案化的绝缘层的对应部分正上方的多个接触垫。
在实施方案中,显示器包括:显示器衬底;多个接触垫,该多个接触垫在显示器衬底上;芯片,该芯片键合到多个接触垫;库结构,该库结构与芯片相邻;迹线,该迹线将多个接触垫中的一个电连接到库结构顶部的LED接触垫;以及LED,该LED键合到LED接触垫。在实施方案中,迹线沿库结构的侧壁延展。钝化填充层可以围绕LED和芯片的侧壁,并且顶部接触层跨越钝化填充层、LED和芯片,其中顶部接触层在LED和导电端子触点上且与其电接触。
在实施方案中,库结构包括第一库级和在第一库级上的第二库级,其中导电端子触点在第二库级上。第二库级可与第一库级一体形成。
在实施方案中,在钝化填充层中,在导电端子触点上方形成开口。导电端子触点可在库结构上,并且顶部接触层沿钝化填充层中的开口的侧壁跨越。
在实施方案中,第二库结构横向地与库结构相邻。可在钝化填充层中,在导电端子触点上方形成开口。导电端子触点可在第二库结构上,并且顶部接触层沿钝化填充层中的开口的侧壁跨越。
根据实施方案,图案化的绝缘层可以任选地覆盖多个接触垫的边缘,并且芯片键合到在图案化的绝缘层的一部分正上方的多个接触垫。根据实施方案,钝化填充层可包括水平顶表面和共形底表面。例如,底表面可与库结构上的导电端子触点的形貌共形,并且迹线将多个接触垫中的一个电连接到LED接触垫。根据实施方案,芯片可包括器件层和在器件层下方的钝化层。多个沟槽在钝化层中并且多个导电立柱在多个沟槽内,使得多个导电立柱在钝化层的底表面下方延伸。每个导电立柱可利用回流到对应沟槽中的焊料材料键合到对应的接触垫。
附图说明
图1为根据实施方案的微驱动器芯片的透视图。
图2至图10为根据实施方案的制造微驱动器芯片阵列的方法的横截面侧视图图示。
图11为根据实施方案的显示器衬底上方的微驱动器芯片的示意性横截面侧视图图示。
图12为根据实施方案的键合到显示器衬底的微驱动器芯片的横截面侧视图图示。
图13至图14为根据实施方案的包括微驱动器芯片和微LED阵列的显示系统的示意性俯视图图示。
图15为示出根据实施方案的将微型器件集成在显示器衬底上的方法的流程图。
图16为根据实施方案的与图案化的钝化填充层集成的显示器衬底的一部分的示意性横截面侧视图图示。
图17至图20为根据实施方案的将微型器件集成在显示器衬底上的示意性横截面侧视图图示,其中图案化的绝缘层覆盖接触垫阵列的边缘。
图21为示出根据实施方案的将微型器件集成在显示器衬底上的方法的流程图。
图22为根据实施方案的与凸起的微LED集成的显示器衬底的一部分的示意性横截面侧视图图示。
图23为示出根据实施方案的将微型器件集成在显示器衬底上的方法的流程图。
图24为根据实施方案的与凸起的微LED和图案化的钝化填充层集成的显示器衬底的一部分的示意性横截面侧视图图示。
图25为根据实施方案的与凸起的微LED和图案化的钝化填充层集成的显示器衬底的一部分的示意性横截面侧视图图示。
图26为根据实施方案的与凸起的微LED和支柱结构集成的显示器衬底的一部分的示意性横截面侧视图图示。
图27A为根据实施方案的包括微驱动器芯片和凸起的微LED的显示器衬底的一部分的示意性俯视图图示。
图27B为根据实施方案的沿图27A的线X-X截取的示意性横截面侧视图图示。
具体实施方式
实施方案描述了用于将微LED和微芯片在显示器衬底上集成和功能化的方法和结构。具体地讲,实施方案涉及与微芯片(例如,微驱动器芯片)相邻的微LED的集成和功能化,微芯片包括用于驱动微LED的电路。根据实施方案,微LED可由基于无机半导体的材料形成,并且在侧壁之间的最大侧向尺寸为1μm至300μm、1μm至100μm、1μm至20μm,或更具体地,1μm至10μm,诸如5μm。根据实施方案,微LED可为垂直结构LED,包括:底部电极,该底部电极键合到显示器衬底上的接触垫(例如,驱动器垫);以及顶部电极,该顶部电极通过顶部接触层与导电端子结构电连接。例如,导电端子结构和对应的信号可为接地线或某个其他低电压(Vss)或反偏压、电源平面或某个其他高电压电平(Vdd)、电流源输出或电压源输出。根据实施方案,微芯片(例如,微驱动器芯片)可以具有1μm至300μm的最大侧向尺寸,并且可以装配在微LED的像素布局内。根据实施方案,微驱动器芯片可替代薄膜晶体管(TFT)衬底架构中常用的每个显示元件的驱动晶体管。微驱动器芯片可包括附加电路,诸如开关晶体管,发射控制晶体管,甚至用于每个显示元件的存储设备。微驱动器芯片可包括数字电路、模拟电路或混合电路。另外,与通常用于常规显示器底板衬底的非晶硅或低温多晶硅上的TFT处理技术相反,MOSFET处理技术可用于在单晶硅上制造微驱动器芯片。
在一个方面,实施方案描述了微芯片(例如,微驱动器芯片)集成方案,其中微芯片被设计用于与显示器衬底的超细间距键合。根据实施方案,从显示器底板衬底卸载到微驱动器芯片中的增加量的电路导致微驱动器芯片与显示器衬底的触点数量增加。此外,随着由单个微驱动器芯片驱动的微LED的数量的增加,触点数量增加。例如,单个微驱动器芯片可以驱动多个像素内的一个或多个LED。示例性触点包括但不限于微LED驱动器触点、Vdd、电源、Vss、接地、数据信号输入、扫描信号输入、发射控制信号输入、参考电压/电流等。
在一个示例性具体实施中,显示器包括红-绿-蓝(RGB)像素布局。以举例的方式,这可以与1920×1080或2560×1600分辨率兼容。在这个RGB布置中,每个像素都包括发红光的子像素、发绿光的子像素和发蓝光的子像素。然而,具体分辨率和RGB颜色方案仅用于说明目的,并且实施方案不限于此。其他示例性像素布置包括红-绿-蓝-黄-青(RBGYC)、红-绿-蓝-白(RGBW),或其中像素具有不同数量的子像素的其他子像素矩阵方案。
以举例的方式,每个子像素都可以通过水平尺寸(x)和垂直尺寸(y)来表征。表1中提供了用于RGB颜色方案的各种示例性尺寸,仅用于说明目的,以便提供根据实施方案的潜在对准公差的参考。
表1
像素间距(x,y) | 子像素间距(x,y) | 每英寸像素数(PPI) |
(634μm,634μm) | (211μm,634μm) | 40 |
(85μm,85μm) | (28μm,85μm) | 299 |
(78μm,78μm) | (26μm,78μm) | 326 |
(58μm,58μm) | (19μm,58μm) | 440 |
(39μm,39μm) | (13μm,39μm) | 652 |
因此,如表1所展示,随着像素密度(PPI)的增大,子像素间距,特别是每个子像素的示例性水平尺寸(x)减小。在结合有示例性最大侧向尺寸(x,y)为10μm或5μm的微LED的示例性显示器中,随着PPI的增大,子像素的水平尺寸(x)接近LED的水平尺寸。此外,微驱动器芯片的可用空间受到额外限制。在包括键合到高分辨率显示器的微驱动器芯片阵列的实施方案中,微驱动器芯片上的相邻触点(例如,导电立柱)之间的可用空间减小,特别是在微驱动器芯片内包含更复杂电路的情况下。根据实施方案,相邻触点之间的可用空间可小于几微米,例如,1μm至15μm,诸如1μm至6μm。
在实施方案中,每个微驱动器芯片利用焊料材料键合到显示器衬底上的多个接触垫。为了抑制焊料材料在相邻接触垫之间的侧向流动,每个微驱动器芯片包括在钝化层中形成的对应的多个沟槽内的多个导电立柱。当微驱动器芯片键合到显示器衬底上的接触垫时,焊料材料在沟槽内回流,沟槽用作收集回流焊料材料的贮存器。此外,与沿微驱动器芯片的底表面形成的阻挡材料(例如,Al2O3)不同,焊料材料可以优先润湿导电立柱。另外,这个优先润湿可用于将回流的焊料材料保持在微驱动器芯片沟槽内。根据一些实施方案,另选地或除此之外,图案化的绝缘层可设置在显示器衬底上,覆盖接触垫阵列的边缘,以便充当相邻接触垫上的焊料材料回流(和电短路)的屏障。
根据实施方案,在显示器衬底上的微LED和微驱动器芯片的侧壁周围施加钝化填充层。钝化填充层可用于将微LED和微驱动器芯片固定在显示器衬底上,钝化微LED的侧壁(例如,防止垂直结构微LED的顶部电极/底部电极之间发生短路),并且为顶部接触层的应用提供阶梯覆盖,该顶部接触层将微LED电连接到导电端子结构(例如,Vss、接地等)。
在一个方面,实施方案描述了显示器衬底上的各种库结构配置和支柱结构,用于升高导电端子接触顶表面和/或微LED顶表面,以补偿与微驱动器芯片的顶表面的高度差。
在一个方面,凸起的微LED可以潜在地减少从相邻微驱动器芯片发出的光的反射引起的低角度光散射。例如,由硅形成的微驱动器芯片可以充当反射从相邻微LED发出的光的镜子,可能在某些视角下降低显示器的光学性能。在实施方案中,将微LED键合在凸起的库结构上可以减少低角度光散射的量。
在一个方面,凸起的微LED可以减少与掩埋在显示器衬底中的信号线的耦接,以及可能导致的RC延迟。在实施方案中,将微LED键合在凸起的库结构上可以提供额外的绝缘,以减少耦接。
在一个方面,凸起的微LED和/或凸起的导电端子触点可以减小与顶部导电层形成电接触的对准公差。在一个方面,描述了各种库结构,其中微LED的顶表面在相邻微驱动器芯片的顶表面的至少2μm内,或更具体地在0.5μm内。在一些实施方案中,微LED的顶表面和微驱动器芯片的顶表面两者高于或与钝化填充层的顶表面齐平。在一些实施方案中,钝化填充层是通过在显示器衬底的整个显示区域上的缝涂形成的。钝化填充层的顶表面可凸起到最高部件(例如,微驱动器芯片)的顶表面,使得缝涂装置的刀片清除微驱动器芯片,而不损坏微驱动器芯片。
现在参考图1,提供了根据实施方案的微驱动器芯片的透视图。具体地讲,提供图1以示出根据实施方案的多个导电立柱134和围绕导电立柱134的多个沟槽114的关系。如图所示,微驱动器芯片120可包括器件层104和在器件层104下方的钝化层112。钝化层112包括底表面113。在钝化层中形成多个沟槽114,并且多个导电立柱134位于多个沟槽114内。每个导电立柱134可从钝化层112下方的着落垫延伸出。每个导电立柱134由对应沟槽114的侧壁115围绕,使得在导电立柱134与对应沟槽114的侧壁115之间形成贮存器。根据实施方案,每个导电立柱134包括在钝化层112的底表面113下方的底表面135。
虽然在图1中提供的图像中不是单独可见的,但可以在钝化层112的底表面113上以及在多个沟槽114的侧壁115上形成薄的共形阻挡层116。也可在多个着落垫上形成阻挡层。形成在钝化层112的底表面113上的阻挡层116可形成微驱动器芯片120的底表面121。另外,阻挡层116还可包括形成在钝化层112的侧壁115上且与其共形的侧壁117。在没有形成阻挡层116的实施方案中,钝化层112的底表面113可对应于微驱动器芯片120的底表面121。
图2至图10为根据实施方案的制造微驱动器芯片120阵列的方法的横截面侧视图图示。在实施方案中,微驱动器芯片120被制造在单晶硅晶片中。例如,制造衬底可包括硅晶片102和形成在硅晶片102上的器件层104。例如,器件层104可为在硅晶片102上生长的外延层。另外,衬底叠层可为绝缘体上硅(SOI)晶片,包括在器件层104下方的掩埋氧化物层。微驱动器芯片设备(例如,驱动器晶体管、发射控制晶体管、开关晶体管等)可以形成在器件层中并且在积聚层106中互连,该积聚层可以包括一个或多个互连层(例如,铜互连件)和绝缘层(例如,夹层电介质,ILD),最终形成在积聚层106顶部的多个着陆垫110中。例如,着落垫110可由铜形成。
在图2所示的实施方案中,在积聚层106上方形成钝化层112并图案化以形成穿过钝化层112的沟槽114,该沟槽暴露出对应的着落垫110的顶表面111。在实施方案中,沟槽的最大宽度为1μm至10μm,诸如1μm至5μm。在实施方案中,着落垫110比沟槽114宽,使得仅着落垫110的顶表面111暴露在沟槽114的底部。钝化层112可以由各种合适的材料形成,包括氧化物、氮化物(例如,SiNx)、聚合物(例如聚酰亚胺、环氧树脂等)。参考图3,然后可任选地在钝化层112上方、在沟槽114内以及在着落垫110的顶表面111上形成阻挡层116。根据实施方案,阻挡层116可以在微驱动器芯片120的蚀刻释放操作期间提供化学保护。另外,阻挡层116可以提供用于焊料回流的非润湿表面。阻挡层116可以使用诸如原子层沉积(ALD)的共形沉积技术来形成。在实施方案中,阻挡层116为成形的Al2O3。在实施方案中,阻挡层116的厚度小于2,000埃(0.2μm)。
现在参考图3,然后穿过钝化层112、积聚层106和器件层104形成小芯片沟槽122,以限定小芯片119阵列。在实施方案中,小芯片沟槽122停在硅晶片102(或掩埋氧化物层)上。示例性沟槽可为约1μm宽,且5μm至10μm深(例如,阻挡层116、钝化层112、积聚层106和器件层104的总厚度)。小芯片沟槽122可以使用诸如电感耦合等离子体反应离子蚀刻(ICP-RIE)的合适的干蚀刻技术来形成。
然后,可以在小芯片119阵列上方以及在小芯片沟槽122内形成牺牲释放层130,如图5所示。在实施方案中,牺牲释放层130由可以相对于形成小芯片119的其他材料而选择性地去除的材料形成。在实施方案中,牺牲释放层130由氧化物(例如,SiO2)形成,但也可以使用其他材料。牺牲释放层130可以使用能够填充小芯片沟槽122的合适的技术形成,诸如溅射、低温等离子体增强化学气相沉积(PECVD)或电子束蒸发。可任选地在沉积之后执行抛光操作以产生水平顶表面131。
在另选的实施方案中,可以在形成图4所示的小芯片沟槽122之后,以及在牺牲释放层130沉积之前形成阻挡层116。在这个实施方案中,阻挡层116也沿小芯片119的侧壁,以及在小芯片沟槽122内跨越。在这个实施方案中,阻挡层116可在蚀刻释放操作期间沿微驱动器芯片120的侧壁提供额外的化学保护。
现在参考图6,立柱-开口132穿过牺牲释放层130和可选的阻挡层116形成,以暴露着落垫110。如图所示,立柱-开口132可比在钝化层112中形成的沟槽114窄。这将允许沟槽在最终结构中用作贮存器。然后用导电材料填充立柱-开口132以形成导电立柱134。例如,导电立柱134可以由铜形成,并且可以使用牺牲释放层130作为电镀模具使用化学镀技术形成。
现在参考图8,然后将衬底叠层用稳定层140键合到承载衬底142。例如,稳定层140可由粘合剂键合材料诸如苯并环丁烯(BCB)或环氧树脂形成,并且可在粘合期间固化以形成交联的热固性材料。在实施方案中,承载衬底142为硅晶片,但也可以使用其他衬底。然后可以使用合适的工艺技术(诸如,研磨、蚀刻和研磨)去除硅晶片102,以使牺牲释放层130暴露在小芯片沟槽122内(如图9所示),之后去除牺牲释放层130(如图10所示),形成由稳定层140支撑在承载衬底142上的微驱动器芯片120阵列。在实施方案中,使用合适的蚀刻化学物质(诸如,HF蒸气)选择性地去除牺牲释放层130,但也可以使用其他化学物质,这取决于牺牲释放层130的组成。图10所示的微驱动器芯片120通过导电立柱134的底表面135与稳定层140接触的接触区域粘附到稳定层140。现在,微驱动器芯片120阵列准备用于拾取并转移到显示器衬底并与之键合。
现在参考图11,提供了根据实施方案的在显示器衬底202上方且在键合到显示器衬底202之前的微驱动器120的示意性横截面侧视图图示。如图所示,显示器衬底202的将接收微驱动器芯片120的部分包括多个接触垫204,该多个接触垫各自包括沉积在其上的焊料材料206。接触垫204可由各种导电材料诸如铜和铝形成,并且可以包括层叠堆。例如,接触垫204可包括粘合剂/阻挡层(例如,TaN),以防止扩散到下面的导电层(例如,铜、铝)中。
在实施方案中,沟槽114的最大宽度为1μm-10μm,诸如1μm-5μm,其中导电立柱134的最大宽度为0.5μm-5μm,例如1μm-3μm。在实施方案中,相邻沟槽114可以分开仅仅几微米的宽度,例如,1-15μm,诸如1μm-6μm。在实施方案中,焊料材料206的分开位置比对应的导电立柱134宽。如图所示,导电立柱134可比钝化层112和阻挡层116更厚(更高),使得导电立柱134的底表面135在微驱动器芯片120的底表面121下方,例如,在0.2μm-2μm的范围内。在实施方案中,微驱动器芯片120的主体(不包括导电立柱134)的总厚度为3μm-20μm,例如5μm-10μm,或8μm。
图12为根据实施方案的键合到显示器衬底202的微驱动器芯片120的横截面侧视图图示。在实施方案中,导电立柱134刺穿焊料材料206。根据实施方案,键合操作可在升高的温度下进行,以液化焊料材料206,该焊料材料回流并且由形成在微驱动器芯片120中的沟槽114容纳。这样,沟槽114可以抑制由于焊料材料206的过度回流而在相邻的接触垫204或导电立柱134上发生电短路的可能性。
根据实施方案,导电立柱134提供增加的表面积,用于与焊料材料206接触。与阻挡层116材料相比,增加的接触面积可另外提供增加的相对面积,用于优先润湿焊料材料206。这种优先润湿可以另外减轻回流的焊料材料206在相邻接触垫204之间的侧向扩展。
在另一方面,导电立柱134可以形成允许与接触垫204形成金属-金属接触的轮廓,该接触垫可以在转移和键合操作期间潜在地充当垫子,并且潜在地保持微驱动器芯片120的机械完整性。在这个配置中,形成导电立柱134和接触垫204的金属或金属合金材料可比微驱动器芯片120或显示器衬底202上的其他材料诸如Al2O3阻挡层116相对更软。这样,与软-硬或硬-硬接触相反,产生相对软-软的接触。
图13至图14为根据实施方案的包括微驱动器芯片120和微LED 220阵列的显示系统的示意性俯视图图示。发射控制器可以接收要在显示器底板上(例如,全部或一部分)显示的内容作为输入,例如,对应于图像信息的输入信号(例如,数据帧)。发射控制器可以包括电路(例如,逻辑)以选择性地使微LED 220发射(例如,对人眼可见)光。发射控制器可导致一个或多个存储设备(例如,电容器或数据寄存器)接收数据信号(例如,用于将微LED220关闭或打开的信号)。列驱动器和/或行驱动器可为发射控制器的部件。列驱动器可允许发射控制器与微驱动器芯片120列通信(例如,对其进行控制)。行驱动器可允许发射控制器与微驱动器芯片120行通信(例如,对其进行控制)。列驱动器和行驱动器可允许发射控制器与单独的微驱动器芯片120或一组微驱动器芯片120通信(例如,对其进行控制)。
在实施方案中,一个或多个微LED 220可连接到微驱动器芯片120,该微驱动器芯片(例如,根据发射控制器)驱动来自一个或多个微LED 220的光的发射。例如,微驱动器芯片120和微LED 220可以表面安装在显示器底板的显示器衬底上。尽管所描绘的微驱动器芯片120包括十个微LED 220,但本公开并不限于此,并且微驱动器芯片120可以驱动一个微LED 220或任意多个微LED 220和多个像素。
在一个实施方案中,显示器驱动器硬件电路(例如,硬件发射控制器)可以包括以下一个或多个:(例如,行选择)逻辑,用于选择显示器面板的发射组中的多个行,其中行数可从显示器面板的单个行调整到整个面板;(例如,列选择)逻辑,用于选择显示器面板的发射组中的多个列,其中列数可从显示器面板的单个列调整到整个面板;以及(例如,发射)逻辑,用于选择要显示的每个数据帧的脉冲数,其中每个数据帧的脉冲数可从一个调整到多个,脉冲长度可从连续工作循环调整到非连续工作循环。发射控制器可以包括硬件、软件、固件或它们的任何组合。
现在参考图13,在所示实施方案中,导电端子触点208的阵列示出为用于将微LED220电连接到导电端子结构的微LED 220和微驱动器芯片120的行和列之间的线的布置。在图14所示的实施方案中,导电端子触点208的阵列示出为用于将微LED 220电连接到导电端子结构的分开位置(例如,支柱或开口)的布置。
在以下描述和附图中,提供了用于将微LED 220和微驱动器芯片120集成在显示器衬底202上以及用于将微LED 220例如利用顶部接触层240电连接到导电端子结构的集成方案的各种横截面侧视图。根据实施方案,顶部接触层240可以以各种配置和区域与导电端子触点208电接触。例如,电触点可以沿钝化填充层230(例如,图13)中的暴露线或开口的线性长度形成,或者沿钝化填充层230(例如,图14)中的暴露柱或开口的离散位置形成。
现在参考图15,提供了示出根据实施方案的将微型器件集成在显示器衬底202上的方法的流程图。图16为根据实施方案的与图案化的钝化填充层230集成的显示器衬底202的一部分的示意性横截面侧视图图示。为了清楚起见,参考相同特征的相同附图标记同时描述图15至图16。
在操作1510中,将库结构212在显示器衬底202上图案化。库结构212可包括一个或多个层。例如,库结构212可包括SiO2、SiNx或SiNx在顶部的SiO2/SiNx叠堆。另选地,库结构212可由有机(例如,光致抗蚀剂)材料形成。库结构212可为线或离散的柱状突起的形式。
显示器衬底202可以是各种衬底。显示器衬底202可以是刚性的或柔性的。在实施方案中,显示器衬底为TFT衬底,其包括用于操作显示器的部分工作电路。例如,TFT衬底可包括没有被包括在微驱动器芯片120中的工作电路,以及用于将微驱动器芯片120与诸如行驱动器、列驱动器、发射控制器等系统部件电连接的路由线210(例如,信号线)。在实施方案中,显示器衬底202不包括工作电路的任何有源设备,但包括用于与系统部件电连接的路由线210。示例性路由线包括但不限于Vdd线、电源线、Vss线、接地线、数据信号输入线、扫描信号输入线、发射控制信号输入线、参考电压/电流线等。
在操作1520中,将接触层在显示器衬底202上图案化。在实施方案中,一个或多个金属层沉积并图案化以形成多个接触垫204、LED接触垫203、将接触垫204中的一个电连接到LED接触垫203的迹线205,以及导电端子触点208。在实施方案中,金属层的沉积和图案化包括剥离技术。另选地,可以使用沉积和蚀刻。在实施方案中,接触垫204、LED接触垫203、迹线205和导电端子触点208可由各种导电材料诸如铜和铝形成,并且可以包括层叠堆。例如,这些可包括粘合剂/阻挡层(例如,TaN),以防止扩散到下面的导电层(例如,铜、铝)中。
在操作1530中,将键合层(例如,焊料材料206)沉积在接触垫204和LED接触垫203上。例如,焊料材料206(例如,In、Sn等)可以使用蒸发技术来沉积。
在操作1540中,微型器件,其包括微驱动器芯片120和微LED 220,如先前相对于图12所述使用焊料材料206转移并键合到显示器衬底202。
图16中提供了微LED 220的近距离视图。如图所示,微LED 220可以包括微型p-n二极管222,其包括掺杂层225(例如,p掺杂)、掺杂层229(例如,n掺杂)以及在掺杂层225,229之间的有源层227(例如,包括一个或多个量子阱层)。在实施方案中,掺杂层225,229的掺杂是相反的。在顶部掺杂层229上形成顶部电极226,并且在底部掺杂层225上形成底部电极224。顶部电极和底部电极可以形成微LED 220的顶表面223和底表面221。如图所示,微LED220包括侧壁228,这些侧壁可以跨越微型p-n二极管222的层的侧向边缘。根据实施方案,可以使用基于不同的II-VI或III-V无机半导体的系统来制造微型p-n二极管222。例如,可以使用诸如但不限于GaN、AlGaN、InGaN、AlN、InAlN、AlInGaN、ZnSe的无机半导体材料来制造发蓝光的或发绿光的微型p-n二极管222。例如,可以使用诸如但不限于GaP、AlP、AlGaP、AlAs、AlGaAs、AlInGaP、AlGaAsP和任何As-P-Al-Ga-In的无机半导体材料来制造发红光的微型p-n二极管222。
在操作1550中,将钝化填充层230涂覆到显示器衬底202上。如图所示,钝化填充层230侧向地围绕微LED 220和微驱动器芯片120。钝化填充层230可以是在显示器衬底202的整个显示区域上方形成的单个层。钝化填充层230可以由介电材料形成。钝化填充层230可以由诸如丙烯酸或环氧树脂的交联材料形成。钝化填充层230可以是光电可成像的。可以使用各种施加方法来形成钝化填充层230,包括旋涂、喷墨和缝涂。在实施方案中,显示器衬底202是面板尺寸的。在这个实施方案中,可以使用缝涂。钝化填充层230的顶表面可凸起到或高于最高部件(例如,微驱动器芯片)的顶表面,使得缝涂装置的刀片清除微驱动器芯片120,而不损坏微驱动器芯片120。在形成钝化填充层230后,可任选地执行回蚀以减小钝化填充层230的厚度。
在实施方案中,钝化填充层230包括水平顶表面233和共形底表面。如图所示,共形底表面可以与其形成的形貌共形,包括库结构212上的导电端子触点208以及将LED接触垫203电连接到接触垫204的迹线205的形貌。
在操作1560中,钝化填充层230图案化以形成导电端子触点开口234来暴露出导电端子触点208,并且形成微LED开口232来暴露出微LED 220的顶表面223。在操作1570中,然后在钝化填充层230、微LED 220和导电端子触点208上形成顶部接触层240,使得顶部接触层与微LED 220和导电端子触点208电接触。
顶部接触层240可以由诸如透明导电氧化物(TCO)或透明导电聚合物等多种材料形成。在实施方案中,顶部接触层240由氧化铟锡(ITO)形成,并且可以使用合适的技术诸如溅射,并且任选地之后进行图案化来形成。在实施方案中,在微LED阵列中的每个微LED 220和导电端子触点阵列中的每个导电端子触点208的上方形成毯状顶部接触层240。在这个配置中,顶部接触层240提供导电端子结构和与底板上的像素区域内的所有微LED 220的信号连接。在实施方案中,形成多个顶部接触层240。
现在参考图17至图20,提供了根据实施方案的将微型器件集成在显示器衬底上的方法的示意性横截面侧视图图示,其中图案化的绝缘层211覆盖接触垫203,204阵列的边缘。具体地讲,可以利用灰度色调光掩模300来从与库结构212相同的层中形成图案化的绝缘层211。参考图17,在显示器衬底202上方形成绝缘层217,包括LED接触垫203、接触垫204和迹线205。绝缘层217可以由诸如光致抗蚀剂的光电可成像材料形成。参考图18,可以使用灰度色调掩模300来形成图案化的绝缘层211,该图案化的绝缘层覆盖接触垫204和任选地LED接触垫203以及图案化的库结构212的边缘。可以任选地在导电端子线201上形成图案化的库结构212。
参考图19,焊料材料206沉积在接触垫204和LED接触垫203上。焊料接触层207可以任选地沉积在库结构212上方,并与导电端子线201形成电接触。微驱动器芯片120和微LED220然后可以如先前相对于图12所述使用焊料材料206转移并键合到显示器衬底202。参考图20,钝化填充层230形成并图案化以形成开口234,232,并且顶部接触层240与相对于图16所述类似地沉积。
图案化的绝缘层211的集成并不限于图20所示的实施方案。例如,图案化的绝缘层211可以与图16、图22、图24、图25和图26中所示结构中的任一种组合。除此之外或另选地,焊料接触层207可以取代图16、图22、图24、图25和图26中的接触层208。
现在参考图21,提供了示出根据实施方案的将微型器件集成在显示器衬底上的方法的流程图。图22为根据实施方案的与凸起的微LED 220集成的显示器衬底202的一部分的示意性横截面侧视图图示。为了清楚起见,参考相同特征的相同附图标记同时描述图21至图22。此外,图21至图22与图15至图16共享多个相似性。为了不模糊本发明,将讨论具体的差异,并且可能不详细讨论类似的特征和操作。
参考图22,在所示实施方案中,库结构212包括多个库级。具体地,库结构212包括第一库级213和在第一库级213上的第二库级214。在操作2110中,将第一库级213图案化,之后在操作2120中将第二库级214图案化。在实施方案中,第一库级213和第二库级214由相同的材料层一体形成。第二库级214可为线或离散的柱状突起的形式。
在操作2130中,将接触层在显示器衬底202上图案化。在实施方案中,一个或多个金属层沉积并图案化以形成多个接触垫204、LED接触垫203、将接触垫204中的一个电连接到LED接触垫203的迹线205,以及导电端子触点208。在图22所示的实施方案中,LED接触垫203在第一库级213顶部,并且迹线205沿第一库级的侧壁215跨越到显示器衬底202上的(微驱动器芯片120)接触垫204。如图所示,在第二库级214上方形成导电端子触点208。在一个实施方案中,导电端子触点208的顶表面与微驱动器芯片120的顶表面123齐平或高于它(该微驱动器芯片在操作2130中尚未键合到显示器衬底)。
在操作2140中,键合层(焊料材料206)的分开位置沉积在接触垫204和微LED接触垫203上。在操作2150中,微驱动器芯片120和微LED 220如先前所述转移并键合到接触垫204,203,之后在操作2150中涂覆钝化层230,并且在操作2170中沉积顶部接触层240。
在图22所示的特定实施方案中,导电端子触点208的顶表面和微LED 220的顶表面223可以与微驱动器芯片120的顶表面123齐平。在实施方案中,导电端子触点208和微LED220的顶表面可以在微驱动器芯片120的顶表面123的2μm内,或0.5μm内。在实施方案中,钝化填充层230使用诸如缝涂的合适技术来形成,并且包括水平顶表面233,该水平顶表面可以任选地在涂覆之后回蚀以暴露出导电端子触点208的顶表面和微LED 220的顶表面223。
在图22所示的实施方案中,凸起的微LED 220可能导致低角度光散射的减少,并减少与掩埋在显示器衬底202中的路由线210的耦接。在将钝化填充层230中的开口图案化以形成电接触时,凸起的微LED 220以及凸起的导电端子触点208可以减轻对对准公差的要求。在其他实施方案中,图22的显示器结构可任选地包括微LED开口232和/或导电端子开口234。在这个配置中,库结构212可以部分地减轻由于微LED开口232和/或导电端子开口234的深度减小而引起的对准公差。
现在参考图23,提供了示出根据实施方案的将微型器件集成在显示器衬底上的方法的流程图。图24为根据实施方案的与凸起的微型LED 220和图案化的钝化填充层230集成的显示器衬底202的一部分的示意性横截面侧视图图示。为了清楚起见,参考相同特征的相同附图标记同时描述图23至图24。此外,图23至图24与图15至图16和图21至图22共享多个相似性。为了不模糊本发明,将讨论具体的差异,并且可能不详细讨论类似的特征和操作。
在操作2310中,将库结构212在显示器衬底202上图案化,之后在操作2320中将接触层图案化。参考图24,在所示实施方案中,导电端子触点208和LED接触垫203两者形成在库结构212的顶表面上,例如,库结构212的水平顶表面上。另外,迹线205沿库结构212的侧壁215跨越到显示器衬底202上的(微驱动器芯片120)接触垫204。然后可以与操作1530-1570类似地执行操作2330-2370,而不是形成微LED开口232。
图24所示的集成结构与相对于图22所示和所述的结构类似,不同之处是在钝化填充层230中形成导电端子触点开口234以及在库结构212顶部形成导电端子触点208,这与微LED接触垫203类似。在图24所示的实施方案中,凸起的微LED 220可能导致低角度光散射的减少,并减少与掩埋在显示器衬底202中的路由线210的耦接。在图案化钝化填充层230中的开口以形成电接触时,凸起的微LED 220可以减轻对对准公差的要求。在所示实施方案中,导电端子触点开口234仍然形成在钝化填充层230中以提供用于电连接到导电端子触点208的路径,然而,在一些实施方案中,对准公差可以比微LED 220的情况更大。例如,沿微LED220的侧壁228短路的风险对于与导电端子触点208接触来说不是问题。此外,根据一些实施方案,导电端子触点208和对应开口234的接触区域可以另外大于微LED 220的接触区域。在其他实施方案中,图24的显示器结构可任选地包括微LED开口232。在这个配置中,库结构212可以部分地减轻由于微LED开口232的深度减小而引起的对准公差。
现在参考图25,提供了根据实施方案的与凸起的微LED 220和图案化的钝化填充层230集成的显示器衬底202的一部分的示意性横截面侧视图图示。图25包括与图24所示实施方案的若干相似之处,一个区别在于针对导电端子触点208和微LED 220形成了单独的库结构212。在其他实施方案中,图25的显示器结构可任选地包括微LED开口232。在这个配置中,库结构212可以部分地减轻由于微LED开口232的深度减小而引起的对准公差。
图26为根据实施方案的与凸起的微LED 220和支柱结构集成的显示器衬底202的一部分的示意性横截面侧视图图示。图25包括与图22所示实施方案的若干相似之处,特别是在钝化填充层230中省略了图案化的开口,以便与导电端子触点和微LED 220电接触。在这个配置中,该处理可以类似于关于图16所描述的那样进行,其中形成了库结构212和导电端子触点208。然后可以在库结构212上的导电端子触点208的顶部和微LED接触垫203上形成支柱结构252,250(例如,通过无电沉积)。例如,支柱结构252,250可以是相同的高度。支柱结构可包括多种材料。例如,支柱结构可以包括铜、镍叠层,之后在支柱的顶部形成焊料材料206,并且在接触垫204上形成焊料材料206。在实施方案中,微驱动器芯片120和微LED220在焊料材料206沉积之后进行转移。在其他实施方案中,图26的显示器结构可任选地包括微LED开口232和/或导电端子开口234。在这个配置中,支柱结构252,250可以部分地减轻由于微LED开口232和/或导电端子开口234的深度减小而引起的对准公差。
现在参考图27A至图27B,提供了根据实施方案的包括微驱动器芯片和凸起的微LED的显示器衬底的一部分的示意性俯视图和横截面侧视图图示。如图所示,沿图27A的线X-X截取图27B的横截面侧视图图示。在图27A所示的特定实施方案中,每个微驱动器芯片120利用多个迹线205在每一侧连接到九个微LED 220,或者在示例性RGB像素布置中在每一侧连接到3个像素(P)。图27A所示的微LED 220和像素(P)的数量可以是说明性的,但实施方案并不限于此。在所示实施方案中,微驱动器芯片120任选地耦接到导电端子触点208。这可以是与顶部接触层240连接到的相同的导电端子触点208,或者另选地是为微驱动器芯片120保留的单独的导电端子触点208。虽然单独的导电端子触点208仍然可以接收与提供给微LED 220以及它们的对应导电端子触点208的信号相同的信号。
在实施方案中,一个或多个微驱动器芯片120安装在显示器衬底202上,在库结构212的开口内,或侧向地设置在库结构212之间。在图27A所示的特定实施方案中,库结构212为跨过显示器衬底延伸(例如,垂直地或水平地)的轨道的形状,其中微驱动器芯片120安装在相邻的库结构212之间。导电端子触点208可以任选地形成在库结构212上。例如,导电端子触点208可以形成在库结构212轨道的突起上。
在图27A至图27B所示的特定实施方案中,冗余微LED 220对安装到库结构212上。例如,每个微驱动器芯片120可连接到每个相邻库结构212上的微LED 220的行/列。可以使用各种操作配置来实现冗余。在示例性实施方案中,一个库结构212上的一组微LED 220(例如,左侧)可为主操作微LED 220,而另一个库结构212上的一组微LED 220(例如,右侧)可以是冗余的或者是次级微LED 220,除非满足一系列条件,否则不运行。但是,也可以操作所有微LED 220。
具体地讲,参考图27B,微LED开口232示出为在左侧的微LED 220对上方,而微LED开口232未示出为在右侧的微LED 220对上方。该异常可以通过具有不同厚度的微LED 220来解释,或者更具体地通过设计用于具有不同厚度的不同颜色发射(例如,红色,绿色和蓝色)的微LED 220来解释。因此,根据实施方案,设计用于不同颜色发射的微LED 220可具有对应的不同深度的微LED开口232。在实施方案中,微LED开口232形成在所有微LED 220上方。在实施方案中,微LED开口232形成在仅一些微LED 220上方。
根据实施方案,关于图27A至图27B所示的物理布局和配置没有特别限制,并且可以应用于本文描述的其他物理布局,包括但不限于图16、图20、图22、图24、图25和图26。
在利用实施方案的各个方面中,对本领域技术人员显而易见的是,对于将微LED和微驱动器芯片在显示器衬底上集成和电连接,以上实施方案的组合或变型是可能的。尽管以特定于结构特征和/或方法行为的语言对实施方案进行了描述,但应当理解,所附权利要求并不一定限于所描述的特定特征或行为。所公开的特定特征和行为相反应当被理解为用于进行例示的权利要求的实施方案。
Claims (20)
1.一种芯片,包括:
器件层;
钝化层,所述钝化层在所述器件层下方,所述钝化层包括底表面;
多个沟槽,所述多个沟槽在所述钝化层中;
多个导电立柱,所述多个导电立柱在所述多个沟槽内;
其中每个导电立柱由对应沟槽的侧壁围绕,使得在所述导电立柱与所述对应沟槽的所述侧壁之间形成贮存器;并且
每个导电立柱包括在所述钝化层的所述底表面下方的底表面。
2.根据权利要求1所述的芯片,还包括着落垫阵列,并且每个立柱从着落垫延伸出。
3.根据权利要求2所述的芯片,还包括阻挡层,所述阻挡层形成在所述钝化层的所述底表面上以及在所述多个沟槽的所述侧壁上。
4.根据权利要求3所述的芯片,其中所述阻挡层形成在所述多个着落垫上。
5.根据权利要求4所述的芯片,其中所述阻挡层比所述钝化层薄。
6.一种显示器,包括:
显示器衬底,所述显示器衬底包括接触垫阵列;
LED阵列,所述LED阵列键合到所述显示器衬底;
芯片阵列,所述芯片阵列键合到所述显示器衬底;
其中每个芯片电连接到一个或多个LED以驱动所述一个或多个LED;
其中每个芯片包括:
钝化层,所述钝化层包括多个沟槽;
多个导电立柱,所述多个导电立柱在所述多个沟槽内并且在所述钝化层的底表面下方延伸;
其中每个导电立柱利用回流到对应沟槽中的焊料材料键合到接触垫。
7.根据权利要求6所述的显示器,还包括:
导电端子线阵列,所述导电端子线阵列在所述显示器衬底上;
顶部接触层,所述顶部接触层在所述LED阵列上且与其电连接,以及在所述导电端子线阵列上且与其电连接。
8.根据权利要求6所述的显示器,还包括:
导电端子柱阵列,所述导电端子柱阵列在所述显示器衬底上;
顶部接触层,所述顶部接触层在所述LED阵列上且与其电连接,以及在所述导电端子柱阵列上且与其电连接。
9.根据权利要求6所述的显示器,还包括:
图案化的绝缘层,所述图案化的绝缘层覆盖所述接触垫阵列的边缘;
其中每个芯片键合到在所述图案化的绝缘层的对应部分正上方的多个接触垫。
10.一种显示器,包括:
显示器衬底;
多个接触垫,所述多个接触垫在所述显示器衬底上;
芯片,所述芯片键合到所述多个接触垫;
库结构,所述库结构与所述芯片相邻;
迹线,所述迹线将所述多个接触垫中的一个电连接到所述库结构顶部的LED接触垫;
LED,所述LED键合到所述LED接触垫。
11.根据权利要求10所述的显示器,其中所述迹线沿所述库结构的侧壁延展。
12.根据权利要求10所述的显示器,还包括:
钝化填充层,所述钝化填充层围绕所述LED和所述芯片的侧壁;以及
顶部接触层,所述顶部接触层跨越所述钝化填充层、所述LED和所述芯片,其中所述顶部接触层在所述LED和导电端子触点上且与其电接触。
13.根据权利要求12所述的显示器,其中所述库结构包括第一库级和在所述第一库级上的第二库级,并且所述导电端子触点在所述第二库级上。
14.根据权利要求13所述的显示器,其中所述第二库级与所述第一库级一体形成。
15.根据权利要求12所述的显示器,还包括:
开口,所述开口在所述钝化填充层中,在所述导电端子触点上方;
其中所述导电端子触点在所述库结构上,并且所述顶部接触层沿所述钝化填充层中的所述开口的侧壁跨越。
16.根据权利要求12所述的显示器,还包括:
第二库结构,所述第二库结构侧向地与所述库结构相邻;
开口,所述开口在所述钝化填充层中,在所述导电端子触点上方;
其中所述导电端子触点在所述第二库结构上,并且所述顶部接触层沿所述钝化填充层中的所述开口的侧壁跨越。
17.根据权利要求12所述的显示器,还包括:
图案化的绝缘层,所述图案化的绝缘层覆盖所述多个接触垫的边缘;
其中所述芯片键合到在所述图案化的绝缘层的一部分正上方的所述多个接触垫。
18.根据权利要求12所述的显示器,其中所述钝化填充层包括顶表面和共形底表面。
19.根据权利要求18所述的显示器,其中所述共形底表面与所述库结构上的导电端子触点的形貌共形,并且所述迹线将所述接触垫中的一个电连接到所述LED接触垫。
20.根据权利要求12所述的显示器,其中所述芯片包括:
器件层;
钝化层,所述钝化层在所述器件层下方,所述钝化层包括底表面;
多个沟槽,所述多个沟槽在所述钝化层中;
多个导电立柱,所述多个导电立柱在所述多个沟槽内;
多个导电立柱,所述多个导电立柱在所述多个沟槽内并且在所述钝化层的底表面下方延伸;
其中每个导电立柱利用回流到对应沟槽中的焊料材料键合到接触垫。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662297113P | 2016-02-18 | 2016-02-18 | |
US62/297,113 | 2016-02-18 | ||
PCT/US2017/017532 WO2017142817A1 (en) | 2016-02-18 | 2017-02-10 | Backplane structure and process for microdriver and micro led |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108701691A true CN108701691A (zh) | 2018-10-23 |
CN108701691B CN108701691B (zh) | 2022-05-27 |
Family
ID=58163208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201780011825.5A Active CN108701691B (zh) | 2016-02-18 | 2017-02-10 | 用于微驱动器和微led的底板结构和方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US10546796B2 (zh) |
EP (1) | EP3384530A1 (zh) |
JP (2) | JP6622923B2 (zh) |
KR (1) | KR102159873B1 (zh) |
CN (1) | CN108701691B (zh) |
WO (1) | WO2017142817A1 (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110164830A (zh) * | 2019-04-26 | 2019-08-23 | 厦门云天半导体科技有限公司 | 一种功率器件的三维互连结构及其制作方法 |
CN112599651A (zh) * | 2020-12-07 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板及转移方法 |
CN112786530A (zh) * | 2019-11-01 | 2021-05-11 | 美光科技公司 | 封装焊料tsv插入互连 |
WO2021219069A1 (zh) * | 2020-04-30 | 2021-11-04 | 华为技术有限公司 | 一种堆叠结构、显示屏及显示装置 |
US11587912B2 (en) | 2019-11-01 | 2023-02-21 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
US11631644B2 (en) | 2019-11-01 | 2023-04-18 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3041625B1 (fr) * | 2015-09-29 | 2021-07-30 | Tronics Microsystems | Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support |
US10115711B2 (en) | 2017-01-25 | 2018-10-30 | International Business Machines Corporation | Vertical light emitting diode with magnetic back contact |
DE102017125276A1 (de) * | 2017-10-27 | 2019-05-02 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung mehrere Halbleiterchips und Halbleiterchip |
KR102603411B1 (ko) | 2017-12-18 | 2023-11-16 | 엘지디스플레이 주식회사 | 마이크로led 표시장치 |
JP7054802B2 (ja) * | 2018-05-28 | 2022-04-15 | パナソニックIpマネジメント株式会社 | 表示基板およびled素子の実装方法 |
JP7132779B2 (ja) * | 2018-07-18 | 2022-09-07 | 株式会社ジャパンディスプレイ | 表示装置及びアレイ基板 |
KR102533666B1 (ko) | 2018-09-14 | 2023-05-17 | 삼성전자주식회사 | 디스플레이 패널 및 이를 포함하는 디스플레이 장치 |
CN110970456B (zh) * | 2018-09-27 | 2022-04-19 | 成都辰显光电有限公司 | 一种Micro-LED芯片及其制备方法、显示装置 |
JP7237536B2 (ja) * | 2018-11-12 | 2023-03-13 | 株式会社ジャパンディスプレイ | 表示装置 |
DE112020000921A5 (de) * | 2019-02-25 | 2021-11-04 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Kontrollierte benetzung bei der herstellung von elektronischen bauteilen |
US11637219B2 (en) | 2019-04-12 | 2023-04-25 | Google Llc | Monolithic integration of different light emitting structures on a same substrate |
US20220246594A1 (en) * | 2019-06-11 | 2022-08-04 | Kyocera Corporation | Light emitter board and display device |
KR20190092331A (ko) * | 2019-07-19 | 2019-08-07 | 엘지전자 주식회사 | 마이크로 led를 이용한 디스플레이 장치 및 이의 제조 방법 |
USD966207S1 (en) * | 2019-09-23 | 2022-10-11 | Star Co Scientific Technologies Advanced Research Co, Llc | Light-emitting diode array |
US11038088B2 (en) | 2019-10-14 | 2021-06-15 | Lextar Electronics Corporation | Light emitting diode package |
TWI779242B (zh) * | 2019-10-28 | 2022-10-01 | 錼創顯示科技股份有限公司 | 微型發光二極體裝置 |
FR3103057B1 (fr) * | 2019-11-08 | 2021-11-19 | Aledia | Procede de protection d'un dispositif optoelectronique contre les decharges electrostatiques |
US12051685B2 (en) * | 2020-02-06 | 2024-07-30 | Lumileds, LLC | Light-emitting device with metal inlay and bottom contacts |
US11621370B2 (en) * | 2020-06-19 | 2023-04-04 | Seoul Viosys Co., Ltd. | Single chip multi band led and application thereof |
US11575074B2 (en) | 2020-07-21 | 2023-02-07 | Lumileds Llc | Light-emitting device with metal inlay and top contacts |
US20230326929A1 (en) * | 2020-08-31 | 2023-10-12 | Lg Electronics Inc. | Display device using semiconductor light-emitting diodes |
KR20220038229A (ko) * | 2020-09-18 | 2022-03-28 | 삼성디스플레이 주식회사 | 표시 장치 및 그 제조 방법 |
KR20220041484A (ko) * | 2020-09-25 | 2022-04-01 | 삼성전자주식회사 | 마이크로 발광 소자, 이를 포함한 디스플레이 장치 및 그 제조 방법 |
KR20230093238A (ko) | 2020-10-23 | 2023-06-27 | 도레이 카부시키가이샤 | 표시 장치 및 표시 장치의 제조 방법 |
JPWO2022085431A1 (zh) | 2020-10-23 | 2022-04-28 | ||
US20230369271A1 (en) | 2020-10-23 | 2023-11-16 | Toray Industries, Inc. | Display device and method for manufacturing display device |
KR20220064004A (ko) * | 2020-11-11 | 2022-05-18 | 삼성전자주식회사 | 디스플레이 모듈 및 이를 포함하는 디스플레이 장치 |
CN113447716B (zh) * | 2020-12-09 | 2022-04-29 | 重庆康佳光电技术研究院有限公司 | 一种显示面板的检测方法及显示面板 |
TWI770813B (zh) * | 2021-02-08 | 2022-07-11 | 友達光電股份有限公司 | 顯示裝置及其製造方法 |
WO2022188859A1 (zh) * | 2021-03-12 | 2022-09-15 | 京东方科技集团股份有限公司 | 半导体装置及其制造方法 |
CN115084110B (zh) * | 2021-03-12 | 2024-09-10 | 京东方科技集团股份有限公司 | 半导体装置及其制造方法 |
CN115084069A (zh) * | 2021-03-12 | 2022-09-20 | 京东方科技集团股份有限公司 | 半导体装置及其制造方法 |
US20220328448A1 (en) * | 2021-04-09 | 2022-10-13 | Innolux Corporation | Manufacturing method of an electronic apparatus |
WO2022251006A1 (en) * | 2021-05-27 | 2022-12-01 | Apple Inc. | Single-pick-multiple-print micro led mass transfer with elastomer stamp |
WO2023002728A1 (ja) | 2021-07-21 | 2023-01-26 | 東レ株式会社 | 表示装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040219774A1 (en) * | 2003-05-02 | 2004-11-04 | Yu-Nung Shen | Method for forming conductive bump and device formed with such a conductive bump |
US20130256871A1 (en) * | 2012-03-29 | 2013-10-03 | Roden R. Topacio | Semiconductor chip device with fragmented solder structure pads |
CN103728747A (zh) * | 2014-01-08 | 2014-04-16 | 友达光电股份有限公司 | 一种覆晶薄膜结构及其液晶显示器 |
CN104392976A (zh) * | 2014-10-11 | 2015-03-04 | 合肥京东方光电科技有限公司 | 一种驱动芯片及显示装置 |
WO2015175131A1 (en) * | 2014-05-15 | 2015-11-19 | LuxVue Technology Corporation | Flexible display and method of formation with sacrificial release layer |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6528857B1 (en) * | 2000-11-13 | 2003-03-04 | Amkor Technology, Inc. | Chip size image sensor bumped package |
JP3690340B2 (ja) * | 2001-03-06 | 2005-08-31 | ソニー株式会社 | 半導体発光素子及びその製造方法 |
JP3836349B2 (ja) * | 2001-09-27 | 2006-10-25 | 株式会社東芝 | 半導体装置およびその製造方法 |
CN102290409B (zh) * | 2003-04-01 | 2014-01-15 | 夏普株式会社 | 发光装置 |
KR100683685B1 (ko) * | 2004-10-28 | 2007-02-15 | 삼성에스디아이 주식회사 | 유기박막 트랜지스터를 구비한 유기전계 발광표시장치 및그의 제조방법 |
US7952206B2 (en) | 2005-09-27 | 2011-05-31 | Agere Systems Inc. | Solder bump structure for flip chip semiconductor devices and method of manufacture therefore |
US20080251927A1 (en) | 2007-04-13 | 2008-10-16 | Texas Instruments Incorporated | Electromigration-Resistant Flip-Chip Solder Joints |
EP2351077B1 (en) | 2008-10-30 | 2017-03-01 | Tessera Advanced Technologies, Inc. | Through-substrate via and redistribution layer with metal paste |
US8440505B2 (en) | 2009-01-29 | 2013-05-14 | International Business Machines Corporation | Semiconductor chips including passivation layer trench structure |
US8164153B2 (en) | 2009-05-27 | 2012-04-24 | Continental Automotive Systems, Inc. | Thin semiconductor device having embedded die support and methods of making the same |
KR101058880B1 (ko) * | 2010-05-07 | 2011-08-25 | 서울대학교산학협력단 | 액티브 소자를 구비한 led 디스플레이 장치 및 그 제조방법 |
US8617926B2 (en) | 2010-09-09 | 2013-12-31 | Advanced Micro Devices, Inc. | Semiconductor chip device with polymeric filler trench |
WO2012102303A1 (ja) * | 2011-01-26 | 2012-08-02 | 株式会社村田製作所 | 電子部品モジュールおよび電子部品素子 |
FR2973573A1 (fr) | 2011-04-01 | 2012-10-05 | St Microelectronics Grenoble 2 | Boitier semi-conducteur comprenant un dispositif semi-conducteur optique |
CN103855142B (zh) * | 2012-12-04 | 2017-12-29 | 东芝照明技术株式会社 | 发光装置及照明装置 |
KR20140144963A (ko) * | 2013-06-12 | 2014-12-22 | 삼성전자주식회사 | 표시 장치 |
JP6152816B2 (ja) * | 2014-03-26 | 2017-06-28 | ソニー株式会社 | 半導体デバイス、表示パネル、表示装置、電子装置、および、半導体デバイスの製造方法 |
JP2015197544A (ja) * | 2014-03-31 | 2015-11-09 | ソニー株式会社 | 実装基板および電子機器 |
WO2015198837A1 (ja) * | 2014-06-27 | 2015-12-30 | ソニー株式会社 | 半導体装置およびその製造方法 |
CN105244347B (zh) * | 2014-07-07 | 2018-09-11 | 万国半导体股份有限公司 | 一种嵌入式封装及封装方法 |
US9799719B2 (en) * | 2014-09-25 | 2017-10-24 | X-Celeprint Limited | Active-matrix touchscreen |
US9698134B2 (en) * | 2014-11-27 | 2017-07-04 | Sct Technology, Ltd. | Method for manufacturing a light emitted diode display |
JP6823893B2 (ja) * | 2014-12-19 | 2021-02-03 | グロ アーベーGlo Ab | バックプレーン上に発光ダイオードアレイを生成する方法 |
US10529696B2 (en) * | 2016-04-12 | 2020-01-07 | Cree, Inc. | High density pixelated LED and devices and methods thereof |
CN107437551B (zh) * | 2016-05-25 | 2020-03-24 | 群创光电股份有限公司 | 显示装置及其制造方法 |
-
2017
- 2017-02-10 KR KR1020187022743A patent/KR102159873B1/ko active IP Right Grant
- 2017-02-10 EP EP17707450.7A patent/EP3384530A1/en not_active Withdrawn
- 2017-02-10 CN CN201780011825.5A patent/CN108701691B/zh active Active
- 2017-02-10 JP JP2018541279A patent/JP6622923B2/ja active Active
- 2017-02-10 WO PCT/US2017/017532 patent/WO2017142817A1/en active Application Filing
- 2017-02-10 US US16/077,185 patent/US10546796B2/en active Active
-
2019
- 2019-11-22 JP JP2019211597A patent/JP6898977B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040219774A1 (en) * | 2003-05-02 | 2004-11-04 | Yu-Nung Shen | Method for forming conductive bump and device formed with such a conductive bump |
US20130256871A1 (en) * | 2012-03-29 | 2013-10-03 | Roden R. Topacio | Semiconductor chip device with fragmented solder structure pads |
CN103728747A (zh) * | 2014-01-08 | 2014-04-16 | 友达光电股份有限公司 | 一种覆晶薄膜结构及其液晶显示器 |
WO2015175131A1 (en) * | 2014-05-15 | 2015-11-19 | LuxVue Technology Corporation | Flexible display and method of formation with sacrificial release layer |
CN104392976A (zh) * | 2014-10-11 | 2015-03-04 | 合肥京东方光电科技有限公司 | 一种驱动芯片及显示装置 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110164830A (zh) * | 2019-04-26 | 2019-08-23 | 厦门云天半导体科技有限公司 | 一种功率器件的三维互连结构及其制作方法 |
CN112786530A (zh) * | 2019-11-01 | 2021-05-11 | 美光科技公司 | 封装焊料tsv插入互连 |
US11587912B2 (en) | 2019-11-01 | 2023-02-21 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
US11631644B2 (en) | 2019-11-01 | 2023-04-18 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
US11973062B2 (en) | 2019-11-01 | 2024-04-30 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
WO2021219069A1 (zh) * | 2020-04-30 | 2021-11-04 | 华为技术有限公司 | 一种堆叠结构、显示屏及显示装置 |
CN112599651A (zh) * | 2020-12-07 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板及转移方法 |
CN112599651B (zh) * | 2020-12-07 | 2022-01-25 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板及转移方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2017142817A1 (en) | 2017-08-24 |
KR102159873B1 (ko) | 2020-10-15 |
KR20180103093A (ko) | 2018-09-18 |
EP3384530A1 (en) | 2018-10-10 |
CN108701691B (zh) | 2022-05-27 |
JP2020052404A (ja) | 2020-04-02 |
US10546796B2 (en) | 2020-01-28 |
JP6622923B2 (ja) | 2019-12-18 |
US20190115274A1 (en) | 2019-04-18 |
JP2019507905A (ja) | 2019-03-22 |
JP6898977B2 (ja) | 2021-07-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108701691A (zh) | 用于微驱动器和微led的底板结构和方法 | |
US20230143510A1 (en) | Led unit for display and display apparatus having the same | |
KR20200026845A (ko) | 반도체 발광소자를 이용한 디스플레이 장치 | |
US10497682B2 (en) | Backplane LED integration and functionalization structures | |
US10607515B2 (en) | Display device using semiconductor light emitting device and method for manufacturing the same | |
KR20200026775A (ko) | 반도체 발광소자를 이용한 디스플레이 장치 및 이의 제조방법 | |
US20230352643A1 (en) | Display apparatus using semiconductor light-emitting device | |
KR102200046B1 (ko) | 반도체 발광 소자를 이용한 디스플레이 장치 및 이의 제조방법 | |
US20210043678A1 (en) | Led display panel and led display apparatus having the same | |
US11908841B2 (en) | Back emission display | |
CN212517197U (zh) | 发光二极管显示面板以及具有其的显示装置 | |
US12080689B2 (en) | Display device using semiconductor light-emitting elements and manufacturing method therefor | |
US20220302351A1 (en) | Display device using semiconductor light emitting diode | |
US20220416126A1 (en) | Display device using semiconductor light emitting element, and method for manufacturing same | |
KR20200021485A (ko) | 반도체 발광소자를 이용한 디스플레이 장치 및 이의 제조방법 | |
KR20200023317A (ko) | 반도체 발광소자를 이용한 디스플레이 장치 | |
EP3993048A1 (en) | Substrate for manufacturing display device and method for manufacturing display device | |
KR20200026781A (ko) | 반도체 발광소자를 이용한 디스플레이 장치 | |
US20240021589A1 (en) | Led display apparatus | |
US20230066130A1 (en) | Display device and method of manufacturing display device | |
KR20200021484A (ko) | 디스플레이 장치 제조용 기판 및 이의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |