WO2022188859A1 - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
WO2022188859A1
WO2022188859A1 PCT/CN2022/080331 CN2022080331W WO2022188859A1 WO 2022188859 A1 WO2022188859 A1 WO 2022188859A1 CN 2022080331 W CN2022080331 W CN 2022080331W WO 2022188859 A1 WO2022188859 A1 WO 2022188859A1
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WIPO (PCT)
Prior art keywords
chip
substrate
layer
chips
terminal
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PCT/CN2022/080331
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English (en)
French (fr)
Inventor
王美丽
梁轩
王飞
王磊
杨亚锋
董学
曹占锋
王明星
李付强
张晨阳
赵欣欣
韩艳玲
王雷
冯煊
李亚鹏
Original Assignee
京东方科技集团股份有限公司
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Priority claimed from CN202110273788.3A external-priority patent/CN115084110B/zh
Priority claimed from CN202110273811.9A external-priority patent/CN115084068A/zh
Priority claimed from CN202110273812.3A external-priority patent/CN115084069A/zh
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP22766381.2A priority Critical patent/EP4131372A4/en
Publication of WO2022188859A1 publication Critical patent/WO2022188859A1/zh

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular, to a semiconductor device and a manufacturing method thereof.
  • embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.
  • a semiconductor device comprising: a substrate; a chip provided on the substrate, the chip comprising a chip body and a plurality of terminals provided on the chip body; a terminal expansion layer of the substrate, the terminal expansion layer comprising a conductive material, wherein the terminal expansion layer and at least one terminal are located on the same side of the chip body, and the semiconductor device further comprises a terminal expansion layer located in the terminal expansion layer a plurality of extension wires, the plurality of extension wires are respectively electrically connected to the plurality of terminals for drawing out the plurality of terminals; and the orthographic projection of at least one extension wire on the substrate is completely covered The orthographic projection on the substrate of the terminal electrically connected to the extension trace.
  • the semiconductor device further includes an adhesive layer disposed between the substrate and the chip body for securing the chip on the substrate; and
  • the chip body includes a first surface that faces or contacts the adhesive layer, and at least one terminal is disposed on a surface of the chip body other than the first surface.
  • the substrate includes a first substrate surface on which the chip is disposed, the first substrate surface including a first substrate edge; and at least one extension The orthographic projection of the trace on the substrate is inclined with respect to the edge of the first substrate.
  • the chip body has a second surface remote from the substrate, the orthographic projection of the second surface on the substrate has a regular shape, the second surface the substrate The orthographic projection on includes a first edge; and the first edge is inclined relative to the first substrate edge.
  • a first included angle is formed between an extension line of the orthographic projection of the at least one extended trace on the substrate and an extension line of the edge of the first substrate, and the first The included angle is greater than 0° and less than 90°; and/or, a second included angle is formed between the extension line of the first edge and the extension line of the edge of the first substrate, and the second included angle is greater than 0° and smaller than 90°.
  • the substrate includes a first substrate surface on which the chip is disposed;
  • the chip body of the chip includes a second surface, a first side surface, and a second surface side surfaces, the second surface and the first surface are respectively located on opposite sides of the chip body, the first side surface and the second side surface are respectively located on side surfaces of the chip body, the first side surface each of one side surface and the second side surface connects the first surface and the second surface; and at least one of the first side surface and the second side surface is relative to the The first substrate surface is inclined.
  • At least one extension trace is in direct contact with at least one terminal, and a portion of the at least one extension trace is in direct contact with one of the first side surface and the second side surface.
  • the semiconductor device further includes a first planarization layer disposed on one side of the chip and covering the terminals; and the terminal extension layer is located away from the first planarization layer.
  • the terminal extension layer is located away from the first planarization layer.
  • one end of the extended wiring is electrically connected to the terminal through a via hole or a groove penetrating the first planarization layer.
  • the semiconductor device further includes a pad, the pad is located on a side of the chip body close to the substrate, and an orthographic projection of the pad on the substrate is the same as that of the pad. Orthographic projections of the chip body on the substrate at least partially overlap.
  • the semiconductor device further includes a first planarization layer disposed on one side of the chip and covering the terminals, and a first planarization layer disposed on a side of the first planarization layer away from the substrate the second planarization layer; the semiconductor device further includes a first trace, the first trace is located in the redistribution layer; and the redistribution layer is located at a part of the second planarization layer away from the chip
  • one end of the first trace is electrically connected to the extended trace through a via hole or a groove penetrating both the first planarization layer and the second planarization layer.
  • the semiconductor device further includes a functional device electrically connected to at least one terminal of the chip; and the functional device is located on a different layer than the chip.
  • the semiconductor device includes a plurality of repeating units arranged on the substrate in an array along a first direction and a second direction; each repeating unit includes a plurality of the repeating units Chips, the plurality of chips in each repeating unit are arranged in an array along the first direction and the second direction on the substrate, or at least a portion of the plurality of chips in each repeating unit are arranged along the first direction the direction and the second direction are arranged in an array on the substrate; and in at least two of the plurality of repeating units, the relative position of at least one chip in one repeating unit in the repeating unit is the same as that of another repeating unit The relative positions of corresponding chips in the repeating unit are not the same in the other repeating unit; and/or, in at least two of the plurality of repeating units, at least one chip in one repeating unit is in the repeating unit is oriented differently from the orientation of the corresponding chip in another repeating unit in that other repeating unit.
  • the length of an extended trace used to lead out at least one terminal of at least one chip in one repeating unit is the same as that used to lead out another repeating unit.
  • the lengths of the extended traces of the corresponding terminals of the corresponding chips in the unit are not equal; and/or, in at least two of the plurality of repeating units, at least one terminal used to lead out at least one chip in one repeating unit
  • the extension direction of the extension trace is different from the extension direction of the extension trace used to lead out the corresponding terminal of the corresponding chip in another repeating unit.
  • the chip body of each chip has a second surface away from the substrate, the first The orthographic projection of the two surfaces on the substrate has a regular shape, and the connection line between the geometric centers of the orthographic projections of the second surfaces of the chip bodies of the two chips on the substrate and the first direction Or a third included angle is formed between the second directions, and the third included angle is greater than 0° and less than 90°.
  • the plurality of terminals included in the chip are all located on the second surface of the chip body of the chip; or, the plurality of terminals included in the chip are respectively located on the first side of the chip body of the chip surface and the second side surface; or, the plurality of terminals included in the chip are respectively located on the first surface and the second surface of the chip body of the chip.
  • the chip includes a first chip and a second chip, the first chip includes at least two first terminals, and the second chip includes at least two second terminals;
  • the first chip and the second chip are configured to implement different functions, the first chip includes at least one of a light-emitting chip and a sensor chip, and the second chip includes a sensor chip and a control chip at least one of chips; and one end of the at least one extension wire is electrically connected to the first chip, and the other end of the at least one extension wire is electrically connected to the second terminal.
  • the first chip includes a light-emitting chip, and the first chip and the second chip are arranged on the same layer.
  • the first chip includes a light-emitting chip, the first chip and the second chip are arranged in different layers; and the semiconductor device further includes a driving element, the driving element and the The first chip is electrically connected through at least one extension wire.
  • the driving element is a driving chip, and an orthographic projection of the driving chip on the substrate at least partially overlaps an orthographic projection of the first chip on the substrate; and
  • the first chip includes a main light-emitting surface, and the main light-emitting surface is located on a side of the first chip away from the driving chip.
  • the driving element is a driving chip, and the orthographic projection of the driving chip on the substrate does not overlap with the orthographic projection of the first chip on the substrate; and the The first chip includes a main light-emitting surface, and the main light-emitting surface is located on the side of the first chip close to the driving chip.
  • the semiconductor device further includes a protective layer, the protective layer is located on a side of the first chip away from the second chip, the protective layer covers the at least one terminal extension layer, and exposing the light emitting surface of the first chip.
  • the driving element includes a driving circuit for driving the first chip, the driving circuit includes at least a thin film transistor, and the thin film transistor is located at the same distance as the first chip and the second chip. different layers of the chip; and the thin film transistor at least includes a source electrode and a drain electrode, and the source electrode or the drain electrode is electrically connected to at least one extended trace through a via hole or a groove.
  • the first chip and the second chip are arranged in different layers; and the thin film transistor is located on a side of the first chip away from the substrate, the second chip on the side of the thin film transistor away from the substrate.
  • the chip further includes a third chip, the first chip, the second chip and the third chip are configured to implement different functions from each other;
  • the semiconductor device includes at least one Chip sets, each chip set includes at least one second chip and at least one third chip; and a plurality of chip sets are electrically connected with a plurality of first chips in a one-to-one correspondence; or, one chip set is connected with a plurality of first chips Chips are electrically connected.
  • the first chip includes a sensor chip, and the plurality of sensor chips are connected in series; and the second chip includes a control chip.
  • the sensor chip includes at least one of a transducer chip and a piezoelectric sensor chip.
  • each of the sensor chips includes a first electrode, a second electrode, and a functional thin film sandwiched between the first electrode and the second electrode;
  • the first electrodes are located on the same layer, and the second electrodes of a plurality of sensor chips are located on the same layer; and in two adjacent sensor chips, the first electrodes of one sensor chip communicate with the other through vias or grooves.
  • the second electrode of the sensor chip is electrically connected.
  • each of the sensing chips includes a first electrode, a second electrode, and a functional thin film sandwiched between the first electrode and the second electrode;
  • the semiconductor device includes multiple a plurality of sensor chip groups and a plurality of conductive parts, each sensor chip group includes at least two sensor chips; the plurality of sensor chip groups are respectively arranged on the plurality of conductive parts, and the plurality of conductive parts are arranged at intervals; In the sensor chip set, the first electrode of one sensor chip and the second electrode of the other sensor chip in any two adjacent sensor chips are in contact with the same conductive part.
  • the semiconductor device further includes a second planarization layer covering the plurality of sensor chips and a second terminal extension disposed on a side of the second planarization layer away from the substrate layer, the second terminal extension layer includes a plurality of second extension traces; and in two adjacent sensor chip groups, the first electrode of the sensor chip of one sensor chip group and the other sensor chip The second electrodes of the sensor chips of the group are electrically connected through at least one second extended trace and via holes or grooves penetrating the second planarization layer.
  • each of the sensing chips includes a first electrode, a second electrode, and a functional thin film sandwiched between the first electrode and the second electrode;
  • the semiconductor device includes multiple sensor chip groups and at least one conductive part, each sensor chip group includes at least two sensor chips; at least two sensor chip groups are arranged on the same conductive part; and in one sensor chip group, at least Two sensor chips are stacked on the conductive part, the first electrode or the second electrode of one sensor chip closest to the conductive part is in contact with the conductive part, and one of any two adjacent sensor chips The first electrode of the sensor chip is in contact with the second electrode of the other sensor chip.
  • the at least one chip further includes a control chip; the control chip is located on the same layer as the plurality of sensor chips; the semiconductor device further includes a cover covering the plurality of sensor chips and all the sensor chips.
  • a second planarization layer of the control chip and a second terminal expansion layer disposed on the side of the second planarization layer away from the substrate, the second terminal expansion layer including a plurality of second expansion traces; and
  • a first electrode or a second electrode of a sensor chip closest to the control chip and a terminal of the control chip pass through at least one second extended trace and a via hole or groove penetrating the second planarization layer electrical connection.
  • the semiconductor device further includes: a plurality of pixels disposed on the substrate, the plurality of pixels being arranged in an array along a row direction and a column direction; a gate chip, the gate The chip includes at least two ports; a plurality of row signal connection lines, one row signal connection line is electrically connected to a plurality of pixels located in the same row; a plurality of column signal connection lines, one column signal connection line and a plurality of pixels located in the same column and a gate transistor, the first chip is electrically connected to a column signal connection line through the gate transistor, wherein the plurality of row signal connection lines are respectively connected to the gate chip through a first extension wire
  • the plurality of ports are electrically connected to the plurality of first chips, and the plurality of first chips are electrically connected to the second chip through second extension wires, and the first extension wires and the second extension wires are located in the at least one terminal extension layer.
  • a display device comprising: a substrate; a plurality of chips disposed on the substrate, wherein each first chip includes at least two terminals, the chips including at least one selected from light-emitting diode chips, sub-millimeter light-emitting diode chips, and miniature light-emitting diode chips; a drive circuit for driving the chip, the drive circuit including at least one thin film transistor; and disposed on the substrate at least one terminal expansion layer of the semiconductor device, the terminal expansion layer comprising a conductive material, wherein the terminal expansion layer and at least one terminal are located on the same side of the chip body, and the semiconductor device further comprises a terminal expansion layer located on the at least one terminal expansion layer A plurality of extension traces in the circuit, the plurality of extension traces are respectively electrically connected to the plurality of terminals, and are used to lead out the plurality of terminals; the orthographic projection of at least one extension trace on the substrate covers the The orthographic projection of the terminal electrically connected to the extension trace
  • a method for manufacturing a semiconductor device comprising:
  • the chip includes a chip body and a plurality of terminals disposed on the chip body;
  • a terminal expansion layer is formed on the side of the chip away from the substrate through a post-alignment process, wherein the terminal expansion layer includes a conductive material,
  • forming the terminal expansion layer on the side of the chip away from the substrate by the post-alignment process includes:
  • the conductive material layer is etched through a photolithography process to form a plurality of extension traces in the terminal extension layer
  • the plurality of extension wires are respectively electrically connected to the plurality of terminals for drawing out the plurality of terminals;
  • the orthographic projection of the at least one extension trace on the substrate completely covers the orthographic projection of the terminal electrically connected to the extension trace on the substrate.
  • the photographing the substrate provided with the chip includes:
  • the photographing device is translated by a fixed stepping distance to photograph the second photographing area of the substrate provided with the chip,
  • the number of photographing times is related to the distribution density of the chips, and each photographing area is provided with at least one of the chips.
  • the placing the chip on the substrate includes:
  • the chip is transferred onto the adhesive layer through a transfer process, so that the chip is fixed on the substrate through the adhesive layer.
  • the manufacturing method further includes:
  • a driving element is formed on the side of the terminal expansion layer away from the substrate
  • the driving element includes a driving chip or a driving circuit with thin film transistors.
  • the manufacturing method further includes:
  • the driving element includes a driving chip or a driving circuit with thin film transistors.
  • the forming at least one terminal extension layer on a side of the plurality of chips away from the substrate by a post-alignment process includes:
  • a first terminal extension layer is directly formed on the chip, and a first extension trace located in the first terminal extension layer is formed by a photolithography process, so that one end of the first extension trace is connected to the first terminal contact, and a part of the first extended wiring is in contact with the sidewall of the chip.
  • the manufacturing method further includes: forming a first planarization layer on a side of the chip away from the substrate, the first planarization layer covering the terminals of the chip; and
  • a plurality of via holes or grooves are formed in the first planarization layer by a photolithography process, and the plurality of via holes or grooves respectively expose at least a part of the terminals of the chip,
  • the forming a terminal extension layer on the side of the chip away from the substrate through a post-alignment process includes:
  • a terminal extension layer is formed on the side of the first planarization layer away from the substrate, and an extension trace in the terminal extension layer is formed through a post-alignment process, so that one end of the extension trace passes through the Vias or grooves are in contact with the terminals.
  • the forming a terminal extension layer on a side of the chip away from the substrate through a post-alignment process includes:
  • a redistribution layer is formed on the side of the first planarization layer away from the substrate,
  • the manufacturing method also includes:
  • a metal layer is electrochemically plated to grow a conductive connection portion equal to the thickness of the first planarization layer in the plurality of via holes or grooves, wherein the The conductive connection portion is used to electrically connect the terminal extension layer and the redistribution layer.
  • the manufacturing method further includes:
  • image recognition technology is used to determine the coordinate information of the defective points.
  • the conductive material layer is etched through the photolithography process based on the coordinate information, so as to form at least one extended trace in the terminal extension layer for repairing the defective point.
  • a semiconductor device comprising: a substrate; a plurality of chips disposed on the substrate, each chip including a chip body and a plurality of terminals disposed on the chip body; a plurality of fixed connection parts disposed on the substrate; a terminal expansion layer disposed on the substrate, the terminal expansion layer comprising a conductive material, wherein the plurality of fixed connection parts are respectively disposed adjacent to the plurality of chips ;
  • the semiconductor device further includes a plurality of extension wires located in the terminal extension layer, the extension wires are used to electrically connect the plurality of chips; and the extension wires used to electrically connect the two chips at least include A first wiring segment and a second wiring segment, the first wiring segment is used to electrically connect a terminal of one chip and a fixed connection portion adjacent to the chip, and the second wiring segment is used to connect two wires between the two chips. a fixed connection.
  • At least one second trace segment extends in a first direction; and of the two chips electrically connected by an extension trace including the second trace segment extending in the first direction, one chip is in the first direction.
  • the relative position in the first direction is different from the relative position of the other chip in the first direction.
  • At least one chip is inclined with respect to an extension line of the second trace segment.
  • one chip is oriented relative to the extension of the second trace segment relative to the other chip.
  • the orientations of the extension lines of the second line segments are different.
  • each chip in two chips that are electrically connected by an extended trace including at least one second trace segment, each chip includes a plurality of terminals including at least a first terminal and a second terminal;
  • the second trace segment included in the extended trace connecting the first terminals of the two chips and the second trace segment included in the extended trace for electrically connecting the second terminals of the two chips are parallel to each other, and/or used for electrical connection.
  • the lengths of the second wire segment included in the extension wire connecting the first terminals of the two chips and the second wire segment included in the extension wire for electrically connecting the second terminals of the two chips are substantially equal.
  • the included angle of is different from the included angle between another first wiring segment and the second wiring segment adjacent and electrically connected to it.
  • a first trace segment and a second trace segment adjacent to and electrically connected to it The included angle therebetween is different from the included angle between another first wiring segment and the second wiring segment adjacent to and electrically connected to it.
  • a plurality of the first trace segments are located in the same layer; and the second trace segments and the first trace segments are located in the same or different layers.
  • a display device comprising: a substrate; a plurality of pixels disposed on the substrate, the plurality of pixels being arranged in an array along a first direction and a second direction Arrangement; a plurality of chips arranged on the substrate, each chip comprising a chip body and a plurality of terminals arranged on the chip body; a plurality of fixed connection parts arranged on the substrate; arranged on the substrate at least one terminal expansion layer at the bottom, the terminal expansion layer includes a conductive material, wherein the plurality of fixed connection parts are respectively disposed adjacent to the plurality of chips; the semiconductor device further comprises a terminal expansion layer located in the at least one terminal expansion layer A plurality of extension lines of the 10000000000000, the extension lines are used to electrically connect the plurality of chips; the extension lines used to electrically connect the two chips include at least a first line segment and a second line segment, the first line The wire segment is used to electrically connect a terminal of one chip and a fixed connection part adjacent to the chip
  • the plurality of chips are arranged in an array along a first direction and a second direction; and at least one first trace segment is inclined with respect to the first direction and the second direction.
  • the second routing segment extends along the first direction or the second direction.
  • a method for manufacturing a semiconductor device comprising:
  • each chip includes a chip body and a plurality of terminals disposed on the chip body;
  • a terminal expansion layer is formed on a side of the plurality of chips away from the substrate through a post-alignment process, wherein the terminal expansion layer includes a conductive material,
  • the forming a terminal extension layer on the side of the plurality of chips away from the substrate through a post-alignment process includes:
  • the conductive material layer is etched through a photolithography process to form a plurality of extension traces in the terminal extension layer
  • the extended wiring is used for electrically connecting the plurality of chips
  • the extended wiring for electrically connecting two chips includes at least a first wiring segment and a second wiring segment
  • the first wiring segment is used for electrical connection
  • a terminal of a chip is connected to a fixed connection portion adjacent to the chip
  • the second wire segment is used to connect the two fixed connection portions between the two chips.
  • the step of generating a graphic file of the terminal includes:
  • a graphic file of the terminals is generated.
  • the photographing the substrate provided with the plurality of chips and the plurality of fixed connection parts includes:
  • the photographing device is translated by a fixed stepping distance to take a second photograph of the substrate provided with the plurality of chips and the plurality of fixed connection parts area to take pictures,
  • the number of photographing times is related to the distribution density of the chips, and each photographing area is provided with at least one of the chips.
  • the manufacturing method further includes:
  • the plurality of position calibration marks are in one-to-one correspondence with the plurality of photographing areas, respectively.
  • a semiconductor device comprising: a first substrate and a second substrate disposed oppositely; a chip disposed on the first substrate, the chip including a chip body and a chip disposed on the first substrate a plurality of first terminals on the chip body; a terminal expansion layer disposed on the first substrate, the terminal expansion layer comprising a conductive material; and a plurality of second terminals disposed on the second substrate , wherein the terminal expansion layer and at least one first terminal are located on the same side of the chip body, and the semiconductor device further includes a plurality of expansion traces located in the terminal expansion layer, the multiple expansion traces They are respectively electrically connected to the plurality of first terminals for drawing out the plurality of first terminals; the orthographic projection of the plurality of extension wires on the first substrate completely covers the first terminals electrically connected to the extension wires.
  • the semiconductor device further includes a plurality of driving elements disposed on the second substrate, and the plurality of second terminals are located away from the plurality of driving elements On one side of the second substrate, the plurality of second terminals are respectively electrically connected to the plurality of driving elements.
  • the plurality of first terminals included in the chip are all located on a side of the chip body of the chip away from the first substrate; and the semiconductor device further includes an adhesive layer, the adhesive layer It is disposed between the first substrate and the chip body, and is used for fixing the at least one chip on the first substrate.
  • the plurality of first terminals included in the chip are respectively located on both sides of the chip body of the chip along a direction parallel to the first substrate surface of the first substrate, wherein the a first substrate surface of the first substrate is a surface on which the first substrate is provided with the chip; and the semiconductor device further includes an adhesive layer provided between the first substrate and the chip between the main bodies, for fixing the chip on the first substrate.
  • the plurality of first terminals included in the chip are respectively located on both sides of the chip body of the chip along a direction perpendicular to the first substrate surface of the first substrate, wherein the The first substrate surface of the first substrate is the surface on which the first substrate is provided with the chip; and the semiconductor device further includes an adhesive layer and a first conductive layer, the adhesive layer being provided on the first substrate between the bottom and the chip body, the first conductive layer is disposed between the adhesive layer and the chip, the first conductive layer and at least a part of the chip close to the first substrate A first terminal is electrically connected.
  • the first substrate includes a first substrate surface on which the chip is disposed, the first substrate surface including a first substrate edge; and at least The orthographic projection of an extended trace on the first substrate is inclined with respect to the edge of the first substrate.
  • the chip body has a second surface remote from the first substrate, the orthographic projection of the second surface on the first substrate has a regular shape, the second surface
  • the orthographic projection on the first substrate includes a first edge; and the first edge is inclined relative to the first substrate edge.
  • a method for manufacturing a semiconductor device comprising:
  • the chip includes a chip body and a plurality of first terminals disposed on the chip body;
  • a terminal expansion layer is formed on a side of the chip away from the first substrate by a post-alignment process, wherein the terminal expansion layer includes a conductive material;
  • forming a terminal extension layer on the side of the chip away from the first substrate through a post-alignment process includes:
  • the conductive material layer is etched through a photolithography process to form a plurality of extension traces in the terminal extension layer
  • the orthographic projection of the plurality of extension wires on the first substrate completely covers the orthographic projection of the first terminal electrically connected with the extension wires on the first substrate;
  • the plurality of first terminals are respectively electrically connected to the plurality of second terminals through the plurality of extension traces, and the orthographic projections of the plurality of second terminals on the first substrate are connected to the plurality of second terminals.
  • the orthographic projections of the extended traces on the first substrate at least partially overlap.
  • the placing the chip on the first substrate includes:
  • the chip is transferred onto the adhesive layer through a transfer process, so that the chip is fixed on the first substrate through the adhesive layer.
  • FIG. 1 schematically shows a block diagram of a display device according to some exemplary embodiments of the present disclosure.
  • FIG. 2 is a schematic diagram schematically illustrating an arrangement of a plurality of chips in a display substrate according to an embodiment of the present disclosure.
  • FIGS. 3A to 3C are schematic diagrams respectively illustrating the relative positional relationship between functional unit groups and display regions in a display substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram schematically illustrating an alignment relationship between a terminal (pad) on a substrate and a terminal (pad) on a chip in a semiconductor device (eg, a display substrate) according to an embodiment of the present disclosure.
  • 5A-5D are schematic diagrams schematically illustrating some steps of a post-alignment process according to an embodiment of the present disclosure.
  • 6A and 6B are a schematic cross-sectional view and a schematic top view, respectively, of a microchip according to an embodiment of the present disclosure.
  • 7A , 7B and 7C are respectively a perspective view and a schematic cross-sectional view of a microchip and an extension trace in a terminal extension layer according to an embodiment of the present disclosure.
  • 8A, 8B, and 8C are schematic cross-sectional views of microchips and extension traces in terminal extension layers, respectively, according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram illustrating a structure formed by a chip first process according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram illustrating a structure formed by a chiplater process according to an embodiment of the present disclosure.
  • FIGS. 11A and 11B are schematic diagrams, respectively, of exemplary arrangements of chips and display units included in a display device according to some embodiments of the present disclosure.
  • 12A to 12F are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed.
  • FIGS. 13A to 13G are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed.
  • FIG. 14 is a schematic cross-sectional view of a semiconductor device (eg, a display device), which may be a large-scale display device or a tiled display device, according to some embodiments of the present disclosure.
  • a semiconductor device eg, a display device
  • a display device may be a large-scale display device or a tiled display device, according to some embodiments of the present disclosure.
  • FIG. 15 is a schematic cross-sectional view of a semiconductor device, such as a display device, schematically illustrating an upwardly emitting implementation, according to some embodiments of the present disclosure.
  • 16 is a schematic cross-sectional view of a semiconductor device, such as a display device, in accordance with some embodiments of the present disclosure.
  • 17A to 17I are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed.
  • FIG. 18 schematically shows a schematic cross-sectional view of a semiconductor device with terminals of a chip on two opposing sides of the chip, according to some embodiments of the present disclosure.
  • 19A to 19H are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device are performed according to an exemplary embodiment of the present disclosure, wherein terminals of a chip are located on upper and lower surfaces of the chip.
  • FIGS. 20A to 20F are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device are performed according to an exemplary embodiment of the present disclosure, wherein a driving element of the display device includes a TFT driving circuit, and the The manufacturing method is realized by the above-mentioned chip first process.
  • Fig. 21 is a partial enlarged view of part I of Fig. 20E.
  • 22 is a schematic cross-sectional view of a display device with LED chips and other chips in different layers according to some embodiments of the present disclosure.
  • FIG. 23 is a partial enlarged view of part II in FIG. 22 .
  • 24 is a schematic cross-sectional view of a display device with LED chips and other chips in different layers according to some embodiments of the present disclosure.
  • FIGS. 25A to 25F are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device are performed according to an exemplary embodiment of the present disclosure, wherein a driving element of the display device includes a TFT driving circuit, and the The manufacturing method is realized by the above-mentioned chiplater process.
  • 26A and 26B respectively schematically illustrate schematic cross-sectional views of via holes of a display device according to an embodiment of the present disclosure.
  • FIG. 27 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein the thin film transistor is a bottom gate type thin film transistor.
  • 28A and 28B are each a schematic block diagram of an acoustic sensor according to some embodiments of the present disclosure.
  • Figure 28C schematically illustrates the arrangement of acoustic sensors in a display according to some embodiments of the present disclosure.
  • 29 is a schematic cross-sectional view of a sensor-integrated display device, wherein the sensor is a Si-based sensor, according to some embodiments of the present disclosure.
  • FIG. 30 schematically shows the relationship between the increase factor of the output voltage and the number of the transducers connected in series in the sensor according to the embodiment of the present disclosure.
  • FIG. 31 is a schematic cross-sectional view of a sensor-integrated display device, wherein the sensor is a piezoelectric sensor including a piezoelectric thin film, according to some embodiments of the present disclosure.
  • FIG. 32 is a partial enlarged view of part III in FIG. 31 .
  • FIGS. 33A to 33C are schematic cross-sectional views respectively illustrating a structure formed after some steps of a method for fabricating a display device integrated with a sensor are performed according to some embodiments of the present disclosure, wherein the sensor is a piezoelectric film including a piezoelectric film. electrical sensor.
  • 34 is a schematic cross-sectional view of a sensor-integrated display device according to some embodiments of the present disclosure.
  • 35A to 35E are schematic cross-sectional views of structures formed after some steps of a method of fabricating a semiconductor device (eg, a display device) are performed according to exemplary embodiments of the present disclosure.
  • a semiconductor device eg, a display device
  • 36A schematically illustrates a top view of forming a plurality of extension traces during a post-alignment process in accordance with some embodiments of the present disclosure.
  • 36B and 36C respectively schematically illustrate top views of forming a plurality of extension traces during a post-alignment process according to some embodiments of the present disclosure.
  • 37A and 37B are cross-sectional views taken along line AA' in FIG. 36B .
  • FIG. 38 schematically shows a partial enlarged view of wiring between two chips.
  • 39A, 39B, and 39C respectively schematically illustrate photographing regions formed in a post-alignment process.
  • FIGS. 40A to 40C respectively schematically illustrate the arrangement of a driving chip and each pixel of a display device according to an embodiment of the present disclosure.
  • Figure 41 schematically shows the projection relationship of chips and pixels.
  • FIG. 42 is a schematic diagram of a gate TFT of a gate chip according to an embodiment of the present disclosure.
  • FIG 43 is a partial plan view of a display device including a gate chip according to an embodiment of the present disclosure.
  • 44A and 44B are respectively circuit connection diagrams of a display device including a gate chip according to an embodiment of the present disclosure.
  • the X axis, the Y axis and the Z axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a broader sense.
  • the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • an integrated circuit is a way of miniaturizing circuits (including semiconductor devices, passive devices, etc.), eg, devices fabricated on the surface of a semiconductor wafer.
  • an integrated circuit may also be referred to as a microcircuit, wafer, chip, or the like.
  • integrated circuits are produced in large quantities on a large semiconductor wafer through multiple steps such as photolithography, and then divided into several small pieces. This small piece is called a chip, and each chip is a collection of integrated circuits.
  • the semiconductor material used for the wafer is usually a single crystal of electronic grade silicon or other semiconductors such as gallium arsenide.
  • a bare die (expressed as die in English, also known as a bare chip, a bare chip, a die or a bare chip) is an unpackaged small integrated circuit made of semiconductor materials. The intended function of the integrated circuit is implemented on this small piece of semiconductor.
  • packaging is the process of assembling an integrated circuit into a chip final product, for example, placing the integrated circuit bare chip on a substrate that acts as a carrier, leading out the pins, and then fixing the package into a A whole.
  • the circuit pins on the integrated circuit bare chip are connected to external joints with wires, so as to facilitate the connection of other devices.
  • the package structure not only plays the role of mounting, fixing, sealing, protecting the chip and enhancing the electrical and thermal performance, but also connected to the pins of the package structure with wires through the contacts on the chip.
  • the wires are connected with other devices, thus realizing the connection between the internal chip and the external circuit.
  • the panel level packaging technology refers to sticking the semiconductor die on the carrier, and pulling the required circuit to the redistribution layer (referred to as RDL) on the end of the die, and then forming the package, without the need for package carrier board, not to mention the need for wire bonding and bumps (Bump in English), thereby reducing production costs.
  • the digital exposure process refers to a direct writing or maskless photolithography process, which can usually be implemented by a digital exposure machine.
  • a digital exposure process ie, without the use of a mask
  • multiple chips can be transferred to the substrate through a low-precision transfer process; the position of each terminal of the chip on the substrate can be read through Mapping, or the chip picture can be obtained through optical detection, and then the position of each terminal can be obtained through an algorithm
  • the coordinate information of each terminal is formed into a file that can be recognized by the digital exposure machine, and the digital exposure machine can perform an exposure process on the conductive layer according to the file to form a wiring layer that electrically connects the terminals of the chip.
  • the digital exposure process can automatically correct the positional deviation of each chip transferred to the substrate. For example, the accuracy of the digital exposure process can reach ⁇ 1 ⁇ m, therefore, the process difficulty caused by bonding can be greatly reduced and improved. Process accuracy.
  • terminal refers to the part of the chip that is electrically connected to external leads, traces, electrodes, etc., including, but not limited to, the pads of the chip.
  • a post-alignment process refers to a process for aligning terminals (eg, pads) of a chip.
  • a plurality of chips may be firstly transferred to a substrate through a process such as SMT or mass transfer, and then image analysis techniques are used to determine the positions of the pads of each chip transferred to the substrate (for example, Based on parameters such as coordinate information of each pad), area and morphology, based on the parameters and through a high-precision patterning process such as a photolithography process, an extended trace or lead electrically connected to the pad of each chip is formed to realize the realization of each chip. bonding.
  • the post-alignment process includes a high-precision patterning process such as a photolithography process, the precision thereof will be higher than that of the mass transfer process.
  • the offset accuracy of the metal extension traces formed by the photolithography machine is generally less than 0.6 microns, while the accuracy of the current mass transfer equipment is about 5-10 microns.
  • the technology can solve the problem of low transfer accuracy that occurs when microchips are transferred in large quantities.
  • the "post-alignment process" can be used to repair bad points in addition to identifying the terminals of the chip for automatic routing.
  • the post-alignment process it is possible to identify and obtain defective points, and obtain the coordinate information of the defective points; Extend traces or leads to fix individual bad points.
  • defect point includes a terminal having an open circuit in its electrical connection path.
  • position and relative position refer to the positions of components such as chips, chip bodies, etc. in a space coordinate system, for example, in an XYZ coordinate system, X, Y, Z may be used The coordinate value representation of the axis.
  • orientation refers to the angle of the chip, the chip body and other components relative to each coordinate axis in the space coordinate system. For example, in the XYZ coordinate system, it can be expressed as an angle relative to the X, Y, and Z axes.
  • maskless lithography can be roughly divided into two categories: (1) charged particle maskless lithography, such as electron beam direct writing and ion beam lithography. (2) Optical maskless technology, such as DMD maskless lithography, laser direct writing, interference lithography, diffractive optical element lithography, etc.
  • DMD maskless lithography is a technology derived from traditional optical lithography. Its exposure imaging method is basically similar to traditional projection lithography. The difference is that digital DMD is used instead of traditional masks.
  • the main principle It is to input the required lithography pattern into the DMD chip through the software through the computer, and change the rotation angle of the DMD chip micromirror according to the distribution of black and white pixels in the image, and irradiate the DMD chip through a collimated light source to form the required pattern.
  • a consistent light image is projected onto the surface of the substrate, and large-area microstructure fabrication is achieved by controlling the movement of the sample stage.
  • Electron beam lithography (often abbreviated as EBL) is a technique that uses an electron beam to draw custom patterns on a resist-covered surface. The electron beam alters the solubility of the resist, and by immersing it in a solvent (ie, developing), the exposed or unexposed areas of the resist can be selectively removed.
  • wire bonding is a process that utilizes heat, pressure or ultrasonic energy to tightly bond metal bonding wires to substrate pads.
  • wire bonds can be used to connect semiconductor die pads to I/O bond wires of a microelectronic package or metal wiring pads on a substrate with metal filaments.
  • the principle of wire bonding is to use heating, pressure or ultrasonic waves to destroy the oxide layer and contamination on the surface to be welded, resulting in plastic deformation, so that the metal bonding wire is in close contact with the surface to be welded, reaching the gravitational range between atoms and causing the interface. Inter-atom diffusion forms solder joints.
  • the expression “light emitting chip” refers to a chip configured to emit light of a specific wavelength, for example, the light emitting chip may include a light emitting diode chip including, but not limited to, a MiniLED chip or a MicroLED chip.
  • an inorganic light emitting diode refers to a light emitting element made of inorganic materials, wherein LED means an inorganic light emitting element different from OLED.
  • the inorganic light-emitting element may include a sub-millimeter light-emitting diode (Mini Light Emitting Diode, abbreviated as MiniLED in English) and a Micro Light Emitting Diode (Micro Light Emitting Diode, abbreviated as MicroLED in English).
  • micro light-emitting diodes ie MicroLED
  • sub-millimeter light-emitting diodes ie MiniLED
  • small light-emitting diodes with a grain size between MicroLED and traditional LEDs ie MicroLED
  • the grain size of MiniLED can be between 100 and 300 microns
  • the grain size of MicroLED can be between 10 and 100 microns.
  • SMT or SMT process refers to surface mount technology
  • mass transfer or mass transfer process is a technology that transfers a large number of microchips onto a target substrate.
  • a common mass transfer technology includes the following steps : Pick up microchips with very high spatial accuracy and orientation from a predetermined position; move these microchips to a predetermined position while maintaining the relative spatial position and orientation of the microchips; then, while maintaining the new relative position and orientation, have The microchips are selectively dispensed onto the target substrate at the new location.
  • PVDF refers to polyvinylidene fluoride material, which has piezoelectric properties.
  • the inventors have found that the size of the chip is increased by at least 20% compared to the original die size after being packaged.
  • the size of the chip can be reduced.
  • the impact of defects on the yield of chips per wafer can be effectively reduced.
  • the yield gradually increases, the equivalent diameter of a single wafer continues to increase, and the number of chips produced per wafer increases, which can greatly reduce the cost of the chip.
  • the expressions “chip”, “chip module”, “microchip”, “microchip”, etc. refer to chips of relatively small size, eg, unpackaged micron-scale chips.
  • the display substrate may include but not be limited to the following chips: sensor chips, control chips, logic operation chips, memory chips, driver chips, LED chips, and other functional chips, as well as digital-to-analog conversion circuits, Sub-module chips that are more subdivided, such as amplifier circuits, comparators, and counters. It should be understood that the display substrate may include at least one of the above-mentioned chips.
  • the expression “functional device” may include a device for realizing a specific function, which may include a single chip, a chip set composed of multiple chips, or a circuit structure, and other forms, for example, a functional device At least one of a thin film transistor and a sensor fabricated by a thin film process may be included.
  • regular shape refers to regular shapes, including but not limited to, rectangles, rounded rectangles, diamonds, squares, hexagons, octagons, circles, ovals, rectangles, triangle etc.
  • the semiconductor device includes: a substrate; a chip provided on the substrate, the chip comprising a chip body and a plurality of terminals provided on the chip body; a terminal expansion layer provided on the substrate, the The terminal expansion layer includes a conductive material, wherein the terminal expansion layer and at least one terminal are located on the same side of the chip body, the semiconductor device further includes a plurality of expansion traces located in the terminal expansion layer, the multiple Each extension wire is electrically connected to the plurality of terminals, respectively, for drawing out the plurality of terminals; and the orthographic projection of at least one extension wire on the substrate completely covers the terminal electrically connected to the extension wire at Orthographic projection on the substrate.
  • the terminals of the chip are drawn out through the terminal extension layer, which facilitates the bonding of the chips.
  • the semiconductor device includes: a substrate; a plurality of chips provided on the substrate, each chip including a chip body and a plurality of terminals provided on the chip body; a plurality of chips provided on the substrate a fixed connection part; a terminal expansion layer disposed on the substrate, the terminal expansion layer comprising a conductive material, wherein the plurality of fixed connection parts are respectively disposed adjacent to the plurality of chips; the semiconductor device further comprises: a plurality of extension wires in the terminal extension layer, the extension wires are used to electrically connect the plurality of chips; and the extension wires used to electrically connect two chips include at least a first wire segment and a second wire segment , the first wire segment is used to electrically connect a terminal of a chip and a fixed connection part adjacent to the chip, and the second wire segment is used to connect two fixed connection parts between the two chips.
  • the semiconductor device by providing the fixed connection portion, it is advantageous to realize the electrical connection between the respective chips.
  • the semiconductor device includes: a first substrate and a second substrate disposed opposite to each other; a chip disposed on the first substrate, the chip including a chip body and a plurality of first substrates disposed on the chip body a terminal; a terminal expansion layer disposed on the first substrate, the terminal expansion layer comprising a conductive material; and a plurality of second terminals disposed on the second substrate, wherein the terminal expansion layer and at least A first terminal is located on the same side of the chip body, and the semiconductor device further includes a plurality of extension wires in the terminal extension layer, the plurality of extension wires are respectively electrically connected to the plurality of first terminals.
  • the orthographic projection of the plurality of extension wires on the first substrate completely covers the first terminals electrically connected with the extension wires on the first substrate and the plurality of first terminals are respectively electrically connected to the plurality of second terminals through the plurality of extended traces, and the orthographic projection of the plurality of second terminals on the first substrate At least partially overlaps with an orthographic projection of the plurality of extended traces on the first substrate.
  • the terminals of the chip are drawn out through the terminal extension layer, which is beneficial to realize the bonding between the chip and other components.
  • the exemplary embodiments of the present disclosure are mainly described by taking display devices such as a display substrate, a display panel, and a display device as examples.
  • Embodiments of the present disclosure are not limited thereto, and may also be applied to other types of semiconductor devices including at least one chip.
  • the types of chips include but are not limited to light-emitting chips, sensing chips, control chips, and driving chips, such as LED chips, analog circuit chips, digital circuit chips, memory chips, digital-to-analog conversion chips, sensing (acoustic, optical, electrical, etc.) chips or other functional module chips.
  • FIG. 1 schematically illustrates a block diagram of a display device according to some exemplary embodiments of the present disclosure.
  • a chip with integrated functions for the display device may be split into a plurality of microchips, and each microchip may have fewer functions than a chip with integrated functions That is, the chip with integrated functions can be divided according to functions, so that a plurality of microchips are arranged in the display device.
  • the size of each microchip is smaller than the size of the chip with integrated functions, for example, each microchip may be an unpackaged micron-scale chip.
  • the size of the terminals on the microchip is smaller than that of the conventional chip, for example, the size of the terminals on the microchip is on the order of tens of microns, and may even be smaller than 10 microns.
  • the traditional bonding process cannot meet the dimensional accuracy of the terminals on the microchip; moreover, the accuracy of the existing mass transfer process cannot meet the dimensional accuracy of the terminals on the microchip.
  • a plurality of chips may be provided, and each chip may be used to realize one function.
  • the plurality of chips may include LED chips and chips related to display, such as driver chips, memory chips, digital-to-analog conversion chips, and information processing chips.
  • a control chip 1 a logic operation chip 2 , a memory chip 3 , a driver chip 4 and other functional chips 5 can be provided.
  • the driving chip 4 may be electrically connected to the display unit 6 .
  • the display unit 6 may include one of an LCD display (Liquid Crystal Display) unit, an OLED (Organic Light Emitting Diode) display unit, or an LED (Inorganic Light Emitting Diode) display unit.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • LED Inorganic Light Emitting Diode
  • FIG. 2 is a schematic diagram schematically illustrating an arrangement of a plurality of chips in a display substrate according to an embodiment of the present disclosure.
  • 3A to 3C are schematic diagrams respectively illustrating the relative positional relationship between functional unit groups and display areas in a display substrate according to an embodiment of the present disclosure.
  • a plurality of chips with specific functions may be interconnected to form a functional unit group CU.
  • the control chip 1 , the logic operation chip 2 , the memory chip 3 , the driver chip 4 and other functional chips 5 can be interconnected to form a functional unit group CU.
  • the display device may include a display substrate.
  • the display substrate may include a display area AA and a non-display area NA.
  • the display substrate may include a plurality of pixels PX located in the display area AA.
  • the plurality of functional unit groups CU may be periodically or aperiodically arranged on the base substrate of the display substrate.
  • the multiple functional unit groups CU may be located in the display area AA, or may be located in the non-display area NA.
  • some of the multiple functional unit groups CU may be located in the display area AA, and some of the multiple functional unit groups CU may be located in the non-display area NA.
  • multiple functional unit groups CU may be respectively located in multiple pixels PX, for example, one functional unit group CU may be set in one pixel PX.
  • one functional unit group CU may be shared by two or more pixels PX.
  • one functional unit group CU may be provided in some pixels PX, and no functional unit group CU may be provided in other pixels PX.
  • the functional unit group CU may only be set in a specific pixel PX to implement applications requiring low data volume, such as eye tracking and other application scenarios.
  • multiple functional unit groups CU may be interconnected as required to realize data interaction.
  • a semiconductor device eg, a display device
  • electrical connections within the chip, between multiple chips, and between the chips and the display unit can be realized, which solves the problem of the wiring precision of the microchip.
  • FIGS. 1 to 4 is a schematic diagram schematically illustrating an alignment relationship between a terminal (pad) on a substrate and a terminal (pad) on a chip in a semiconductor device (eg, a display substrate) according to an embodiment of the present disclosure.
  • the plurality of chips described above may be transferred to a substrate such as a substrate substrate through a bulk transfer process.
  • a substrate such as a substrate substrate
  • the alignment of the terminal p2 on the substrate and the terminal p1 on the chip can be achieved. Limited by the precision of the mass transfer process, a certain misalignment may occur between the terminal p2 on the substrate and the terminal p1 on the chip.
  • the terminals on the chip (eg p1 ) and the terminals on the substrate (eg p2 ) do not need to overlap, and the terminals on the chip (eg p1 ) in at least a part of the area are the same as The terminals on the substrate (eg p2) are not in face-to-face contact.
  • “there may be a certain misalignment between the terminal p2 on the substrate and the terminal p1 on the chip” can be understood as the difference between the terminal p1 on the chip and its ideal position that may occur during the chip transfer process. Positional deviation caused by misalignment between.
  • FIG. 4 For example, six pairs of terminals p2 on the substrate and terminals p1 on the chip are schematically shown in FIG. 4 .
  • the small dashed box represents the position of the terminal p2
  • the large dashed box represents the ideal position of the terminal p1 (ie, the position of the terminal p1 precisely aligned with the terminal p2).
  • the terminals are described as the first pair of terminals, the second pair of terminals, the third pair of terminals, the fourth pair of terminals, the fifth pair of terminals and the first pair of terminals in a top-to-bottom and left-to-right manner.
  • Six pairs of terminals Six pairs of terminals.
  • the terminal p1 In the first pair of terminals, the terminal p1 is located in its ideal position, in this case, the terminal p2 is precisely aligned with the terminal p1; in the second pair of terminals, the terminal p1 is shifted to the left by a certain distance relative to its ideal position , resulting in terminal p1 being shifted to the left by a certain distance relative to terminal p2; in the third pair of terminals, terminal p1 is displaced upward by a certain distance relative to its ideal position, causing terminal p1 to be displaced upward relative to terminal p2 a certain distance; in the fourth pair of terminals, terminal p1 is offset a certain distance to the right relative to its ideal position, resulting in terminal p1 being displaced a certain distance to the right and upward relative to terminal p2; in the fifth pair of terminals In the sixth pair of terminals, terminal p1 is deflected clockwise by a certain angle relative to its ideal position, resulting in a certain angle of clockwise deflection
  • the terminal p1 and the terminal p2 are precisely aligned, and the terminal p1 is offset relative to the terminal p2 in at least one of the first direction and the second direction. distance, the terminal p1 is deflected by a certain angle relative to the terminal p2.
  • the semiconductor device may include a plurality of repeating units PU arranged on the substrate in an array along a first direction D1 and a second direction D2.
  • Each repeating unit PU may include a plurality of the chips, and the plurality of chips located in each repeating unit PU are arranged on the substrate in an array along the first direction D1 and the second direction D2, or, each At least a portion of the plurality of chips within the repeating unit are arranged on the substrate in an array along a first direction and a second direction.
  • each repeating unit PU includes 3 chips, however, these numbers should not be regarded as limitations of the embodiments of the present disclosure.
  • a relative position of at least one chip in one repeating unit PU in the repeating unit and a corresponding chip in another repeating unit in the other repeating unit are not the same.
  • the orientation of at least one chip in one repeating unit in the repeating unit is not the same as the orientation of a corresponding chip in the other repeating unit in the other repeating unit .
  • the length of the extended traces used to lead out at least one terminal of at least one chip in one repeating unit corresponds to that used to lead out a corresponding chip in another repeating unit
  • the extension traces of the terminals are not of equal length.
  • the extending direction of the extended trace used to lead out at least one terminal of at least one chip in one repeating unit is the same as the extending direction of the extended wiring used to lead out the corresponding chip in another repeating unit.
  • the extension directions of the extension traces of the corresponding terminals are not the same.
  • corresponding chip can be understood as a chip at a corresponding position in each repeating unit.
  • a repeating unit located on the upper side The leftmost chip in the inner and the leftmost chip in another repeating unit located on the lower side are corresponding chips to each other.
  • a post-alignment process may be used to form extension traces on a terminal extension layer (ie, RDL) to electrically connect the terminal p1 and the terminal p2.
  • RDL terminal extension layer
  • the position of the terminal p1 and the terminal p2 can be identified by taking a photo
  • the lithography pattern can be designed according to the position of the terminal p1 and the terminal p2, and the exposure is performed by using a maskless lithography technique.
  • a plurality of extension wires RL are formed in the terminal extension layer RDL. Based on the designed lithography pattern, the plurality of extension wires RL are electrically connected to the terminal p1 and the terminal p2 according to design requirements.
  • it is not necessary to improve the alignment accuracy of the mass transfer process the electrical connection inside the microchip and between the microchips can be realized, and the wiring accuracy of the microchip is improved.
  • a plurality of chips CP may be formed on the carrier board SUB1, for example, a plurality of chips CP may be formed on the carrier board SUB1 in an array, or a plurality of chips CP may be formed on the carrier board SUB1 aperiodically .
  • the "chip CP" here can be the above-mentioned microchip, including but not limited to, the above-mentioned LED chip, control chip 1, logic operation chip 2, memory chip 3, driver chip 4, and other functional chips 5 and so on.
  • a plurality of chips CP are transferred onto the substrate SUB2 through a bulk transfer process.
  • an adhesive layer AD1 may be provided on the substrate SUB2.
  • the adhesive layer AD1 can play the role of fixing the chip.
  • the adhesive layer AD1 can be a whole surface or a patterned one.
  • multiple extended traces can be formed through a post-alignment process.
  • a metal layer ML1 and a photoresist layer PR1 may be deposited on the chip CP, and then, through a patterning process, a patterned photoresist layer PR1 is formed.
  • the metal layer ML1 is etched to form a patterned metal layer ML1
  • the patterned metal layer ML1 is the above-mentioned terminal extension layer RDL
  • a plurality of patterns formed in the terminal extension layer RDL are formed into a plurality of extensions
  • a wire RL is routed to electrically connect the various terminals.
  • the patterning process includes, but is not limited to, submicron exposure technologies such as digital exposure machines, laser direct writing, and EBL.
  • the chips can be transferred to the substrate through a mass transfer process with low positional accuracy, and then the chips with low positional accuracy can be identified and analyzed through a post-alignment process, for example, by taking pictures and images
  • the identification method identifies and analyzes the terminal p1 of the chip and the terminal p2 of the substrate, and determines the relative positional relationship between the terminals. Based on the results of the identification and analysis, an autorouting file is generated.
  • the photoresist layer PR1 may be patterned according to the automatic routing file. In this way, automatic wiring and high-precision chip bonding can be realized, and the integration of the microchip and the display unit can be realized.
  • the post-alignment process has at least the following advantages: the accuracy of the post-alignment process depends on the alignment accuracy of the optical exposure, and the alignment accuracy of the optical exposure is much higher than that of the mass transfer process. It is suitable for bonding of microchips; and, the post-alignment process adopts exposure, development and etching processes, which is more suitable for large-area, high-efficiency batch chip bonding.
  • chips on the same substrate may be the same or different in shape and function.
  • the pins of the terminal p1 of the chip are upward and the number is greater than or equal to 2, and the size and shape of each terminal p1 may be the same or different.
  • 6A and 6B are a schematic cross-sectional view and a schematic top view, respectively, of a microchip according to an embodiment of the present disclosure.
  • a plurality of chips CP are provided, and the functions of the plurality of chips CP may be different.
  • the shapes of the plurality of chips CP may be different in a cross-sectional view and a top view. For example, referring to FIG.
  • the chip CP may have various shapes such as a rectangle and a trapezoid in a cross-sectional view.
  • the chip CP may have various shapes such as a trapezoid, a rectangle, a diamond, a triangle, a circle, and an ellipse in a plan view.
  • FIGS. 7A , 7B and 7C are respectively a perspective view and a schematic cross-sectional view of a microchip and an extension trace in a terminal extension layer according to an embodiment of the present disclosure.
  • the chip CP has a trapezoidal shape in a cross-sectional view.
  • at least one side surface of the chip CP is relatively gentle, that is, the slope angle of at least one side surface of the chip CP is less than 90°, for example, less than 70°.
  • the extended traces can be directly drawn from the terminal p1 of the chip CP. As shown in FIG.
  • the extended traces RL drawn from the terminal p1 of the chip CP can be formed on the side surface with a slope angle less than 90°.
  • a terminal expansion layer and at least one redistribution layer may be provided, and for convenience of description, they will be referred to as a terminal expansion layer RDL1 and a redistribution layer RDL2, respectively.
  • the expansion layers located in the terminal expansion layer RDL1 and the redistribution layer RDL2 The traces are referred to as the extension trace RL1 and the first trace RL2, respectively.
  • a planarization layer PLN1 may be provided between the terminal extension layer RDL1 and the redistribution layer RDL2.
  • the extended trace RL1 is directly led out from the terminal p1 of the chip CP.
  • the first trace RL2 is electrically connected to the extended trace RL1 through a via hole penetrating the planarization layer PLN1. In this way, the terminals leading out of the chip can be realized, which facilitates the electrical connection between the various terminals of the chip.
  • the chip CP has a substantially rectangular shape in a cross-sectional view.
  • the sides of the chip CP are relatively steep, that is, the slope angle of the sides of the chip CP is substantially equal to 90° or close to 90°, for example, in the range of 70° ⁇ 90°.
  • the extended wiring is not suitable to be directly formed on the side surface of the chip CP, that is, it is not suitable to directly lead out the extended wiring from the terminal p1 of the chip CP.
  • the planarization layer PLN1 may be formed on the side of the chip CP away from the substrate first, and the height of the planarization layer PLN1 is greater than that of the chip CP, so that the planarization layer PLN1 can cover the chip CP and the terminals p1 thereon. Then, the extended trace RL1 is formed through a post-alignment process. As shown in FIG.
  • the semiconductor device may include a substrate SUB2, an adhesive layer AD1 disposed on the substrate SUB2, a chip CP disposed on the adhesive layer AD1, and a planarization layer disposed on a side of the chip CP away from the substrate PLN1, and an extended trace RL1 disposed on the side of the planarization layer PLN1 away from the substrate.
  • the extended trace RL1 may be electrically connected to the terminal p1 through a via hole penetrating the planarization layer PLN1. In this way, the terminals of the chip can be drawn out, which is beneficial to the electrical connection between the various terminals of the chip.
  • a planarization layer may be formed on at least one side surface of the chip CP to form a side surface having a smaller slope.
  • extended traces can be formed on the sides of the planarization layer with a smaller slope.
  • planarization layer PLN1 may have a single-layer or multi-layer structure.
  • FIG. 8A, 8B, and 8C are schematic cross-sectional views of microchips and extension traces in terminal extension layers, respectively, according to some embodiments of the present disclosure.
  • a plurality of chips CP are disposed on the substrate SUB2, and there is a height difference between at least two chips CP.
  • the two chips with the height difference are respectively referred to as chip CP1 and chip CP2.
  • the wiring can be realized by the one-step post-alignment process, that is, by the one-step post-alignment process
  • a layer of terminal expansion layer RDL1 is formed in a quasi-process, and a plurality of expansion traces RL1 located in the terminal expansion layer RDL1 can lead out the terminals of the chip CP1 and the chip CP2.
  • the semiconductor device may include a substrate SUB2, an adhesive layer AD1 disposed on the substrate SUB2, chips CP1, CP2 disposed on the adhesive layer AD1, and a planarization layer disposed on the side of the chips CP1, CP2 away from the substrate PLN1, and a terminal extension layer RDL1 disposed on the side of the planarization layer PLN1 away from the substrate.
  • the terminal extension layer RDL1 is provided with a plurality of extension wires RL1.
  • the height of the planarization layer PLN1 is greater than that of each of the chips CP1, CP2.
  • a part of the extended traces RL1 can be electrically connected to the terminal p1 of the chip CP1 through a via hole passing through the planarization layer PLN1, and another part of the extended trace RL1 can be electrically connected to the terminal p1 of the chip CP2 through a via hole passing through the planarization layer PLN1.
  • the terminals of the chip CP1 and the chip CP2 can be drawn out, which is beneficial to the electrical connection between the respective terminals of the chips.
  • the terminals of multiple chips can be drawn out, which is beneficial to the electrical connection between the terminals of multiple chips.
  • wiring can be realized by at least two-step post-alignment processes, that is, for thin
  • the chip CP1 is first subjected to a post-alignment process and wiring, and then the post-alignment process and wiring are sequentially performed on the chips CP2 with different thickness ranges (eg, thicker).
  • a planarization layer needs to be added between the latter post-alignment process and the previous post-alignment process.
  • the semiconductor device may include a substrate SUB2, an adhesive layer AD1 disposed on the substrate SUB2, chips CP1 and CP2 disposed on the adhesive layer AD1, a planarization layer PLN1 disposed on the side of the chip CP1 away from the substrate, A terminal expansion layer RDL1 disposed on the side of the planarization layer PLN1 away from the substrate, a planarization layer PLN2 disposed on the side of the terminal expansion layer RDL1 away from the substrate, and a redistribution layer disposed on the side of the planarization layer PLN2 away from the substrate RDL2.
  • the terminal extension layer RDL1 is provided with an extension wiring RL1
  • the redistribution layer RDL2 is provided with a first wiring RL2.
  • the extended wire RL1 may be electrically connected to the terminal p1 of the chip CP1 through a via hole passing through the planarization layer PLN1, and the first wire RL2 may be electrically connected to the terminal p1 of the chip CP2 through a via hole passing through the planarization layer PLN2.
  • the terminals of the chip CP1 and the chip CP2 can be drawn out, which is beneficial to the electrical connection between the respective terminals of the chips.
  • a spacer may be prepared on the substrate first, wherein the height difference of the chips is - The process limit of the post-alignment exposure process in the vertical direction ⁇ the height of the pad ⁇ the height difference of the chip; then, the wiring can be realized by a one-step post-alignment process.
  • the semiconductor device may include a substrate SUB2, an adhesive layer AD1 disposed on the substrate SUB2, a pad PS disposed on the adhesive layer AD1, a chip CP2, a chip CP1 disposed on the pad PS, a chip CP1 disposed on the chip
  • the planarization layer PLN1 on the side of CP1 and CP2 away from the substrate, and the terminal extension layer RDL1 on the side of the planarization layer PLN1 away from the substrate.
  • the terminal extension layer RDL1 is provided with a plurality of extension wires RL1.
  • the height of the planarization layer PLN1 is greater than that of each of the chips CP1, CP2, that is, the height of the planarization layer PLN1 away from the surface of the substrate SUB2 is greater than the height of each of the chips CP1, CP2 away from the surface of the substrate SUB2.
  • the orthographic projection of the chip CP1 on the substrate is within the orthographic projection of the pad PS on the substrate, and the area of the orthographic projection of the chip CP1 on the substrate is smaller than the area of the orthographic projection of the pad PS on the substrate. In this way, the alignment accuracy between the chip CP1 and the pad PS does not need to be high, which is beneficial for placing the chip CP1 on the pad PS.
  • a part of the extended traces RL1 can be electrically connected to the terminal p1 of the chip CP1 through a via hole passing through the planarization layer PLN1, and another part of the extended trace RL1 can be electrically connected to the terminal p1 of the chip CP2 through a via hole passing through the planarization layer PLN1.
  • the terminals of the chip CP1 and the chip CP2 can be drawn out, which is beneficial to the electrical connection between the respective terminals of the chips.
  • the height of the substrate PS may also be slightly larger than the height difference of the chip, for example, the difference between the height of the substrate PS minus the height difference of the chip may be smaller than the height difference of the post-alignment The process limit of the exposure process in the vertical direction.
  • the chip may be formed on the substrate using a chip first process or a chiplater process.
  • the chip may be formed first, and then the driving unit of the display device may be formed, that is, a chip first process; or, the driving unit of the display device may be formed first, and then formed
  • the chip is the chiplater process.
  • the chip may include a chip body CPM and a plurality of terminals p1 , p2 disposed on the chip body CPM.
  • the chip body CPM may include a first surface CPM1, a second surface CPM2, a first side surface CPM3 and a second side surface CPM4, the second surface CPM2 and the first surface CPM1 being respectively located opposite to the chip body.
  • the first side surface CPM3 and the second side surface CPM4 are respectively located on side surfaces of the chip body, and each of the first side surface CPM3 and the second side surface CPM4 is connected to the The first surface CPM1 and the second surface CPM2, the first surface CPM1 faces or contacts the adhesive layer AD1, and at least one terminal p1, p2 is disposed on the surface of the chip body except the first surface CPM1 ( For example, on CPM2, CPM3, CPM4).
  • the substrate may include a first substrate surface SUBP on which the chip is disposed, the first substrate surface SUBP including a first substrate edge SUBP1.
  • the orthographic projection of at least one extended trace RL on the substrate is inclined with respect to the first substrate edge SUBP1.
  • the orthographic projection of the second surface CPM2 on the substrate has a regular shape, as shown in FIG. 6B , and the regular shape includes, but is not limited to, rectangle, rounded rectangle, diamond, square, hexagon, Octagon, circle, ellipse, rectangle, triangle, etc.
  • the orthographic projection of the second surface CPM2 on the substrate includes a first edge CPM21 .
  • the first edge CPM21 is inclined with respect to the first substrate edge SUBP1.
  • a first included angle is formed between the extension line of the orthographic projection of the at least one extended trace RL on the substrate and the extension line of the first substrate edge SUBP1, and the first included angle is greater than 0 ° is less than 90°.
  • a second included angle is formed between the extension line of the first edge CPM21 and the extension line of the first substrate edge SUBP1, and the second included angle is greater than 0° and less than 90°.
  • the orientation of the chip relative to the substrate cannot be deflected or can only be deflected by a small angle, for example, the deflection angle needs to be less than 10°. In this way, the effective bonding of each terminal of the chip can be ensured.
  • the orientation of the chip relative to the substrate may be deflected by a certain angle, and the deflection angle may be between 0° and 90°, for example, between 0° and 50°, and may be between 1° and 1°.
  • the chip may be deflected by a large angle relative to the substrate, eg, may be greater than 10°.
  • the extended wiring layer can still be formed through a subsequent post-alignment process to achieve effective bonding of the chip and avoid the formation of defective spots.
  • FIG. 9 is a schematic diagram illustrating a structure formed by a chip first process according to an embodiment of the present disclosure.
  • 10 is a schematic diagram illustrating a structure formed by a chiplater process according to an embodiment of the present disclosure.
  • the display device may include a substrate SUB2, an adhesive layer AD1 disposed on the substrate SUB2, a chip CP1 disposed on the adhesive layer AD1, and a terminal extension layer disposed on the side of the chip CP1 away from the substrate RDL1, the planarization layer PLN1 arranged on the side of the terminal extension layer RDL1 away from the substrate, the redistribution layer RDL2 arranged on the side of the planarization layer PLN1 away from the substrate, the planarization layer arranged on the side of the redistribution layer RDL2 away from the substrate layer PLN2, and a redistribution layer RDL3 and a driving unit DRU disposed on the side of the planarization layer PLN2 away from the substrate.
  • the terminal extension layer RDL1 is provided with an extension wiring RL1
  • the redistribution layer RDL2 is provided with a first wiring RL2
  • the redistribution layer RDL3 is provided with a second wiring RL3.
  • at least a part of the extension wire RL1 is disposed on the sidewall of the chip CP1, and is directly electrically connected to the terminal p1 of the chip CP1.
  • the first wire RL2 may be electrically connected to the extended wire RL1 through a via hole passing through the planarization layer PLN1
  • the second wire RL3 may be electrically connected to the first wire RL2 through a via hole passing through the planarization layer PLN2.
  • the second wire RL3 and the driving unit DRU may be located on the same layer, and the second wire RL3 may be electrically connected to the driving unit DRU.
  • the terminals of the chip CP1 can be drawn out, and the electrical connection of the chip CP1 and the drive unit DRU can be realized.
  • the chip CP1 is closer to the substrate SUB2 than the driving unit DRU.
  • the chip CP1 may be formed on the substrate SUB2 first, and then a plurality of terminal extension layers are formed through a post-alignment process, and then the driving unit DRU is formed.
  • the processing precision of microchips is usually higher than that of driving units such as thin film transistors. It is beneficial to avoid the barriers of the processing technology of the driving units such as thin film transistors, so as to realize high-resolution display.
  • the display device may include a substrate SUB2, a driving unit DRU disposed on the substrate SUB2, a planarization layer PLN1 disposed on the side of the driving unit DRU away from the substrate, and a planarization layer PLN1 disposed on a flat surface.
  • the terminal extension layer RDL1 on the side of the chemical layer PLN1 away from the substrate, the adhesive layer AD1 arranged on the side of the terminal extension layer RDL1 away from the substrate, the chip CP1 arranged on the adhesive layer AD1, the chip CP1 arranged on the side of the chip CP1 away from the substrate Redistribution layer RDL2.
  • the terminal extension layer RDL1 is provided with an extension wiring RL1, and the redistribution layer RDL2 is provided with a first wiring RL2.
  • the first trace RL2 is disposed on the sidewall of the chip CP1, and is directly electrically connected to the terminal p1 of the chip CP1.
  • the first trace RL2 may be electrically connected to the extension trace RL1 through a via hole passing through the adhesive layer AD1, and the extension trace RL1 may be electrically connected to the driving unit DRU through a via hole passing through the planarization layer PLN1. In this way, the electrical connection between the chip CP1 and the driving unit DRU can be achieved.
  • the chip CP1 is further away from the substrate SUB2 than the drive unit DRU.
  • the driving unit DRU may be formed on the substrate SUB2 first, and then the terminal extension layer may be formed through a post-alignment process, and then the chip CP1 may be formed.
  • the driving units such as thin film transistors are first transferred or prepared on the substrate, and then the chip is transferred to the substrate, so as to avoid the processing of the driving units such as thin film transistors from affecting the chip performance.
  • the driving unit DRU includes, but is not limited to, a thin film transistor (TFT) driving circuit, a MOS driving circuit, a driving chip (IC), and the like.
  • the driving unit or the driving element can be used for the LED chip to provide electrical signals to control the luminous brightness thereof.
  • the driving unit or driving element may be a plurality of pixel driving circuits connected with each light-emitting diode chip in a one-to-one correspondence, or a plurality of microchips connected with each light-emitting diode chip in a one-to-one correspondence and other structures, each LED chip can be controlled to emit different brightness gray scales.
  • the specific circuit structure of the driving unit or the driving element can be set according to actual needs, which is not limited by the embodiments of the present disclosure.
  • FIGS. 11A and 11B are schematic diagrams, respectively, of exemplary arrangements of chips and display units included in a display device according to some embodiments of the present disclosure.
  • the chip CP1 may be a driving chip for driving the display unit
  • the display unit DU may be an LED chip that can emit light.
  • one pixel may include 3 LED chips, for example, corresponding to R, G, and B sub-pixels.
  • One chip CP1 may correspond to one pixel, that is, one driving chip is used to drive one pixel.
  • one chip CP1 may correspond to multiple pixels, that is, one driving chip is used to drive multiple pixels.
  • a plurality of pixels can be driven in an active matrix system (AM system) using a driver chip.
  • AM system active matrix system
  • a plurality of light emitting diodes are arranged in an array along the first direction X and the second direction Y.
  • the first direction X is the row direction and the second direction Y is the column direction.
  • the embodiments of the present disclosure are not limited thereto, and the first direction and the second direction may be any direction, as long as the first direction and the second direction intersect.
  • the plurality of LED chips are not limited to being arranged in a straight line, but can also be arranged in a curved line, a circular arrangement or an arbitrary manner, which can be determined according to actual needs, which is not limited by the embodiments of the present disclosure.
  • the chip CP1 is not limited to a driver chip for driving the display unit, but may also include a control chip, a logic operation chip, a memory chip, and other functional chips.
  • chip CP1 the chip for driving or controlling the LED
  • CP3 the LED chip for emitting light
  • the manufacturing method of the display device may include at least two process routes.
  • the manufacturing method of the display device according to the exemplary embodiment of the present disclosure may include at least the following steps. It should be noted that the case where the size of the chip CP1 is small may include: the size of the chip CP1 is substantially equal to or smaller than the size of the LED chip, or in other words, the area of the orthographic projection of the chip CP1 on the substrate is the same as the size of the LED chip on the substrate. The ratio of the area of the orthographic projection is less than or equal to 1.2.
  • an adhesive layer AD1 is coated or adhered on the substrate SUB2.
  • the substrate SUB2 may be a glass substrate.
  • the material of the adhesive layer AD1 may include hot melt adhesive, laser curable adhesive or UV curable adhesive, and the like.
  • the driving chip CP1 and/or the LED chip CP3 are transferred to the substrate SUB2 by SMT or a mass transfer process, and fixed on the substrate by the adhesive layer AD1.
  • the driving chip CP1 and the LED chip CP3 may both be located on the adhesive layer AD1, and the terminals p1 of the driving chip CP1 and the LED chip CP3 may be upward, ie on the side of the chip away from the substrate.
  • the driver chip CP1 may use a Si-based CMOS process, which is not limited in the embodiments of the present disclosure.
  • a passivation layer PVX1 is deposited on the side of the driving chip CP1 and the LED chip CP3 away from the substrate, and a planarization layer PLN1 is coated on the side of the passivation layer PVX1 away from the substrate.
  • the passivation layer PVX1 may include a material such as silicon dioxide for insulating and increasing the adhesion of the cover layer OC1.
  • the planarization layer PLN1 may include a resin material, and is used to fill in the level difference between the driving chip CP1 and the LED chip CP3 and other chips to achieve planarization.
  • the passivation layer PVX1 may not be prepared.
  • a passivation layer PVX2 may be formed on the side of the planarization layer PLN1 away from the substrate.
  • the passivation layer PVX2 may include a material such as silicon nitride, which is used to isolate the water vapor in the planarization layer PLN1 and prevent the water vapor in the planarization layer PLN1 from corroding the upper terminal extension layer.
  • the substrate (which may be referred to as a backplane) on which the chip is formed is photographed, and image recognition technology is used to determine the position of the terminal p1 of each driver chip CP1 and LED chip CP3 disposed on the backplane , according to the corresponding logic to generate the graphics file of the opening of the terminal area (ie the pad area).
  • a photoresist is coated on the backplane, and the photoresist is patterned by a digital direct writing or digital exposure machine according to the above graphic file, and then the passivation layer PVX2, the planarization layer PLN1 and the passivation layer PVX2 are etched.
  • the parts of the passivation layer PVX2, the planarization layer PLN1 and the passivation layer PVX2 located above the terminals can also be directly etched with EBL to form vias exposing a part of the terminals p1 of the respective driving chips CP1 and LED chips CP3. VH3.
  • a terminal extension layer RDL1 is prepared on the side of the passivation layer PVX2 away from the substrate. Then, a graphic file of the terminal extension layer RDL1 is automatically generated according to the connection relationship of each terminal and based on the previously determined positions of the terminals p1 of each of the driver chip CP1 and the LED chip CP3.
  • the terminal extension layer RDL1 is patterned by digital exposure or EBL to form a plurality of extension traces RL1. That is, through the post-alignment process, the extension wirings RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL1.
  • the terminal extension layer RDL1 may include a single film layer structure or a stacked layer structure composed of a plurality of film layers.
  • the terminal extension layer RDL1 may contain a metal material such as copper (Cu).
  • the terminal extension layer RDL1 may include materials such as titanium/aluminum/titanium (Ti/Al/Ti), molybdenum aluminum molybdenum (Mo/Al/Mo), etc. .
  • the redistribution layer RDL2 may be prepared according to the requirements of line interconnection.
  • the capping layer PLN2 may be formed on the side of the terminal extension layer RDL1 away from the substrate. Then, a redistribution layer RDL2 is formed on the side of the cap layer PLN2 away from the substrate.
  • the redistribution layer RDL2 may be prepared by a conventional photolithography process to form the first wiring RL2 for electrically connecting the respective chips in the redistribution layer RDL2.
  • Embodiments of the present disclosure are not limited thereto, and the redistribution layer RDL2 may also be prepared through a post-alignment process.
  • the capping layer PLN2 may include silicon nitride, silicon oxide, or a laminated structure composed of silicon nitride and silicon oxide, and may also include a polymer material for isolating and insulating the terminal extension layer RDL1 and the redistribution layer RDL2.
  • a third-layer wiring, a fourth-layer wiring, etc. may also be prepared, which is not particularly limited in the embodiment of the present disclosure.
  • a semiconductor device may be a display device, which may include: a substrate SUB2; an adhesive layer AD1 disposed on the substrate SUB2; A number of chips CP1, CP3, each of which may include at least one terminal p1; a passivation layer PVX1 disposed on the side of the plurality of chips CP1, CP3 away from the substrate; a planarization layer disposed on the side of the passivation layer PVX1 away from the substrate PLN1; the passivation layer PVX2 arranged on the side of the planarization layer PLN1 away from the substrate; the terminal extension layer RDL1 arranged on the side of the passivation layer PVX2 away from the substrate; the cover layer arranged on the side of the terminal extension layer RDL1 away from the substrate PLN2; and a redistribution layer RDL2 provided on the side of the cover layer PLN2 away from the substrate.
  • a plurality of extension wirings RL1 are located in the terminal extension
  • a plurality of chips CP1, CP3 may be located on the same layer, that is, the surfaces of the chips CP1, CP3 facing the substrate may all be in contact with the adhesive layer AD1.
  • Some terminals p1 in the chips CP1 and CP3 may be electrically connected through a plurality of extension wires RL1.
  • Other terminals p1 in the chips CP1 and CP3 may be electrically connected through a plurality of first traces RL2.
  • FIGS. 13A to 13G are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed.
  • the manufacturing method of the display device according to the exemplary embodiment of the present disclosure may include at least the following steps.
  • the larger size of the chip CP1 may include: the size of the chip CP1 is larger than the size of the LED chip, or in other words, the area of the orthographic projection of the chip CP1 on the substrate and the orthographic projection of the LED chip on the substrate The area ratio is greater than 1.2.
  • an adhesive layer AD1 is coated or adhered on the substrate SUB2.
  • the LED chip CP3 is transferred to the substrate SUB2 through an SMT or mass transfer process, and is fixed on the substrate through an adhesive layer AD1.
  • the terminal p1 of the LED chip CP3 may face upwards, that is, on the side of the chip away from the substrate.
  • a passivation layer PVX1 is deposited on the side of the driving chip CP1 and the LED chip CP3 away from the substrate, and a planarization layer PLN1 is coated on the side of the passivation layer PVX1 away from the substrate.
  • a passivation layer PVX2 may be formed on the side of the planarization layer PLN1 away from the substrate.
  • the substrate (which may be referred to as a backplane) on which the chip is formed is photographed, and image recognition technology is used to determine the position of the terminal p1 of each LED chip CP3 disposed on the backplane, according to the corresponding
  • the logic generates a graphic file of the opening of the terminal area (ie, the pad area).
  • a photoresist is coated on the backplane, and the photoresist is patterned by a digital direct writing or digital exposure machine according to the above graphic file, and then the passivation layer PVX2, the planarization layer PLN1 and the passivation layer PVX2 are etched.
  • the portions of the passivation layer PVX2, the planarization layer PLN1 and the passivation layer PVX2 above the terminals may also be directly etched with EBL to form via holes VH3 exposing a portion of the terminals p1 of each LED chip CP3.
  • a terminal extension layer RDL1 is prepared on the side of the passivation layer PVX2 away from the substrate. Then, according to the connection relationship of the respective terminals, and based on the previously determined positions of the terminals p1 of the respective LED chips CP3, a graphic file of the terminal extension layer RDL1 is automatically generated.
  • the terminal extension layer RDL1 is patterned by digital exposure or EBL to form a plurality of extension traces RL1. That is, through the post-alignment process, the extension wirings RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL1.
  • the redistribution layer RDL2 may be prepared according to the requirements of line interconnection.
  • the capping layer PLN2 may be formed on the side of the terminal extension layer RDL1 away from the substrate. Then, a redistribution layer RDL2 is formed on the side of the cap layer PLN2 away from the substrate.
  • the redistribution layer RDL2 may be prepared by a conventional photolithography process to form first traces RL2 for electrically connecting the respective chips in the redistribution layer RDL2.
  • Embodiments of the present disclosure are not limited thereto, and the redistribution layer RDL2 may also be prepared through a post-alignment process.
  • a third-layer wiring, a fourth-layer wiring, etc. may also be prepared, which is not particularly limited in the embodiment of the present disclosure.
  • the driving chip CP1 is transferred onto the substrate SUB2 through SMT or a bulk transfer process.
  • the terminal p1 of the driving chip CP1 can be electrically connected to the first trace RL2 in the redistribution layer RDL2 through eutectic soldering, solder paste soldering, conductive glue, etc., so as to realize the electrical connection between the driving chip CP1 and the LED chip CP3. connect.
  • a semiconductor device may be a display device, which may include: a substrate SUB2; an adhesive layer AD1 disposed on the substrate SUB2; LED chips CP3, each LED chip CP3 may include at least one terminal p1; a passivation layer PVX1 disposed on the side of the plurality of LED chips CP3 away from the substrate; a planarization layer disposed on the side of the passivation layer PVX1 away from the substrate PLN1; the passivation layer PVX2 arranged on the side of the planarization layer PLN1 away from the substrate; the terminal extension layer RDL1 arranged on the side of the passivation layer PVX2 away from the substrate; the cover layer arranged on the side of the terminal extension layer RDL1 away from the substrate PLN2; a redistribution layer RDL2 disposed on the side of the cover layer PLN2 away from the substrate; and at least one chip CP1 disposed on the side of the redistribution layer R
  • chip CP1 and chip CP3 may be located on different layers.
  • a plurality of LED chips CP3 may be located on the same layer, all in contact with the adhesive layer AD1.
  • the driving chip CP1 may be located on a side of the plurality of LED chips CP3 away from the substrate.
  • the LED chip CP3 located on the lower layer is electrically connected to the driving chip CP1 located on the upper layer through the extended wiring RL1 and the first wiring RL2.
  • FIG. 14 is a schematic cross-sectional view of a semiconductor device (eg, a display device), which may be a large-scale display device or a tiled display device, according to some embodiments of the present disclosure.
  • a binding area BND for electrically connecting a circuit board eg, a flexible circuit board FPC
  • the binding area BND does not need to punch holes or lead wires, and the binding area BND is located on the back side of the light-emitting area of the LED, thereby facilitating seamless splicing display.
  • the edge of the display device does not need to be provided with extended wiring areas, so that the edge size of the formed display device is only related to the edge of the cutting process of the substrate.
  • the width of the laser cutting edge can be controlled within 20 microns, and the width of the heat affected zone can be less than 50 microns. Therefore, a smaller frame can be realized, and the four sides of the display device can be realized. Equal width, which is beneficial for splicing display.
  • the main light-emitting surface of the LED may face the substrate SUB2, that is, the driving chip CP1 may be located on the backside of the light-emitting side of the LED, so that the driving chip CP1 may not occupy the area of the light-emitting region, that is, the driving chip CP1 is on the substrate SUB2
  • the orthographic projection on the bottom SUB2 may at least partially overlap with the orthographic projection of the LED chip CP3 on the substrate SUB2. Therefore, a plurality of driving chips CP1 can be arranged with a small pitch, which is beneficial to realize high-resolution display.
  • FIG. 15 is a schematic cross-sectional view of a semiconductor device, such as a display device, schematically illustrating an upwardly emitting implementation, according to some embodiments of the present disclosure.
  • the LED chip CP3 may emit light upward, that is, the driving chip CP1 may be located on the light-emitting side of the LED. That is, the orthographic projection of the driving chip CP1 on the substrate SUB2 does not overlap with the orthographic projection of the LED chip CP3 on the substrate SUB2.
  • the display device may further include: an adhesive layer AD2 disposed on the side of the redistribution layer RDL2 away from the substrate; a driving chip CP1 disposed on the side of the adhesive layer AD2 away from the substrate; The passivation layer PVX3 on the side of the chip CP1 away from the substrate; the planarization layer PLN3 on the side of the passivation layer PVX3 away from the substrate; and the redistribution layer RDL3 on the side of the planarization layer PLN3 away from the substrate.
  • a plurality of second wirings RL3 may be disposed in the redistribution layer RDL3.
  • the plurality of terminals p1 of the driving chip CP1 may face upward, that is, face a side away from the substrate.
  • the driving chip CP1 is disposed on the adhesive layer AD2, which is beneficial to the fixing of the driving chip CP1.
  • the process of preparing the redistribution layer RDL3 and the second trace RL3 may be similar to the process of preparing the terminal expansion layer RDL1 and the expansion trace RL1, that is, the post-alignment process is also used to prepare the redistribution layer RDL3 and the second trace RL3 .
  • the driving chip CP1 can be electrically connected to the first wiring RL2 through the second wiring RL3, the first wiring RL2 is electrically connected to the extension wiring RL1, and the extension wiring RL1 is electrically connected to the terminal p1 of the LED chip CP3. In this way, the electrical connection between the driving chip CP1 and the LED chip CP3 can be realized.
  • 17A to 17I are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device according to an exemplary embodiment of the present disclosure are performed.
  • an adhesive layer AD1 is coated or adhered on the substrate SUB2.
  • the substrate SUB2 may be a glass substrate, a polyimide (ie, PI) substrate or a quartz substrate.
  • the adhesive layer AD1 can use laser dissociating glue, temperature change dissociating glue, UV dissociating glue, etc. In this way, specific means can be used for peeling off in the subsequent process to remove the substrate SUB2.
  • the material of the substrate may include, but is not limited to, glass, quartz, plastic, silicon, polyimide, and the like.
  • the terminals may be columnar structures.
  • the material of the terminal may include conductive materials, such as metal materials, etc., specifically, may be at least one selected from gold, silver, copper, aluminum, molybdenum, gold alloys, silver alloys, copper alloys, aluminum alloys, molybdenum alloys, and the like. one or a combination of at least two, which is not limited by the embodiments of the present disclosure.
  • the LED chip CP3 and/or the functional element CP4 are transferred to the substrate SUB2 by SMT or a mass transfer process, and fixed on the substrate by the adhesive layer AD1.
  • the LED chip CP3 and the functional element CP4 may both be located on the adhesive layer AD1, and the terminals p1 of the LED chip CP3 and the functional element CP4 may face upward, ie, on the side of the chip away from the substrate.
  • the functional element CP4 here can be the above-mentioned microchip, which is used to implement specific functions, including but not limited to, a control chip, a memory chip, a logic operation chip, a sensor chip, and the like.
  • the substrate (which may be referred to as a backplane) provided with the LED chip CP3 and the functional element CP4 is photographed, and image recognition technology is used to determine each LED chip CP3 provided on the backplane and the coordinates and area of the terminal p1 of the functional element CP4 to generate a graphic file of the terminal area (ie, the pad area).
  • a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by a digital direct writing or digital exposure machine according to the above-mentioned graphic file. Then, according to the patterned photoresist, the metal layer is etched to form the terminal extension layer RDL1.
  • a plurality of extension wires RL1 are formed in the terminal extension layer RDL1, and the plurality of extension wires RL1 can be respectively electrically connected to the terminals p1 of the LED chips CP3 and the functional elements CP4 to lead out the terminals p1. That is, through the post-alignment process, the extension wirings RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL1.
  • the terminal extension layer RDL1 may include a single film layer structure or a stacked layer structure composed of a plurality of film layers.
  • the terminal extension layer RDL1 may contain a metal material such as copper (Cu).
  • the terminal extension layer RDL1 may include materials such as titanium/aluminum/titanium (Ti/Al/Ti), molybdenum aluminum molybdenum (Mo/Al/Mo), etc. .
  • a planarization layer PLN1 is coated on the side of the terminal extension layer RDL1 away from the substrate.
  • the planarization layer PLN1 may include a resin-based material for filling the level difference between each LED chip CP3 and the functional element CP4 to achieve planarization.
  • a passivation layer PVX2 may be formed on the side of the planarization layer PLN1 away from the substrate.
  • the passivation layer PVX2 may include a material such as silicon nitride, which is used to isolate the water vapor in the planarization layer PLN1 and prevent the water vapor in the planarization layer PLN1 from corroding the upper terminal extension layer.
  • via holes may be formed through the planarization layer PLN1 and the passivation layer PVX2 to expose at least a portion of each extended trace RL1 .
  • a metal layer is deposited on the side of the passivation layer PVX2 away from the substrate, and a redistribution layer RDL2 is formed through a patterning process including steps of coating photoresist, exposing, developing, and etching.
  • a plurality of first wirings RL2 are formed in the redistribution layer RDL2.
  • the plurality of first wires RL2 may be electrically connected to the plurality of extension wires RL1 through the above-mentioned via holes, so as to further lead out the respective terminals p1.
  • an adhesive layer AD2 is formed on the side of the redistribution layer RDL2 away from the substrate.
  • the side of the adhesive layer AD2 away from the substrate forms the driving element DRU.
  • the driving element DRU can be fixed on the substrate through the adhesive layer AD2.
  • the driving element DRU may include a driving chip CP1, and the driving chip CP1 may be transferred to the substrate SUB2 by SMT or a mass transfer process, and fixed on the substrate by an adhesive layer AD2.
  • the driving element DRU may include electronic elements such as thin film transistors, that is, a plurality of thin film transistors may be formed on the substrate SUB2 through a process of preparing TFTs.
  • a planarization layer PLN2 is formed on the side of the driving element DRU away from the substrate.
  • the planarization layer PLN2 may include a resin-based material for filling the level difference between the driving elements DRU to achieve planarization.
  • via holes may be formed through the planarization layer PLN2 and the adhesive layer AD2 to expose at least a portion of each of the first traces RL2.
  • a metal layer is deposited on the side of the planarization layer PLN2 away from the substrate, and a redistribution layer RDL3 is formed through a patterning process including steps of coating photoresist, exposing, developing, and etching. For example, a plurality of second wirings RL3 are formed in the redistribution layer RDL3.
  • the plurality of second wires RL3 can be electrically connected to the plurality of first wires RL2 through the above-mentioned via holes to further lead out each terminal p1 and electrically connect the driving element DRU to each LED chip CP3 and each functional element CP4.
  • a planarization layer PLN3 is formed on the side of the redistribution layer RDL3 away from the substrate. Then, the substrate SUB4 is attached on the surface of the planarization layer PLN3 away from the substrate SUB2 through the adhesive layer AD3.
  • the substrate SUB2 is separated from the devices formed thereon by means of laser dissociation, temperature dissociation, or UV dissociation.
  • a protective layer PTL is coated on the side of each LED chip CP3 and each functional element CP4 away from the substrate SUB4.
  • a patterning process is performed on the protective layer PTL to expose surfaces of the respective LED chips CP3 and the respective functional elements CP4 close to the protective layer PTL.
  • the protective layer PTL can protect, for example, the metal layer of the extended wiring RL1, so that the metal layer is not exposed to the air, and at the same time, the main light-emitting surface of each LED chip CP3 and the functional surface of each functional element CP4 can be exposed. Conducive to lighting and realizing their respective functions.
  • the step of performing a patterning process on the protective layer PTL is optional.
  • at least a part of the surface of the chips or functional elements facing the protective layer PTL may not be exposed, and in this case, it is not necessary to perform a patterning process on parts of the protective layer PTL corresponding to these chips or functional elements.
  • the protective layer PTL may include an insulating layer, that is, to play an insulating role.
  • the terminals p1 of each chip are located on one surface of the chip.
  • the LED chip CP3 includes at least two terminals p1, and the at least two terminals p1 are both located on the surface of the LED chip CP3 away from the light-emitting surface, that is, On the back of the light-emitting side.
  • embodiments of the present disclosure are not limited to such a terminal arrangement.
  • the chip CP includes at least two terminals p1 located on two opposite sides of the chip CP, respectively.
  • the chip CP includes a surface facing the substrate SUB2 (ie, the lower surface in FIG. 18 ), and two opposite sides of the chip CP are located on either side of the lower surface, respectively.
  • the chip CP shown in FIG. 18 may be the above-mentioned LED chip CP3 and/or functional element CP4.
  • the extension traces RL1 located in the terminal extension layer RDL1 may also be electrically connected to at least two terminals p1 respectively, so as to lead out the terminals p1 of the chip.
  • 19A to 19H are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device are performed according to an exemplary embodiment of the present disclosure, wherein terminals of a chip are located on upper and lower surfaces of the chip.
  • an adhesive layer AD1 is coated or adhered on the substrate SUB2.
  • the substrate SUB2 may be a glass substrate, a polyimide (ie, PI) substrate or a quartz substrate.
  • the adhesive layer AD1 can use laser dissociating glue, temperature change dissociating glue, UV dissociating glue, etc. In this way, specific means can be used for peeling off in the subsequent process to remove the substrate SUB2.
  • a conductive layer CDL1 is formed on the side of the adhesive layer AD1 away from the substrate.
  • the conductive layer CDL1 may include conductive materials such as metal and conductive oxide.
  • An adhesive layer AD2 is formed on the side of the conductive layer CDL1 away from the substrate.
  • the adhesive layer AD2 can be adhesive and can be evaporated by heating and reflowing.
  • the adhesive layer AD2 may contain solder resist.
  • the chip CP (eg, the LED chip CP3 and/or the functional element CP4 ) is transferred onto the substrate SUB2 by SMT or a mass transfer process.
  • the chip CP has terminals on both the surface close to the substrate SUB2 (ie, the lower surface in the figure) and the surface farther from the substrate SUB2 (ie, the upper surface in the figure).
  • the terminal located on the lower surface is referred to as a terminal p11
  • the terminal located on the upper surface is referred to as a terminal p12.
  • the adhesive layer AD2 is evaporated, so that the terminal p11 can be electrically connected to the conductive layer ADL1. In this way, good conduction between the chip CP and the underlying conductive layer ADL1 is achieved.
  • a passivation layer PVX1 is formed on the side of the chip CP away from the substrate, and a planarization layer PLN1 is formed on the side of the passivation layer PVX1 away from the substrate.
  • the substrate (which may be referred to as a backplane) provided with the chip CP is photographed, and the coordinates and area, and generate a graphic file of the terminal area (ie, the pad area).
  • a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by a digital direct writing or digital exposure machine according to the above-mentioned graphic file. Then, according to the patterned photoresist, the metal layer is etched to form the terminal extension layer RDL1.
  • a plurality of extension wires RL1 are formed in the terminal extension layer RDL1, and the plurality of extension wires RL1 can be electrically connected to the terminals p12 of the respective chips CP through via holes, so as to lead out the respective terminals p12. That is, through the post-alignment process, the extension wirings RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL1.
  • an adhesive layer AD3 is formed on the side of the terminal extension layer RDL1 away from the substrate.
  • the driving element DRU is formed on the side of the adhesive layer AD3 away from the substrate.
  • the driving element DRU can be fixed on the substrate through the adhesive layer AD3.
  • a planarization layer PLN2 is formed on the side of the driving element DRU away from the substrate.
  • via holes may be formed through the planarization layer PLN2 and/or the adhesive layer AD3 to expose at least a portion of the respective extension traces RL1 and the terminals of the driving element DRU.
  • a metal layer is deposited on the side of the planarization layer PLN2 away from the substrate, and a redistribution layer RDL2 is formed through a patterning process including steps of coating photoresist, exposing, developing, and etching. For example, a plurality of first wirings RL2 are formed in the redistribution layer RDL2.
  • the plurality of first traces RL2 may be electrically connected to the plurality of extension traces RL1 through the above-mentioned via holes respectively, so as to further lead out each terminal p12 and electrically connect the driving element DRU and each chip CP.
  • a planarization layer PLN3 is formed on the side of the redistribution layer RDL2 away from the substrate. Then, the substrate SUB4 is attached on the surface of the planarization layer PLN3 remote from the substrate SUB2 through the adhesive layer AD4.
  • the substrate SUB2 is separated from the devices formed thereon by means of laser dissociation, temperature dissociation, or UV dissociation.
  • a protective layer PTL is coated on the side of the conductive layer CDL1 away from the substrate SUB4. Then, a patterning process is performed on the protective layer PTL to expose a portion of the conductive layer CDL1 (eg, a portion corresponding to each chip CP) close to the surface of the protective layer PTL. In this way, the terminal p11 of the chip CP can be drawn out through the exposed part of the conductive layer CDL1.
  • the semiconductor device as a display device and the driving element of the display device including a TFT driving circuit as an example.
  • FIGS. 20A to 20F are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device are performed according to an exemplary embodiment of the present disclosure, wherein a driving element of the display device includes a TFT driving circuit, and the The manufacturing method is realized by the above-mentioned chip first process.
  • an adhesive layer AD1 is coated or adhered on the substrate SUB2.
  • the substrate SUB2 may be a glass substrate, a polyimide (ie, PI) substrate or a quartz substrate.
  • the adhesive layer AD1 can use laser dissociating glue, temperature change dissociating glue, UV dissociating glue, etc. In this way, specific means can be used for peeling off in the subsequent process to remove the substrate SUB2.
  • a plurality of chips CP are transferred onto the substrate SUB2 through an SMT or bulk transfer process, and are fixed on the substrate through an adhesive layer AD1.
  • the plurality of chips CP may include, but are not limited to, LED chips, driver chips, memory chips, control chips, digital-to-analog conversion chips, information processing chips, sensor chips, and the like.
  • the LED chip can be an LED chip with a sapphire substrate removed, and the driver chip, memory chip, control chip, digital-to-analog conversion chip, information processing chip, and sensor chip can be Si-based chips, and the Si-based chips can be For a bare chip without a package structure, the height of the chip can be less than 100 microns.
  • chips CP1, CP2, CP3 and CP4 are schematically shown.
  • the four chips are respectively referred to as chips CP1, CP2, CP3 and CP4.
  • chip CP1 may be a control chip
  • chip CP2 may be a control chip
  • the memory chip, the chip CP3 can be an LED chip, and the chip CP4 can be a sensor chip. It should be understood that embodiments of the present disclosure are not limited to the arrangement shown in FIG. 20B .
  • the chips CP1, CP2, CP3, and CP4 may all be located on the adhesive layer AD1, and the terminals p1 of the respective chips CP1, CP2, CP3, and CP4 may face upward, that is, on the side of the chip away from the substrate.
  • the substrate (which may be referred to as a backplane) provided with the chips CP1, CP2, CP3, and CP4 is photographed, and image recognition technology is used to determine the respective chips CP1, CP2,
  • the coordinates and area of the terminal p1 of CP3 and CP4 generate a graphic file of the terminal area (ie, the pad area).
  • a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by a digital direct writing or digital exposure machine according to the above-mentioned graphic file.
  • the metal layer is etched to form the terminal extension layer RDL1.
  • a plurality of extension wires RL1 are formed in the terminal extension layer RDL1, and the plurality of extension wires RL1 can be respectively electrically connected to the terminals p1 of the chips CP1, CP2, CP3, and CP4 to lead out the terminals p1. That is, through the post-alignment process, the extension wirings RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL1.
  • a planarization layer PLN1 is coated on the side of the terminal extension layer RDL1 away from the substrate.
  • the passivation layer PVX1 may be formed on the side of the planarization layer PLN1 close to the substrate, and the passivation layer PVX2 may be formed on the side of the planarization layer PLN1 away from the substrate.
  • the passivation layer PVX1 and the passivation layer PVX2 may include materials such as silicon nitride, silicon oxide, etc., for isolating water vapor in the planarization layer PLN1 and preventing the water vapor in the planarization layer PLN1 from corroding the terminal extension layer.
  • via holes VH1 may be formed through the passivation layer PVX1 , the planarization layer PLN1 , and the passivation layer PVX2 to expose at least a portion of each extended trace RL1 .
  • the planarization layer PLN1 may include a resin-based material, such as polyimide (ie, PI) and other materials, for filling the level difference between the chips CP1, CP2, CP3, and CP4, achieve flattening.
  • a resin-based material such as polyimide (ie, PI) and other materials, for filling the level difference between the chips CP1, CP2, CP3, and CP4, achieve flattening.
  • the planarization layer PLN1 may include a low-temperature-curable planarization material, for example, an acrylic resin-based material.
  • the cost of the low-temperature-curable planarizing material is lower than that of the polyimide-based material, thereby helping to reduce the cost of the product.
  • a planarization material that can be cured at a low temperature is used, and then a low-temperature oxide TFT process or other semiconductor devices that can be fabricated at a low temperature can be used to complete the fabrication of the entire TFT device.
  • the curing temperature of the low-temperature-curable planarizing material can be less than 250°C, and accordingly, the TFT device can be prepared below 250°C in the TFT process, which can reduce the impact of high temperature in the TFT process on the performance of the microchip. risk of injury.
  • the thickness of the planarization layer PLN1 is higher than the maximum height of each chip CP1 , CP2 , CP3 , and CP4 by 10 ⁇ m or more.
  • a metal layer is deposited on the side of the passivation layer PVX2 away from the substrate, and a redistribution layer RDL2 is formed through a patterning process including steps of coating photoresist, exposing, developing, and etching.
  • a plurality of first wirings RL2 are formed in the redistribution layer RDL2.
  • the plurality of first wires RL2 may be electrically connected to the plurality of extension wires RL1 through the above-mentioned via holes, so as to further lead out the respective terminals p1.
  • 26A and 26B respectively schematically illustrate schematic cross-sectional views of via holes of a display device according to an embodiment of the present disclosure.
  • the redistribution layer RDL2 In the process of forming the redistribution layer RDL2, a part of the metal layer needs to be deposited in the via hole VH1, so that the plurality of first traces RL2 in the redistribution layer RDL2 can pass through the via hole VH1 and the terminal extension layer RDL1 respectively.
  • a plurality of extension traces RL1 in the are electrically connected.
  • the insulating layer between the terminal extension layer RDL1 and the redistribution layer RDL2 may be formed using conventional organic materials.
  • the shape of the via hole VH1 in the cross-sectional view is an inverted trapezoid shape to facilitate the deposition of a part of the metal layer in the via hole VH1 .
  • the terminal extension layer RDL1 may be used as a seed layer, and the metal layer (eg, a copper layer) may be plated by an electrochemical method or an electroless plating method.
  • a metal layer with the same thickness as the combination of the passivation layer PVX1, the planarization layer PLN1 and the passivation layer PVX2 is grown to fill the via hole VH1, so that the plurality of first traces RL2 in the redistribution layer RDL2 can be respectively
  • the via holes VH1 are electrically connected to a plurality of extension traces RL1 located in the terminal extension layer RDL1.
  • the insulating layer between the terminal extension layer RDL1 and the redistribution layer RDL2 may be formed using a high temperature resistant organic material.
  • the method of hard mask layer-exposure development-dry etching-removal of hard mask layer can be used to form relatively vertical via holes.
  • the shape of the via hole VH1 in the cross-sectional view may be a rectangle. That is, the area of the opening of the via hole VH1 on the side close to the terminal extension layer RDL1 is substantially equal to the area of the opening of the via hole VH1 on the side close to the redistribution layer RDL2. Therefore, in this embodiment, the requirements for the profile of the via hole are lower, and the via hole with an opening size of less than 10 microns can be formed, which is beneficial to improve the PPI of the display device.
  • the number of layers of the wiring layers can also be increased.
  • the redistribution layers RDL3 and RDL4 can also be formed on the side of the redistribution layer RDL2 away from the substrate.
  • the adjacent two layers An insulating layer can be used for isolation and insulation between the trace layers.
  • a backplane including the respective chips CP1, CP2, CP3, CP4 and a terminal extension layer is formed, and then, driving elements including TFT driving circuits can be formed on the backplane. That is, in this embodiment, the display device is formed using a chip first process.
  • Fig. 21 is a partial enlarged view of part I of Fig. 20E.
  • a barrier layer BRL and a buffer layer BFL may be sequentially formed on the side of the redistribution layer RDL2 away from the substrate.
  • the film structure of the TFT may be formed on the side of the buffer layer BFL away from the substrate.
  • an active layer, a gate insulating layer GI1 , a conductive layer CDL1 , a gate insulating layer GI2 , a conductive layer CDL2 , an interlayer dielectric layer IDL and a conductive layer CDL3 may be sequentially formed on the side of the buffer layer BFL away from the substrate.
  • the TFT driving circuit may include at least one thin film transistor and at least one storage capacitor, the gate of the thin film transistor (ie TFT) and one electrode of the storage capacitor may be located in the conductive layer CDL1, and the other electrode of the storage capacitor may be located in the conductive layer CDL2 , the source and drain electrodes of the thin film transistor may be located in the conductive layer CDL3.
  • a plurality of second traces RL3 may be located in the conductive layer CDL3.
  • the second wire RL3 may be electrically connected to the first wire RL2 through a via hole penetrating through the gate insulating layer GI1 , the gate insulating layer GI2 and the interlayer dielectric layer IDL.
  • the source and drain electrodes of the thin film transistor may be electrically connected to the source and drain regions of the active layer through via holes penetrating the gate insulating layer GI1 , the gate insulating layer GI2 and the interlayer dielectric layer IDL.
  • planarization layer PLN2 may be formed on the side of the conductive layer CDL3 away from the substrate.
  • the thin film transistors included in the above-mentioned TFT driving circuit may include, but are not limited to, polysilicon TFTs, low temperature polysilicon TFTs, oxide TFTs, and the like.
  • the substrate SUB4 may be attached on the surface of the planarization layer PLN3 remote from the substrate SUB2 through the adhesive layer AD3.
  • the substrate SUB2 is separated from the devices formed thereon by means of laser dissociation, temperature dissociation or UV dissociation.
  • a protective layer PTL is coated on the side of each chip CP1 , CP2 , CP3 , and CP4 away from the substrate SUB4 .
  • a patterning process is performed on the protective layer PTL to expose surfaces of the respective chips CP1, CP2, CP3, CP4 close to the protective layer PTL.
  • the protective layer PTL can protect, for example, the metal layer of the extended trace RL1, so that the metal layer is not exposed to the air, and at the same time, the functional surfaces of each chip CP1, CP2, CP3, and CP4 can be exposed, which is beneficial to the realization of each chip. function.
  • 20F is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure.
  • the semiconductor device according to some embodiments of the present disclosure may be a display device, for example, the display device may be a ⁇ LED display device.
  • It can include: a substrate SUB4; an adhesive layer AD3 arranged on the substrate SUB4; a planarization layer PLN2 arranged on the side of the adhesive layer AD3 away from the substrate; a conductive layer CDL3 arranged on the side of the planarization layer PLN2 away from the substrate be arranged on the interlayer dielectric layer IDL on the side of the conductive layer CDL3 away from the substrate; be arranged on the conductive layer CDL2 on the side of the interlayer dielectric layer IDL away from the substrate; be arranged on the grid insulation on the side of the conductive layer CDL2 away from the substrate layer GI2; the conductive layer CDL1 arranged on the side of the gate insulating layer GI2 away from the substrate; the active layer ACT arranged on the side of the conductive layer CDL1 away from the substrate; the buffer layer BFL arranged on the side of the active layer ACT away from the substrate The barrier layer BRL that is arranged on the side of the buffer layer BFL away from the substrate;
  • the TFT driving circuit may include at least one thin film transistor and at least one storage capacitor, the gate of the thin film transistor (ie TFT) and one electrode of the storage capacitor may be located in the conductive layer CDL1, and the other electrode of the storage capacitor may be located in the conductive layer CDL2 , the source and drain electrodes of the thin film transistor may be located in the conductive layer CDL3.
  • the gate of the thin film transistor ie TFT
  • one electrode of the storage capacitor may be located in the conductive layer CDL1
  • the other electrode of the storage capacitor may be located in the conductive layer CDL2
  • the source and drain electrodes of the thin film transistor may be located in the conductive layer CDL3.
  • a plurality of extension wires RL1 may be located in the terminal extension layer RDL1.
  • a plurality of first routing lines RL2 may be located in the redistribution layer RDL2.
  • a plurality of second wirings RL3 may be located in the conductive layer CDL3.
  • Each of the chips CP1, CP2, CP3, CP4 may comprise at least one terminal p1.
  • the terminals p1 of the respective chips CP1, CP2, CP3, and CP4 are led out through the extended wiring RL1.
  • the plurality of first wires RL2 may be respectively electrically connected to the plurality of extension wires RL1 through via holes penetrating through the passivation layer PVX1, the planarization layer PLN1 and the passivation layer PVX2.
  • the plurality of second wirings RL3 may be electrically connected to the first wirings RL2 through via holes penetrating through the gate insulating layer GI1 , the gate insulating layer GI2 and the interlayer dielectric layer IDL, respectively.
  • the source and drain electrodes of the thin film transistor may be electrically connected to the source and drain regions of the active layer through via holes penetrating the gate insulating layer GI1 , the gate insulating layer GI2 and the interlayer dielectric layer IDL. In this way, the electrical connection between the TFT driving circuit and the chip, and the electrical connection between multiple chips can be realized.
  • FIG. 22 is a schematic cross-sectional view of a display device with LED chips and other chips in different layers according to some embodiments of the present disclosure.
  • FIG. 23 is a partial enlarged view of part II in FIG. 22 . 22 and 23, considering the difference in process and performance (such as temperature resistance) between LED chips and display-related and sensing-related Si-based chips, LED chips and other chips can be disposed on different sides of the TFT .
  • the LED chip can be disposed on the side of the thin film transistor close to the substrate SUB2, and other chips can be disposed on the side of the thin film transistor away from the substrate SUB2.
  • the chips CP1 , CP2 , and CP4 located on the upper layer may be electrically connected to the LED chip CP3 located on the lower layer through a plurality of second wirings RL3 located in the redistribution layer RDL3 .
  • the display device may be a ⁇ LED (ie miniLED) display device, which may include: a substrate SUB2; an adhesive layer AD1 disposed on the substrate SUB2; an LED chip CP3 disposed on the side of the adhesive layer AD1 away from the substrate ;
  • the terminal expansion layer RDL1 is arranged on the side of the LED chip CP3 away from the substrate;
  • the passivation layer PVX1 is arranged on the side of the terminal expansion layer RDL1 away from the substrate;
  • the planarization layer PLN1 is arranged on the side of the passivation layer PVX1 away from the substrate ; Be arranged on the passivation layer PVX2 on the side of the planarization layer PLN1 away from the substrate; Be arranged on the redistribution layer RDL2 on the side of the passivation layer PVX2 away from the substrate; Be arranged on the barrier layer BRL on the side of the redistribution layer RDL2 away from the substrate and/or buffer layer BFL; active layer ACT
  • the TFT driving circuit may include at least one thin film transistor and at least one storage capacitor, the gate of the thin film transistor (ie TFT) and one electrode of the storage capacitor may be located in the conductive layer CDL1, and the other electrode of the storage capacitor may be located in the conductive layer CDL2 , the source and drain electrodes of the thin film transistor may be located in the conductive layer CDL3.
  • the gate of the thin film transistor ie TFT
  • one electrode of the storage capacitor may be located in the conductive layer CDL1
  • the other electrode of the storage capacitor may be located in the conductive layer CDL2
  • the source and drain electrodes of the thin film transistor may be located in the conductive layer CDL3.
  • a plurality of extension wires RL1 may be located in the terminal extension layer RDL1.
  • a plurality of first routing lines RL2 may be located in the redistribution layer RDL2.
  • a plurality of second wirings RL3 may be located in the conductive layer CDL3.
  • a plurality of third wirings RL4 may be located in the redistribution layer RDL3.
  • Each of the chips CP1, CP2, CP3, CP4 may comprise at least one terminal p1.
  • the terminals p1 of the respective chips CP1, CP2, and CP4 can be led out through the second wiring RL3.
  • the terminals p1 of the chips CP1, CP2, and CP4 may be electrically connected through the second wiring RL3.
  • At least one third wire RL4 may be electrically connected to at least one of the second wire RL3 and the source and drain of the thin film transistor through a via hole passing through the adhesive layer AD2 and the planarization layer PLN2.
  • the plurality of first wires RL2 may be respectively electrically connected to the plurality of extension wires RL1 through via holes penetrating through the passivation layer PVX1, the planarization layer PLN1 and the passivation layer PVX2.
  • the plurality of second wirings RL3 may be electrically connected to the first wirings RL2 through via holes penetrating through the gate insulating layer GI1 , the gate insulating layer GI2 and the interlayer dielectric layer IDL, respectively.
  • the source and drain electrodes of the thin film transistor may be electrically connected to the source and drain regions of the active layer through via holes penetrating through the gate insulating layer GI1 , the gate insulating layer GI2 and the interlayer dielectric layer IDL. In this way, the electrical connection between the TFT driving circuit and the chip, and the electrical connection between multiple chips can be realized.
  • the chips CP1, CP2, CP4 and the LED chip CP3 are located on opposite sides of the thin film transistor.
  • a plurality of terminal extension layers may be provided to realize electrical connection between the plurality of chips CP1 , CP2 , and CP4 located in the upper layers.
  • a terminal extension layer RDL4 and a passivation layer PVX4 may be provided between the passivation layer PVX3 and the planarization layer PLN3.
  • the passivation layer PVX4 is disposed on the side of the planarization layer PLN3 away from the substrate SUB4, and the terminal extension layer RDL4 is disposed between the passivation layer PVX4 and the passivation layer PVX3.
  • a plurality of extension traces RL5 may be located in the terminal extension layer RDL4.
  • the chips CP1, CP2, CP4 may include at least 3 terminals p1.
  • the third wiring RL4 located in the redistribution layer RDL3 can lead out the terminals p1 located on both sides.
  • the extension traces RL5 in the terminal extension layer RDL4 may electrically connect the terminal p1 in the middle of one chip and the terminal p1 in the middle of the other chip.
  • FIGS. 25A to 25F are schematic cross-sectional views of structures formed after some steps of a manufacturing method of a display device are performed according to an exemplary embodiment of the present disclosure, wherein a driving element of the display device includes a TFT driving circuit, and the The manufacturing method is realized by the above-mentioned chiplater process.
  • a TFT driving circuit may be formed on the substrate SUB2.
  • the thin film transistors in the above-mentioned TFT driving circuit may include, but are not limited to, polysilicon TFTs, low temperature polysilicon TFTs, oxide TFTs, and the like.
  • the barrier layer BRL and the buffer layer BFL can be sequentially formed on the substrate SUB4. Then, the film structure of the TFT may be formed on the side of the buffer layer BFL away from the substrate.
  • an active layer ACT, a gate insulating layer GI1, a conductive layer CDL1, a gate insulating layer GI2, a conductive layer CDL2, an interlayer dielectric layer IDL and a conductive layer CDL3 may be sequentially formed on the side of the buffer layer BFL away from the substrate.
  • the TFT driving circuit may include at least one thin film transistor and at least one storage capacitor, the gate of the thin film transistor (ie TFT) and one electrode of the storage capacitor may be located in the conductive layer CDL1, and the other electrode of the storage capacitor may be located in the conductive layer CDL2 , the source and drain electrodes of the thin film transistor may be located in the conductive layer CDL3.
  • a plurality of second traces RL3 may be located in the conductive layer CDL3.
  • the source and drain electrodes of the thin film transistor may be electrically connected to the source and drain regions of the active layer through via holes penetrating the gate insulating layer GI1 , the gate insulating layer GI2 and the interlayer dielectric layer IDL.
  • the planarization layer PLN1 may be formed on the side of the conductive layer CDL3 away from the substrate, and the conductive layer CDL4 may be formed on the side of the planarization layer PLN1 away from the substrate.
  • a plurality of third traces RL4 may be located in the conductive layer CDL4.
  • the plurality of third wires RL4 may be electrically connected to the plurality of second wires RL3 and the sources and drains of the thin film transistors through via holes penetrating through the planarization layer PLN1, respectively.
  • the TFT driving circuit is first formed on the substrate SUB4, and then each chip and at least one terminal extension layer are formed on the backplane on which the TFT driving circuit is formed, that is, the chiplater process is used to form the display device.
  • an adhesive layer AD2 is formed on the side of the conductive layer CDL4 away from the substrate. Then, the plurality of chips CP are transferred to the substrate SUB4 by SMT or a mass transfer process, and are fixed on the substrate SUB4 by the adhesive layer AD2.
  • Each chip CP may include at least two terminals p1, and in the illustrated embodiment, the terminal p1 of each chip CP faces upward, ie, toward the side of the chip away from the substrate SUB4.
  • the plurality of chips CP may include, but are not limited to, LED chips, driver chips, memory chips, control chips, digital-to-analog conversion chips, information processing chips, sensor chips, and the like.
  • the LED chip can be an LED chip with a sapphire substrate removed, and the driver chip, memory chip, control chip, digital-to-analog conversion chip, information processing chip, and sensor chip can be Si-based chips, and the Si-based chips can be Bare chip without package structure.
  • FIG. 25C four chips are schematically shown. For the convenience of description, the four chips are respectively referred to as chips CP1, CP2, CP3 and CP4.
  • chip CP1 may be a control chip
  • chip CP2 may be a control chip
  • the memory chip, the chip CP3 can be an LED chip, and the chip CP4 can be a sensor chip. It should be understood that embodiments of the present disclosure are not limited to the arrangement shown in FIG. 25C.
  • the substrate SUB4 may be a glass substrate, a polyimide (ie, PI) substrate or a quartz substrate.
  • the adhesive layer AD2 may include, but is not limited to, thermal adhesive, laser curable adhesive, photoresist, UV curable adhesive and other adhesive materials.
  • a patterning process may be used to form a plurality of via holes VH2 in the adhesive layer AD2 to expose at least a portion of the third trace RL4 located in the conductive layer CDL4.
  • the patterning process here can use a known photolithography process, including steps such as photoresist coating, exposure, development, and etching, and a mask can be used in the exposure process.
  • a substrate (which may be called a backplane) provided with the chips CP1, CP2, CP3, and CP4 is photographed, and image recognition technology is used to determine the respective chips CP1, CP2,
  • the coordinates and area of the terminal p1 of CP3 and CP4 generate a graphic file of the terminal area (ie, the pad area).
  • a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by a digital direct writing or digital exposure machine according to the above-mentioned graphic file. Then, according to the patterned photoresist, the metal layer is etched to form the terminal extension layer RDL1.
  • a plurality of extension wires RL1 are formed in the terminal extension layer RDL1, and the plurality of extension wires RL1 can be respectively electrically connected to the terminals p1 of the chips CP1, CP2, CP3, and CP4 to lead out the terminals p1. That is, through the post-alignment process, the extension wirings RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL1.
  • At least one extended trace RL1 may be electrically connected to the TFT driving circuit, eg, to the source or drain of the thin film transistor, through the third trace RL4 located in the conductive layer CDL4.
  • the at least one extension wire RL1 may also be electrically connected to at least two of the chips CP1, CP2, CP3, and CP4. In this way, electrical connection between the TFT driver circuit and the chip, as well as electrical connection between multiple chips, can be achieved.
  • a passivation layer PVX1 and a planarization layer PLN2 may be sequentially formed on a side of the terminal extension layer RDL1 away from the substrate.
  • redistribution layers RDL2 and RDL3 can also be formed on the side of the terminal expansion layer RDL1 away from the substrate.
  • the adjacent two layers An insulating layer can be used for isolation and insulation between the trace layers.
  • the semiconductor device may be a display device, for example, the display device may be a ⁇ LED display device. It can include: a substrate SUB4; a barrier layer BRL arranged on the substrate SUB4; a buffer layer BFL arranged on the side of the barrier layer BRL away from the substrate; an active layer ACT arranged on the side of the buffer layer BFL away from the substrate;
  • the gate insulating layer GI1 is arranged on the side of the active layer ACT away from the substrate;
  • the conductive layer CDL1 is arranged on the side of the gate insulating layer GI1 away from the substrate;
  • the gate insulating layer GI2 is arranged on the side of the conductive layer CDL1 away from the substrate;
  • the conductive layer CDL2 on the side of the gate insulating layer GI2 away from the substrate; the interlayer dielectric layer IDL arranged on the side of the conductive layer CDL2 away from the substrate; the conductive layer CDL3 arranged on the side of the
  • the TFT driving circuit may include at least one thin film transistor and at least one storage capacitor, the gate of the thin film transistor (ie TFT) and one electrode of the storage capacitor may be located in the conductive layer CDL1, and the other electrode of the storage capacitor may be located in the conductive layer CDL2 , the source and drain electrodes of the thin film transistor may be located in the conductive layer CDL3.
  • the gate of the thin film transistor ie TFT
  • one electrode of the storage capacitor may be located in the conductive layer CDL1
  • the other electrode of the storage capacitor may be located in the conductive layer CDL2
  • the source and drain electrodes of the thin film transistor may be located in the conductive layer CDL3.
  • a plurality of extension wires RL1 may be located in the terminal extension layer RDL1.
  • Each of the chips CP1, CP2, CP3, CP4 may comprise at least one terminal p1.
  • the terminals p1 of the respective chips CP1, CP2, CP3, and CP4 are led out through the extended wiring RL1.
  • a plurality of second wirings RL3 may be located in the conductive layer CDL3.
  • the source and drain electrodes of the thin film transistor may be electrically connected to the source and drain regions of the active layer through via holes penetrating the gate insulating layer GI1 , the gate insulating layer GI2 and the interlayer dielectric layer IDL.
  • a plurality of third traces RL4 may be located in the conductive layer CDL4.
  • the plurality of third wirings RL4 may be electrically connected to the plurality of second wirings RL3 and the sources and drains of the thin film transistors through via holes penetrating through the planarization layer PLN1, respectively.
  • At least one extended trace RL1 may be electrically connected to the TFT driving circuit, eg, to the source or drain of the thin film transistor, through the third trace RL4 located in the conductive layer CDL4.
  • the at least one extension wire RL1 may also be electrically connected to at least two of the chips CP1, CP2, CP3, and CP4. In this way, electrical connection between the TFT driver circuit and the chip, and electrical connection between multiple chips can be achieved.
  • the thin film transistors are top-gate thin film transistors, and it should be understood that the embodiments of the present disclosure are not limited thereto.
  • the thin film transistor can also be a bottom-gate thin film transistor, for example, a back-channel etched structure (ie, a BCE type TFT).
  • the gate material layer CDL1 may be prepared first, then the gate insulating layer GI1 may be formed, and then the active layer ACT may be formed.
  • the gate material layer CDL1 may include materials such as Mo/Al/Mo or Mo/Cu, and the thickness may be 3000-6000 angstroms.
  • the gate insulating layer GI1 may include silicon nitride or silicon oxide, and the thickness may be 2000 ⁇ 5000 angstroms.
  • the active layer ACT may include oxide semiconductor materials such as IGZO, IGTO, and IZO, and the thickness may be 300-1000 angstroms.
  • the chips with integrated functions are functionally split into multiple microchips.
  • some more chips can be installed in the front-end part to improve the ability to collect information, and these front-end miniature parts (such as the control part) can share the control chip, and through chip splitting and part of the function enhancement, there are It is beneficial to realize the optimization of sensor device function.
  • the demand for space detection technology for objects is also increasing.
  • objects need to be detected at multiple depths and multiple locations to achieve integration.
  • Smart display for multi-area space exploration For example, in the existing space detection technology, the outer module scheme is usually adopted. That is, the sensor used for space detection is usually placed in the middle of the upper frame of the display or on the desktop in front of the display. The application space is limited and there is a blind spot for identification.
  • the existing 2D display the person standing in the best recognition range can realize the manipulation of gestures.
  • 3D display the display image is distributed in multiple layers and positions, and the user's desired experience is to touch virtual objects at different positions. Therefore, the device solution for integrating sensors and display components for space detection has gradually become an important topic for developers. one.
  • an acoustic sensor is taken as an example to describe a device solution for integrating a sensor and a display element for spatial detection according to an embodiment of the present disclosure.
  • the functions of the acoustic sensor can be split to form multiple microchips.
  • the acoustic sensor may include at least a signal acquisition chip and a signal processing chip.
  • 28A and 28 are schematic block diagrams of acoustic sensors according to some embodiments of the present disclosure, respectively, and FIG. 28C schematically illustrates the arrangement of the acoustic sensors in a display according to some embodiments of the present disclosure. Referring to FIG. 28A and FIG. 28B , by functionally splitting the acoustic sensor, a plurality of microchips can be formed.
  • a plurality of signal collection chips SNC1 may be provided in one acoustic sensor, and the plurality of signal collection chips SNC1 may be electrically connected to at least one signal processing chip.
  • Multiple signal acquisition chips SNC1 can be connected in series to increase the signal-to-noise ratio of the collected signals, thereby increasing the signal detection sensitivity and realizing long-distance detection.
  • a signal processing chip may include an LC filter circuit, an amplifier circuit, a digital-to-analog conversion circuit, and a control circuit.
  • the LC filter circuit can filter the signals collected by the signal collection chip.
  • the amplifying circuit can amplify and rectify the filtered signal.
  • the digital-to-analog conversion circuit can perform digital-to-analog conversion on the amplified signal.
  • the control circuit may receive the digital-to-analog converted signal and perform a corresponding control function based on the signal.
  • the signal processing chip can also be functionally split, so that one signal processing chip can include multiple microchips. chips so that individual microchips can be flexibly arranged.
  • the acoustic sensor may include an LC filter chip SNP1, an amplifier chip SNP2, a digital-to-analog conversion chip SNP3, and a control chip SNP4.
  • multiple signal acquisition chips SNC1 can be connected in series with each other, and then electrically connected to the LC filter chip SNP1, the amplifier chip SNP2, the digital-to-analog conversion chip SNP3 and the control chip SNP4, and the multiple signal acquisition chips SNC1, LC filter chip SNP1, and amplifier chip SNP2 , the digital-to-analog conversion chip SNP3 and the control chip SNP4 can be arranged in a straight line, as shown in Figure 28A. In this way, the acoustic sensor SR1 with such an arrangement can be disposed at the middle position of the upper frame of the display.
  • a plurality of signal acquisition chips SNC1, LC filter chips SNP1, amplifier chips SNP2, digital-to-analog conversion chips SNP3, and control chips SNP4 can be arranged in a rectangle, as shown in FIG. 28B.
  • the acoustic sensor SR2 with such an arrangement can be arranged in the display area of the display.
  • the sensor may be placed in the display area of the display, or may be placed on the frame of the display.
  • the sensor since the sensor is split into a plurality of microchips, the sensor can be arranged flexibly, for example, the sensor can be arranged in a row, a circle, a serpentine, a rectangular area, a circular area, an oval area, etc.
  • the sensor a plurality of microchips can be densely arranged in the blank area, or a plurality of microchips can be placed in the gap between the pixels. That is to say, the sensors according to the embodiments of the present disclosure can be flexibly arranged on the display, which improves the device performance and installation flexibility, thereby solving the problems that the existing devices are limited in detection and can only be placed in an external module manner.
  • the senor may be a Si-based sensor.
  • the signal acquisition chip may include transducers for acquiring and converting acoustic signals into electrical signals.
  • 29 is a schematic cross-sectional view of a sensor-integrated display device, wherein the sensor is a Si-based sensor, according to some embodiments of the present disclosure.
  • the display device may include a substrate SUB5; a driving element disposed on the substrate SUB5; a planarization layer PLN1 disposed on the side of the drive element away from the substrate; disposed on the planarization layer PLN1 away from the substrate
  • the plurality of chips may be a signal acquisition chip SNC1, an LC filter chip SNP1, an amplifier chip SNP2, a digital-to
  • a plurality of extension wires RL1 may be located in the terminal extension layer RDL1.
  • Multiple signal acquisition chips SNC1 can be connected in series through multiple extended traces RL1, and multiple extended traces RL1 can also connect multiple signal acquisition chips SNC1, LC filter chip SNP1, amplifier chip SNP2, digital-to-analog conversion chip SNP3 and control The chips SNP4 are electrically connected in sequence.
  • the driving element may include the above-mentioned TFT driving circuit, and the specific film layer structure may refer to the above description, which will not be repeated here.
  • FIG. 30 schematically shows the relationship between the increase factor of the output voltage and the number of the transducers connected in series in the sensor according to the embodiment of the present disclosure.
  • the transducer and other signal processing circuits such as filter and amplifier are split, and multiple transducers are connected in series to increase the amount of received signals, as shown in FIG. 30 , and then through Filter and amplifier circuits.
  • the signal processing chip can be placed closely with the transducer, reducing RC load and noise, and increasing the signal detection sensitivity, thereby facilitating the realization of longer-distance detection.
  • the TFT backplane and the terminal extension layer are fabricated first, and then the chips are bonded.
  • embodiments of the present disclosure are not limited thereto, and individual chips may be bonded side by side/stack, chip face down or chip face up (ie face down/up), chip first or RDL first (ie die first/RDL first) ).
  • Types of the substrate SUB5 include, but are not limited to, glass substrates, PCBs, FPCs, and the like.
  • FIG. 31 is a schematic cross-sectional view of a sensor-integrated display device, wherein the sensor is a piezoelectric sensor including a piezoelectric thin film, according to some embodiments of the present disclosure.
  • the sensor is a piezoelectric sensor including a piezoelectric thin film, according to some embodiments of the present disclosure.
  • a plurality of piezoelectric sensing units are fabricated on a backplane including a TFT driving circuit, the plurality of piezoelectric sensing units are connected in series, and a signal processing chip is bonded.
  • piezoelectric film is used for description, and the embodiment of the present disclosure is not limited thereto.
  • the sensor chip included in the semiconductor device according to the embodiment of the present disclosure may include other type of sensor that can include other types of functional films. That is, herein, the expression “functional thin film” includes, but is not limited to, piezoelectric thin films.
  • the display device may include a substrate SUB5; a driving element arranged on the substrate SUB5; a planarization layer PLN1 arranged on a side of the driving element away from the substrate; The conductive layer CDL4 on the bottom side; the piezoelectric thin film PVL disposed on the side of the conductive layer CDL4 away from the substrate; and the conductive layer CDL5 disposed on the side of the piezoelectric thin film PVL away from the substrate.
  • the piezoelectric sensing unit includes a first electrode E1, a second electrode E2, and a piezoelectric thin film PVL sandwiched between the first electrode E1 and the second electrode E2.
  • the piezoelectric thin film PVL may be a PVDF piezoelectric thin film.
  • the plurality of first electrodes E1 are located in the conductive layer CDL4, and the plurality of second electrodes E2 are located in the conductive layer CDL5.
  • the first electrode E1 and the second electrode E2 of each piezoelectric sensing unit are arranged opposite and spaced apart.
  • FIG. 32 is a partial enlarged view of part III in FIG. 31 . 31 and 32, in two adjacent piezoelectric sensing units, the first electrode E1 of one piezoelectric sensing unit is connected to the second electrode of the other piezoelectric sensing unit through a via or groove. E2 electrical connection. In this way, a series connection of a plurality of piezoelectric sensing units can be achieved.
  • a conductive layer can be deposited first, and a plurality of first electrodes E1 can be formed through a patterning process; then, a PVDF piezoelectric film layer is spin-coated, and the PVDF piezoelectric film is cured and dry-etched film layer to form a patterned PVDF piezoelectric film; then, a conductive layer may be deposited to form a plurality of second electrodes E2 through a patterning process.
  • the thickness of the PVDF piezoelectric thin film layer is relatively thick, such as several micrometers, so a flat layer can be formed on the piezoelectric thin film layer, and then the second electrode E2 is formed.
  • the signal processing chip may include at least two terminals p1.
  • the terminal p1 may face downward, one terminal p1 may be electrically connected to the first electrode E1 of an adjacent piezoelectric sensing unit, and the other terminal p1 may be electrically connected to an extension trace located in the conductive layer CDL4.
  • FIGS. 33A to 33C are schematic cross-sectional views respectively illustrating a structure formed after some steps of a method for fabricating a display device integrated with a sensor are performed according to some embodiments of the present disclosure, wherein the sensor is a piezoelectric film including a piezoelectric film. electrical sensor.
  • a piezoelectric sensor can be fabricated separately, and then a plurality of piezoelectric sensing units can be formed by cutting.
  • a backplane including a TFT driving circuit can be fabricated separately.
  • the backplane includes a substrate SUB5; a driving element disposed on the substrate SUB5; Chemical layer PLN1.
  • the conductive layer CDL4 may be formed on the side of the planarization layer PLN1 away from the substrate.
  • a plurality of piezoelectric sensing units and chips are placed on the backplane.
  • at least two conductive parts are formed in the conductive layer CDL4, and the at least two conductive parts are arranged at intervals.
  • Two adjacent piezoelectric sensing units are placed on the same conductive part with opposite polarities.
  • the first electrode E1 of one piezoelectric sensing unit and the second electrode E2 of the other piezoelectric sensing unit are in electrical contact with the conductive layer CDL4.
  • a plurality of first wirings RL2 are formed in the redistribution layer RDL2.
  • the second electrode E2 of one piezoelectric sensing unit is electrically connected to the first electrode E1 of the other piezoelectric sensing unit through a first wire RL2 . In this way, a series connection of a plurality of piezoelectric sensing units can be achieved.
  • the signal processing chip may include at least two terminals p1.
  • the terminal p1 may face upward, one terminal p1 may be electrically connected to the second electrode E2 of an adjacent piezoelectric sensing unit through a first trace RL2, and the other terminal p1 may be connected to an extended trace located in the rewiring layer RDL2. electrical connection.
  • a plurality of piezoelectric sensing units may be disposed in a manner of stacking and bonding on top of each other.
  • a piezoelectric sensing unit is placed on the above-mentioned conductive part, its first electrode E1 is in contact with the conductive part, and its second electrode E2 faces upward; another piezoelectric sensing unit is prevented from being on the piezoelectric sensing unit, The first electrode E1 of the other piezoelectric sensing unit is in contact with the second electrode E2 of the above-mentioned piezoelectric sensing unit.
  • a series connection of a plurality of piezoelectric sensing units can also be achieved.
  • the possible production line incompatibility problem can be solved, and the formation of via holes in the piezoelectric thin film layer with a large thickness is avoided, the problem of odd-even polarization is solved, and the voltage is reduced. Process requirements for electrical thin films.
  • the driving circuit of the TFT driving element and each chip are arranged on the same substrate, and the chip first and chiplater processes are taken as examples for detailed description.
  • the embodiments of the present disclosure are not limited thereto, for example, driving circuits such as TFT driving elements and respective chips may be fabricated on different substrates, and then the semiconductor device may be formed in a box-to-box manner.
  • 35A to 35E are schematic cross-sectional views of structures formed after some steps of a method of fabricating a semiconductor device (eg, a display device) are performed according to exemplary embodiments of the present disclosure.
  • a semiconductor device eg, a display device
  • an adhesive layer AD1 is coated or adhered on the substrate SUB7.
  • each chip (eg, LED chip CP3 and functional element CP4 ) is transferred onto a substrate SUB7 by SMT or a mass transfer process, and fixed on the substrate by an adhesive layer AD1 .
  • each chip may be located on the adhesive layer AD1, and the terminal p1 of each chip may face upwards, ie, on the side of the chip away from the substrate.
  • a backplane Taking pictures of the substrate (which may be called a backplane) provided with the LED chip CP3 and the functional element CP4, and using image recognition technology to determine the terminals p1 of each LED chip CP3 and functional element CP4 provided on the backplane
  • the coordinates and area of are generated, and the graphics file of the terminal area (that is, the pad area) is generated.
  • a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by a digital direct writing or digital exposure machine according to the above-mentioned graphic file. Then, according to the patterned photoresist, the metal layer is etched to form the terminal extension layer RDL1.
  • a plurality of extension wires RL1 are formed in the terminal extension layer RDL1, and the plurality of extension wires RL1 can be respectively electrically connected to the terminals p1 of the LED chips CP3 and the functional elements CP4 to lead out the terminals p1. That is, through the post-alignment process, the extension wirings RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL1.
  • a planarization layer PLN1 is coated on the side of the terminal extension layer RDL1 away from the substrate.
  • the planarization layer PLN1 may include a resin-based material for filling the level difference between each LED chip CP3 and the functional element CP4 to achieve planarization.
  • a passivation layer PVX2 may be formed on the side of the planarization layer PLN1 away from the substrate.
  • the passivation layer PVX2 may include a material such as silicon nitride, which is used to isolate the water vapor in the planarization layer PLN1 and prevent the water vapor in the planarization layer PLN1 from corroding the upper terminal extension layer.
  • via holes may be formed through the planarization layer PLN1 and the passivation layer PVX2 to expose at least a portion of each extended trace RL1 .
  • a metal layer is deposited on the side of the passivation layer PVX2 away from the substrate, and a redistribution layer RDL2 is formed through a patterning process including steps of coating photoresist, exposing, developing, and etching.
  • a plurality of first wirings RL2 are formed in the redistribution layer RDL2.
  • the plurality of first wires RL2 can be electrically connected to the plurality of extension wires RL1 through the above-mentioned via holes, respectively, so as to further lead out the respective terminals p1.
  • the redistribution layer RDL3 may be prepared according to the requirements of line interconnection.
  • the capping layer PLN2 may be formed on the side of the redistribution layer RDL2 away from the substrate. Then, a redistribution layer RDL3 is formed on the side of the cap layer PLN2 away from the substrate.
  • the redistribution layer RDL3 may be prepared by a conventional photolithography process to form second wirings RL3 for electrically connecting the chips in the redistribution layer RDL3.
  • Embodiments of the present disclosure are not limited thereto, and the redistribution layer RDL3 may also be prepared through a post-alignment process.
  • the fourth-layer wiring, the fifth-layer wiring, etc. may also be prepared, which is not particularly limited in the embodiment of the present disclosure.
  • the backplane may include a substrate SUB8; a driving element disposed on the substrate SUB8; and a plurality of terminals p2 disposed on a side of the driving element away from the substrate.
  • the backplane and the substrate SUB7 on which the chips are disposed are assembled.
  • the plurality of terminals p2 on the backplane are respectively electrically connected to the plurality of second traces RL3 located in the redistribution layer RDL3, so as to realize the electrical connection between the driving element and the chip.
  • the chips can be arranged with a certain precision first, and then the positions, areas, and shapes of the chips and terminals (ie, pads) can be identified and analyzed through the post-alignment process, and the Combined with photolithography process, high-precision automatic wiring and chip bonding are realized.
  • the bonding precision of the microchip can be improved, which is beneficial to the integration of the chip and other circuits.
  • the requirement on the precision of the chip transfer process can be reduced, that is, it is beneficial to reduce the difficulty of the chip transfer process.
  • the automatic routing process can simultaneously perform high-precision bonding of a large number of chips transferred in a large area, which improves the bonding efficiency and is more suitable for large-scale and large-area chip bonding.
  • 36A schematically illustrates a top view of forming a plurality of extension traces during a post-alignment process in accordance with some embodiments of the present disclosure.
  • a partial top view of the display substrate is shown.
  • the plurality of pixels PX may include, but are not limited to, display pixels for implementing a display function, sensor pixels for implementing a detection function, and the like.
  • the display pixels include but are not limited to display elements such as OLED, microLED, miniLED, and LCD.
  • a plurality of chips CP are also disposed on the substrate SUB9.
  • a plurality of chips CP may be transferred onto the substrate SUB9 by SMT or a bulk transfer process.
  • a plurality of extension traces RL1 may be formed using the post-alignment process to electrically connect the plurality of chips CP.
  • the substrate which may be referred to as a backplane
  • image recognition technology is used to determine the coordinates, area and shape of the terminals p11 of each chip CP provided on the backplane and other parameters to generate the graphics file of the terminal area (ie the pad area).
  • FIG. 36A schematically shows the photographing area PTA corresponding to each chip CP.
  • the coordinates of the terminal p11 of each chip CP can be determined; and the area and shape of the terminal p11 of each chip CP can be determined by using image recognition technology.
  • bad judgment and detection can be made on the visual graphics on the backplane to identify the open-circuited connections on the backplane, and the metal extension wiring pairs of the post-alignment process can be used. Repair the bad points on the backplane, and screen the chips that cannot be connected due to excessive offset after transfer.
  • image recognition technology can be used to determine the coordinate information of each defective point.
  • a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by a digital direct writing or digital exposure machine according to the above-mentioned graphic file. Then, according to the patterned photoresist, the metal layer is etched to form the terminal extension layer RDL1.
  • a plurality of extension wires RL1 are formed in the terminal extension layer RDL1, and the plurality of extension wires RL1 can be electrically connected to the terminals p11 of the respective chips CP through via holes, so as to lead out the respective terminals p11. That is, through the post-alignment process, the extension wirings RL1 for electrically connecting the respective chips are formed in the terminal extension layer RDL1.
  • the software can determine the path of the automatic routing according to the coordinates of the terminal p11 of each chip CP and in combination with the actual transfer situation of the chips on each substrate. For example, in the process of determining the path of automatic wiring, it can be considered to avoid functional areas such as display pixels, so that the wiring paths are distributed in the gap area between the pixels, so as to electrically connect each chip.
  • the photoresist can be patterned by digital direct writing or digital exposure machine according to the coordinate information of each defective point. Then, according to the patterned photoresist, the metal layer is etched to form the terminal extension layer RDL1. A plurality of extension wires RL1 are formed in the terminal extension layer RDL1, and the plurality of extension wires RL1 can be electrically connected to respective defective points through via holes, so as to repair each defective point.
  • each chip on the backplane may be a densely packed chip on the entire screen, for example, a microLED chip in a display device.
  • the microscope takes a position calibration mark (MARK) of the entire backplane as the origin, takes pictures at a fixed step distance, and then translates to the next photographing area.
  • the actual number of pictures is related to the size of the backplane and the chip density.
  • One or more chips can be set in a photographing area.
  • the chips are not densely packed on the backplane, that is, the number of chips is small.
  • the photographing area may be an area surrounding the ideal position of the chip, and the coverage area of one photographing area may be larger than the possible offset range of the chip to ensure that the chip is in the photographing area.
  • a calibration mark (MARK) can be made on the backplane as the origin to determine the actual coordinates after the chip is transferred.
  • regularly arranged position calibration marks (MARK1) can be made on the backplane, and the position between the position calibration mark (MARK1) in each single image and the overall absolute coordinate calibration mark (MARK0) of the backplane It is relatively fixed and is used to convert the chip position in the single image of each photograph into absolute position coordinates relative to the entire backplane.
  • each single image has a position calibration mark (MARK1), there is no need to do image stitching when performing image recognition on the chip coordinates. It is only necessary to calculate the position of the chip in a single image relative to the position calibration in a single image after image recognition.
  • MARK1 position calibration mark
  • the coordinates of the mark (MARK1) are converted by the positional relationship between the position calibration mark (MARK1) in the single picture and the overall absolute coordinate calibration mark (MARK0) of the backplane to obtain the absolute position of the chip in the single picture relative to the overall backplane.
  • the absolute coordinates of the coordinate mark (MARK0) are converted by the positional relationship between the position calibration mark (MARK1) in the single picture and the overall absolute coordinate calibration mark (MARK0) of the backplane to obtain the absolute position of the chip in the single picture relative to the overall backplane.
  • 36B and 36C respectively schematically illustrate top views of forming a plurality of extension traces during a post-alignment process according to some embodiments of the present disclosure.
  • 37A and 37B are cross-sectional views taken along line AA' in FIG. 36B .
  • FIG. 38 schematically shows a partial enlarged view of wiring between two chips.
  • a plurality of fixed connection parts 12 may be provided on the substrate SUB9.
  • at least two fixed connection parts 12 may be provided near the position where each chip CP is located.
  • the extended wiring for electrically connecting the two chips CP may at least include a first wiring segment RL11 for connecting the terminal p1 of one chip and a fixed connection part 12 adjacent to the chip, and for connecting two fixed connections between the two chips.
  • the second wire segment RL12 of the connection part 12 and the third wire segment RL13 of a fixed connection part 12 for connecting the terminal p1 of another chip to the adjacent one of the other chip.
  • first line segment the second line segment, and the third line segment
  • first line segment and the third line segment are used.
  • first line segment and the third line segment The line segments are all used to electrically connect one terminal of the chip and the fixed connection part, so they can all be called the first line segment; the second line segment is used to electrically connect the two fixed connection parts. That is to say, in this article, expressions such as the first line segment and the second line segment can also be used to distinguish different parts of an extended line.
  • each chip CP may have a mark that can distinguish different pads according to pictures, and the actual coordinates of each chip are calculated and determined by identifying and analyzing the image after taking a photo.
  • the marks on the chip may include, but are not limited to, features such as the topography, shape, size, orientation, and the like of the pad on the chip.
  • special features can be made to differentiate pads from different chips.
  • the above-mentioned second line segment RL12 can be fabricated on the backplane using a conventional photolithography process, and the above-mentioned post-alignment process only forms the first line segment RL11 and the third line segment RL13.
  • the first routing segment RL11 and the third routing segment RL13 may be located in the terminal extension layer RDL1
  • the second routing segment RL12 may be located in a different layer from the terminal expansion layer RDL1.
  • the first line segment RL11 , the second line segment RL12 and the third line segment RL13 described above can all be formed through a post-alignment process.
  • the above-mentioned first wiring segment RL11 , second wiring segment RL12 and third wiring segment RL13 may be located in the terminal extension layer RDL1 . That is, the first line segment RL11 , the second line segment RL12 and the third line segment RL13 may be extended lines of the same layer of metal.
  • the distance between the fixed connection 12 and the center of the ideal transfer location of the chip may be greater than the maximum offset that can occur during chip transfer.
  • the maximum offset that can occur during chip transfer is about 10 microns
  • the distance between the fixed connection 12 and the center of the ideal transfer position of the chip is greater than 10 microns.
  • the path of the wiring between the fixed connection parts 12 is relatively fixed.
  • the path of the wiring between the fixed connection parts 12 can be set to be the same, that is, the path of the second wiring segment RL12
  • the routing paths are the same. In this way, when calculating and determining the routing path, there is no need to calculate the routing path of each second routing segment RL12, so that the complexity of automatic routing can be reduced.
  • the wiring path between the terminals of each chip and the fixed connection part can be accurately calculated according to the actual position of each chip after the transfer. Accuracy and efficiency of wiring.
  • At least one second routing segment RL12 extends in the first direction or the second direction; and in the extended routing including the second routing segment extending in the first or second direction Among the two chips that are electrically connected, the relative position of one chip in the first direction is different from the relative position of the other chip in the first direction.
  • At least one chip is inclined with respect to the extension line of the second wire segment RL12.
  • the 4 chips shown in Figure 36C are two chips that are electrically connected by an extension wire including at least one second wire segment.
  • the orientation of one chip relative to the extension line of the second line segment RL12 is the same as that of the other chip relative to the second line segment RL12.
  • the orientations of the extension lines of the line segment RL12 are not the same.
  • each chip in two chips electrically connected by extended traces including at least one second trace segment, each chip includes a plurality of terminals including at least a first terminal (eg, the left side of the chip shown in FIG. 36B, FIG. 36C ). side terminals) and second terminals (eg, the right side terminals of the chip shown in Figures 36B, 36C).
  • the second trace segment RL12 included in the extended trace for electrically connecting the first terminals of the two chips and the second trace segment RL12 included in the extended trace for electrically connecting the second terminals of the two chips are parallel to each other, and/ Or, the length of the second line segment RL12 included in the extension line for electrically connecting the first terminals of the two chips and the second line segment RL12 included in the extension line for electrically connecting the second terminals of the two chips is substantially equal.
  • the included angle is greater than 0° and less than 180°.
  • the included angle is different from the included angle between another first wiring segment RL13 and the second wiring segment RL12 adjacent to and electrically connected to it.
  • the clip between one first trace segment RL11 and the second trace segment RL12 adjacent to it and electrically connected The angle is different from the included angle between another first wiring segment RL11 and the second wiring segment RL12 adjacent to and electrically connected to it.
  • the second line segment RL12 between the fixed connection parts 12 can be set as a bus shared by different products according to the common characteristics of the products, such as the deviation of the transfer accuracy or the chip connection method;
  • the circuit is electrically connected to make it act as an intelligent bus with gating function.
  • the actual position of each chip may be different under the influence of the precision of the transfer process. Since the fixed connection parts 12 are provided, the paths of the second wire segments RL12 between the fixed connection parts 12 can be the same. When calculating the actual routing path, it is only necessary to layout and update the paths of the first routing segment RL11 and the third routing segment RL13.
  • the semiconductor device may be a display device.
  • the driving elements of the display device may be provided in the form of driving chips.
  • FIGS. 40A to 40C respectively schematically illustrate the arrangement of a driving chip and each pixel of a display device according to an embodiment of the present disclosure.
  • a driving chip CP1 serving as a driving element may be electrically connected to a portion corresponding to a pixel, so that the driving chip CP1 can drive a plurality of pixels PX. That is, in the embodiments of the present disclosure, there is no need to provide a driving circuit on the backplane.
  • the plurality of pixels PX may include, but are not limited to, display pixels for implementing a display function, sensor pixels for implementing a detection function, and the like.
  • the display pixels include but are not limited to display elements such as OLED, microLED, miniLED, and LCD.
  • one chip CP may include at least 2 terminals p1, eg, 4 terminals p1. At least 2 pixels PX, for example, 4 pixels PX may be arranged around one chip CP.
  • the four terminals p1 of one chip CP are respectively electrically connected with the four surrounding pixels PX through the extended wiring RL7.
  • the pixel PX is a display pixel
  • one terminal p1 of a chip CP is electrically connected to the anode of the display pixel through the extension line RL7, and the chip CP can supply a driving signal to the display pixel.
  • a terminal p1 of a chip CP is electrically connected to an electrode of the sensor pixel through an extension line RL7, and the chip CP can receive a sensing signal from the sensor pixel and perform certain processing (such as filtering ,enlarge).
  • a plurality of chips CP can be electrically connected to the master control chip CP10 through the extension line RL8.
  • the chip CP can be a driver chip; corresponding to a sensor pixel, the chip CP can be a power amplifier chip, and the general control chip CP10 can be an ADC chip.
  • the extension wire RL7 and the extension wire RL8 may be located in the same terminal extension layer, or the extension wire RL7 and the extension wire RL8 may be located in different terminal extension layers.
  • the extended trace RL7 and the extended trace RL8 may be formed through the above-described post-alignment process.
  • each extended trace RL7 and RL8 can be determined according to the spacing between chips. If the distance between the chips is relatively short, for example, the distance is a distance of a size of a plurality of pixels, the route may be directly extended according to the actual coordinates of the chips. If the distance between the chips is long and the connection paths are complicated, the combination of the fixed extended wiring and the flexible extended wiring proposed in the above-mentioned embodiment may be adopted.
  • the extended wiring RL8 between chips may adopt a fixed extended wiring manner
  • the extended wiring RL7 between the chips and the pixels may adopt a flexible extended wiring manner.
  • one master control chip CP10 and multiple chips CP may form a chip group, and one or more such chip groups may be arranged on the backplane.
  • the correspondence between the number of chips CP with driving circuits and pixels PX can be determined according to the PPI of the display device and the extended wiring space that can be provided.
  • the chips CP can be in one-to-one correspondence with the pixels PX, or Make one chip CP correspond to all pixels PX on the backplane.
  • the pixels PX on the backplane may be different types of pixels, for example, the pixels PX may include red sub-pixels (ie R sub-pixels), green sub-images (ie G sub-pixels) and blue sub-pixels pixel (ie B sub-pixel).
  • the pixels PX may include red sub-pixels (ie R sub-pixels), green sub-images (ie G sub-pixels) and blue sub-pixels pixel (ie B sub-pixel).
  • one chip CP may have 6 terminals p1 (ie, 6 interfaces). The six terminals p1 are respectively electrically connected to the R/G/B sub-pixels of the two pixels through the extension line RL7.
  • both the display pixels and the sensor pixels may be provided on the backplane.
  • one chip CP may have interfaces (ie, terminals) with different functions, such as a driver interface and a power amplifier interface.
  • the position of the chip pad is determined after image recognition, and the chip CP and each pixel PX are correctly connected.
  • the display pixels PX may be electrically connected to the terminal p11 of the chip CP, and the sensor pixels PX may be electrically connected to the terminal p12 of the chip CP.
  • the display device may include a light emitting element.
  • the light-emitting element may be a top-emitting light-emitting element, and the chip CP may be disposed below the light-emitting element; or, the light-emitting element may be a bottom-emitting light-emitting element, and the chip CP may be disposed above the light-emitting element.
  • Figure 41 schematically shows the projection relationship of chips and pixels. Referring to FIG. 41 , the orthographic projection of the chip CP on the substrate may partially overlap the orthographic projection of the plurality of pixels PX on the substrate. In this way, a display device with higher PPI can be realized.
  • a chip driving manner on a smaller scale can be implemented.
  • the master control chip can also be electrically connected to a higher-level control chip, so that separate control of each area can be realized.
  • the display device may include a gate chip CP12 disposed on the backplane.
  • the gate chip CP12 may include a gate TFT or a gate-level circuit.
  • 42 is a schematic diagram of a gate TFT of a gate chip according to an embodiment of the present disclosure.
  • 43 is a partial plan view of a display device including a gate chip according to an embodiment of the present disclosure.
  • 44A and 44B are respectively circuit connection diagrams of a display device including a gate chip according to an embodiment of the present disclosure.
  • the display device may include a gate chip CP12, a chip CP and a master control chip CP10.
  • One of the gate chips CP12 may include at least 2 ports (eg, 4 ports MUX1/MUX2/MUX3/MUX4), and one of the chips CP may include at least 2 terminals p1 (eg, 4 terminals p1).
  • a plurality of pixels PX located in the same row may be electrically connected through a row signal connection line L1, and a plurality of pixels PX located in the same column may be electrically connected through a column signal connection line L2.
  • a plurality of ports MUX1 ⁇ MUX4 of a gate chip CP12 can be electrically connected to a plurality of row signal connection lines L1 respectively through the extension wiring RL13 .
  • One terminal p1 of one chip CP may be electrically connected to a plurality of pixels in the same column through a plurality of gate TFTs, respectively.
  • the gate chip CP12 and the plurality of chips CP can also be electrically connected to the master control chip CP10 through the extension line RL14.
  • a plurality of strobe chips, at least one master control chip and a plurality of chips can form a chip group, and a plurality of such chip groups can be arranged on the backplane.
  • the pixels of a certain row can be controlled to be turned on.
  • the corresponding chip CP can be controlled to send driving signals to the pixels of a certain column. In this way, under the control of the strobe signal, the partitioned display and individual control of the pixels on the backplane can be realized.
  • the pixels PX may include, but are not limited to, display pixels for implementing a display function, sensor pixels for implementing a detection function, and the like.
  • the display pixels include but are not limited to display elements such as OLED, microLED, miniLED, and LCD.
  • the chip CP can be a driver chip; corresponding to a sensor pixel, the chip CP can be a power amplifier chip, and the general control chip CP10 can be an ADC chip.
  • the terms “substantially,” “approximately,” “approximately,” and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to explain what would be recognized by one of ordinary skill in the art Inherent deviation of a measured or calculated value.
  • “About” or “approximately” as used herein includes the stated value and is intended to mean the Specific values, as determined by one of ordinary skill in the art, are within acceptable tolerances. For example, “about” can mean within one or more standard deviations, or within ⁇ 10% or ⁇ 5% of the stated value.

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Abstract

提供一种半导体装置及其制造方法。所述半导体装置包括：衬底；设置于所述衬底的芯片，所述芯片包括芯片主体和设置于所述芯片主体上的多个端子；设置于所述衬底的端子扩展层，所述端子扩展层包括导电材料，其中，所述端子扩展层和至少一个端子位于所述芯片主体的同一侧，所述半导体装置还包括位于所述端子扩展层中的多个扩展走线，所述多个扩展走线分别与所述多个端子电连接，用于引出所述多个端子；以及至少一个扩展走线在所述衬底上的正投影完全覆盖与该扩展走线电连接的端子在所述衬底上的正投影。

Description

半导体装置及其制造方法
相关申请的交叉引用
本申请要求于2021年3月12日递交中国专利局的、申请号为202110273811.9，2021年3月12日递交中国专利局的、申请号为202110273812.3，以及2021年3月12日递交中国专利局的、申请号为202110273788.3的中国专利申请的权益，这些申请的全部公开内容以引用方式并入本文。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种半导体装置及其制造方法。
背景技术
在目前的例如显示装置的半导体装置中，通常需要采用多种不同的集成电路(缩写为IC)，包括但不限于，驱动IC，触控IC以及ROIC等，这些芯片通过COF或COG等不同的方式与显示背板进行连接，这种传统的方式难以实现显示像素单元与不同芯片之间的有机结合，同时也占据了显示背板外的额外空间，难以实现系统的微型化与集成化。另外，受限于PCB及FPC工艺的低精度以及后续的键合工艺精度，封装后的芯片引脚的Pad的尺寸会比较大，从而降低了芯片微型化的可行性。
在本部分中公开的以上信息仅用于对本公开的发明构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
为了解决上述问题的至少一个方面，本公开实施例提供一种半导体装置及其制造方法。
在一个方面，提供一种半导体装置，所述半导体装置包括：衬底；设置于所述衬底的芯片，所述芯片包括芯片主体和设置于所述芯片主体上的多个端子；设置于所述衬底的端子扩展层，所述端子扩展层包括导电材料，其中，所述端子扩展层和至少一个端子位于所述芯片主体的同一侧，所述半导体装置还包括位于所述端子扩展层中的 多个扩展走线，所述多个扩展走线分别与所述多个端子电连接，用于引出所述多个端子；以及至少一个扩展走线在所述衬底上的正投影完全覆盖与该扩展走线电连接的端子在所述衬底上的正投影。
根据一些示例性的实施例，所述半导体装置还包括粘性层，所述粘性层设置在所述衬底与所述芯片主体之间，用于将所述芯片固定于所述衬底上；以及所述芯片主体包括第一表面，所述第一表面面向或接触所述粘性层，至少一个端子设置在所述芯片主体除该第一表面之外的表面上。
根据一些示例性的实施例，所述衬底包括第一衬底表面，所述芯片设置在该第一衬底表面上，所述第一衬底表面包括第一衬底边缘；以及至少一个扩展走线在所述衬底上的正投影相对于所述第一衬底边缘倾斜。
根据一些示例性的实施例，所述芯片主体具有远离所述衬底的第二表面，所述第二表面在所述衬底上的正投影具有规则形状，所述第二表面所述衬底上的正投影包括第一边缘；以及所述第一边缘相对于所述第一衬底边缘倾斜。
根据一些示例性的实施例，所述至少一个扩展走线在所述衬底上的正投影的延长线与所述第一衬底边缘的延长线之间形成第一夹角，所述第一夹角大于0°小于90°；和/或，所述第一边缘的延长线与所述第一衬底边缘的延长线之间形成第二夹角，所述第二夹角大于0°小于90°。
根据一些示例性的实施例，所述衬底包括第一衬底表面，所述芯片设置在该第一衬底表面上；所述芯片的芯片主体包括第二表面、第一侧表面和第二侧表面，所述第二表面和所述第一表面分别位于所述芯片主体的相对侧，所述第一侧表面和所述第二侧表面分别位于所述芯片主体的侧表面，所述第一侧表面和所述第二侧表面中的每一个均连接所述第一表面与所述第二表面；以及所述第一侧表面和所述第二侧表面中的至少一个相对于所述第一衬底表面倾斜。
根据一些示例性的实施例，至少一个扩展走线与至少一个端子直接接触，并且所述至少一个扩展走线的一部分与所述第一侧表面和所述第二侧表面中的一个直接接触。
根据一些示例性的实施例，所述半导体装置还包括设置于所述芯片的一侧且覆盖所述端子的第一平坦化层；以及所述端子扩展层位于所述第一平坦化层远离所述芯片 的一侧，所述扩展走线的一端通过贯穿所述第一平坦化层的过孔或凹槽与所述端子电连接。
根据一些示例性的实施例，所述半导体装置还包括衬垫，所述衬垫位于所述芯片主体靠近所述衬底的一侧，所述衬垫在所述衬底上的正投影与所述芯片主体在所述衬底上的正投影至少部分重叠。
根据一些示例性的实施例，所述半导体装置还包括设置于所述芯片的一侧且覆盖所述端子的第一平坦化层和设置于所述第一平坦化层远离所述衬底一侧的第二平坦化层；所述半导体装置还包括第一走线，所述第一走线位于重布线层中；以及所述重布线层位于所述第二平坦化层远离所述芯片的一侧，所述第一走线的一端通过贯穿所述第一平坦化层和所述第二平坦化层两者的过孔或凹槽与所述扩展走线电连接。
根据一些示例性的实施例，所述半导体装置还包括功能器件，所述功能器件与所述芯片的至少一个端子电连接；以及所述功能器件与所述芯片位于不同的层。
根据一些示例性的实施例，所述半导体装置包括多个重复单元，多个重复单元沿第一方向和第二方向成阵列地布置在所述衬底上；每个重复单元包括多个所述芯片，位于每个重复单元内的多个芯片沿第一方向和第二方向成阵列地布置在所述衬底上，或者，位于每个重复单元内的多个芯片中的至少一部分沿第一方向和第二方向成阵列地布置在所述衬底上；以及在所述多个重复单元中的至少两个中，一个重复单元中的至少一个芯片在该重复单元中的相对位置与另一个重复单元中的对应芯片在该另一个重复单元中的相对位置不相同；和/或，在所述多个重复单元中的至少两个中，一个重复单元中的至少一个芯片在该重复单元中的朝向与另一个重复单元中的对应芯片在该另一个重复单元中的朝向不相同。
根据一些示例性的实施例，在所述多个重复单元中的至少两个中，用于引出一个重复单元中的至少一个芯片的至少一个端子的扩展走线的长度与用于引出另一个重复单元中的对应芯片的对应端子的扩展走线的长度不相等；和/或，在所述多个重复单元中的至少两个中，用于引出一个重复单元中的至少一个芯片的至少一个端子的扩展走线的延伸方向与用于引出另一个重复单元中的对应芯片的对应端子的扩展走线的延伸方向不相同。
根据一些示例性的实施例，对于位于沿所述第一方向或所述第二方向的同一排的两个芯片，每一个芯片的芯片主体具有远离所述衬底的第二表面，所述第二表面在所 述衬底上的正投影具有规则形状，所述两个芯片的芯片主体的第二表面在所述衬底上的正投影的几何中心之间的连线与所述第一方向或所述第二方向之间形成第三夹角，所述第三夹角大于0°小于90°。
根据一些示例性的实施例，所述芯片包括的多个端子均位于该芯片的芯片主体的第二表面上；或者，所述芯片包括的多个端子分别位于该芯片的芯片主体的第一侧表面和第二侧表面上；或者，所述芯片包括的多个端子分别位于该芯片的芯片主体的第一表面和第二表面上。
根据一些示例性的实施例，其特征在于，所述芯片包括第一芯片和第二芯片，所述第一芯片包括至少两个第一端子，所述第二芯片包括至少两个第二端子；其中，所述第一芯片和所述第二芯片被配置为实现不同的功能，所述第一芯片包括发光芯片和传感芯片中的至少一种，所述第二芯片包括传感芯片和控制芯片中的至少一种；以及所述至少一个扩展走线的一端与所述第一芯片电连接，所述至少一个扩展走线的另一端与所述第二端子电连接。
根据一些示例性的实施例，所述第一芯片包括发光芯片，所述第一芯片和所述第二芯片布置在同一层。
根据一些示例性的实施例，所述第一芯片包括发光芯片，所述第一芯片和所述第二芯片布置在不同的层；以及所述半导体装置还包括驱动元件，所述驱动元件和所述第一芯片通过至少一个扩展走线电连接。
根据一些示例性的实施例，所述驱动元件为驱动芯片，所述驱动芯片在所述衬底上的正投影与所述第一芯片在所述衬底上的正投影至少部分重叠；以及所述第一芯片包括主发光面，所述主发光面位于所述第一芯片远离所述驱动芯片的一侧。
根据一些示例性的实施例，所述驱动元件为驱动芯片，所述驱动芯片在所述衬底上的正投影与所述第一芯片在所述衬底上的正投影不重叠；以及所述第一芯片包括主发光面，所述主发光面位于所述第一芯片靠近所述驱动芯片的一侧。
根据一些示例性的实施例，所述半导体装置还包括保护层，所述保护层位于所述第一芯片远离所述第二芯片的一侧，所述保护层覆盖所述至少一个端子扩展层，且暴露所述第一芯片的出光面。
根据一些示例性的实施例，所述驱动元件包括用于驱动所述第一芯片的驱动电路，所述驱动电路至少包括薄膜晶体管，所述薄膜晶体管位于与所述第一芯片和所述第二 芯片不同的层；以及所述薄膜晶体管至少包括源极和漏极，所述源极或所述漏极通过过孔或凹槽与至少一个扩展走线电连接。
根据一些示例性的实施例，所述第一芯片和所述第二芯片布置于不同的层；以及所述薄膜晶体管位于所述第一芯片远离所述衬底的一侧，所述第二芯片位于所述薄膜晶体管远离所述衬底的一侧。
根据一些示例性的实施例，所述芯片还包括第三芯片，所述第一芯片、所述第二芯片和所述第三芯片被配置为彼此实现不同的功能；所述半导体装置包括至少一个芯片组，每个芯片组包括至少一个第二芯片和至少一个第三芯片；以及多个芯片组以一一对应的方式与多个第一芯片电连接；或者，一个芯片组与多个第一芯片电连接。
根据一些示例性的实施例，所述第一芯片包括传感芯片，多个传感芯片串联连接；以及所述第二芯片包括控制芯片。
根据一些示例性的实施例，所述传感芯片包括换能器芯片和压电传感芯片中的至少一种。
根据一些示例性的实施例，每一个所述传感芯片包括第一电极、第二电极和夹设在所述第一电极与所述第二电极之间的功能薄膜；多个传感芯片的第一电极位于同一层，多个传感芯片的第二电极位于同一层；以及在相邻的两个传感芯片中，一个传感芯片的第一电极通过过孔或凹槽与另一个传感芯片的第二电极电连接。
根据一些示例性的实施例，每一个所述传感芯片包括第一电极、第二电极和夹设在所述第一电极与所述第二电极之间的功能薄膜；所述半导体装置包括多个传感芯片组和多个导电部，每一个传感芯片组包括至少两个传感芯片；多个传感芯片组分别设置在多个导电部上，多个导电部间隔设置；以及在一个传感芯片组中，任意两个相邻的传感芯片中的一个传感芯片的第一电极和另一个传感芯片的第二电极与同一个导电部接触。
根据一些示例性的实施例，所述半导体装置还包括覆盖所述多个传感芯片的第二平坦化层和设置在所述第二平坦化层远离所述衬底一侧的第二端子扩展层，所述第二端子扩展层包括多个第二扩展走线；以及在两个相邻的传感芯片组中，一个传感芯片组的传感芯片的第一电极与另一个传感芯片组的传感芯片的第二电极通过至少一个第二扩展走线和贯穿所述第二平坦化层的过孔或凹槽电连接。
根据一些示例性的实施例，每一个所述传感芯片包括第一电极、第二电极和夹设在所述第一电极与所述第二电极之间的功能薄膜；所述半导体装置包括多个传感芯片组和至少一个导电部，每一个传感芯片组包括至少两个传感芯片；至少两个传感芯片组设置在同一个导电部上；以及在一个传感芯片组中，至少两个传感芯片堆叠放置于导电部上，最靠近所述导电部的一个传感芯片的第一电极或第二电极与所述导电部接触，任意两个相邻的传感芯片中的一个传感芯片的第一电极和另一个传感芯片的第二电极接触。
根据一些示例性的实施例，所述至少一个芯片还包括控制芯片；所述控制芯片与所述多个传感芯片位于同一层；所述半导体装置还包括覆盖所述多个传感芯片和所述控制芯片的第二平坦化层和设置在所述第二平坦化层远离所述衬底一侧的第二端子扩展层，所述第二端子扩展层包括多个第二扩展走线；以及最靠近所述控制芯片的一个传感芯片的第一电极或第二电极与所述控制芯片的一个端子通过至少一个第二扩展走线和贯穿所述第二平坦化层的过孔或凹槽电连接。
根据一些示例性的实施例，所述半导体装置还包括：设置于所述衬底的多个像素，所述多个像素沿行方向和列方向成阵列地布置；选通芯片，所述选通芯片包括至少两个端口；多个行信号连接线，一个行信号连接线与位于同一行的多个像素电连接；多个列信号连接线，一个列信号连接线与位于同一列的多个像素电连接；以及选通晶体管，所述第一芯片通过所述选通晶体管与列信号连接线电连接，其中，所述多个行信号连接线分别通过第一扩展走线与所述选通芯片的多个端口电连接，多个第一芯片通过第二扩展走线与第二芯片电连接，所述第一扩展走线和所述第二扩展走线位于所述至少一个端子扩展层中。
根据一些示例性的实施例，提供一种显示装置，所述显示装置包括：衬底；设置于所述衬底的多个芯片，其中，每个第一芯片包括至少两个端子，所述芯片包括从发光二极管芯片、次毫米发光二极管芯片和微型发光二极管芯片中选择的至少一种；用于驱动所述芯片的驱动电路，所述驱动电路包括至少一个薄膜晶体管；和设置于所述衬底的至少一个端子扩展层，所述端子扩展层包括导电材料，其中，所述端子扩展层和至少一个端子位于所述芯片主体的同一侧，所述半导体装置还包括位于所述至少一个端子扩展层中的多个扩展走线，所述多个扩展走线分别与所述多个端子电连接，用于引出所述多个端子；至少一个扩展走线在所述衬底上的正投影覆盖与该扩展走线电 连接的端子在所述衬底上的正投影；以及所述至少一个扩展走线的一端与所述驱动电路的薄膜晶体管电连接。
在另一方面，提供一种半导体装置的制造方法，所述制造方法包括：
将芯片置于衬底上，其中，所述芯片包括芯片主体和设置于所述芯片主体上的多个端子；以及
通过后对准工艺在所述芯片远离所述衬底的一侧形成端子扩展层，其中，所述端子扩展层包括导电材料，
其中，所述通过后对准工艺在芯片远离所述衬底的一侧形成端子扩展层包括：
对设置有所述芯片的衬底进行拍照；
采用图像识别技术确定多个端子的坐标，生成端子的图形文件；
在所述芯片远离所述衬底的一侧形成导电材料层；以及
根据所述图形文件，通过光刻工艺刻蚀所述导电材料层，以在所述端子扩展层中形成多个扩展走线，
其中，所述多个扩展走线分别与所述多个端子电连接，用于引出所述多个端子；以及
至少一个扩展走线在所述衬底上的正投影完全覆盖与该扩展走线电连接的端子在所述衬底上的正投影。
根据一些示例性的实施例，所述对设置有所述芯片的衬底进行拍照包括：
对设置有所述芯片的衬底的第一拍照区域进行拍照；以及
以设置于所述衬底上的一个位置标定标记为原点，按固定的步进距离平移拍照设备，以对设置有所述芯片的衬底的第二拍照区域进行拍照，
其中，拍照的次数与所述芯片的分布密度相关，每一个拍照区域中设置有至少一个所述芯片。
根据一些示例性的实施例，所述将芯片置于衬底上包括：
在所述衬底上形成粘性层；以及
通过转移工工艺将芯片转移至所述粘性层上，使得所述芯片通过所述粘性层固定于所述衬底上。
根据一些示例性的实施例，所述制造方法还包括：
在所述通过后对准工艺在多个芯片远离所述衬底的一侧形成至少一个端子扩展层之后，在所述端子扩展层远离所述衬底的一侧形成驱动元件，
其中，所述驱动元件包括驱动芯片或具有薄膜晶体管的驱动电路。
根据一些示例性的实施例，所述制造方法还包括：
在将多个芯片置于衬底上之前，在所述衬底上形成驱动元件，
其中，所述驱动元件包括驱动芯片或具有薄膜晶体管的驱动电路。
根据一些示例性的实施例，所述通过后对准工艺在多个芯片远离所述衬底的一侧形成至少一个端子扩展层包括：
直接在所述芯片上形成第一端子扩展层，通过光刻工艺形成位于所述第一端子扩展层中的第一扩展走线，使得所述第一扩展走线的一端与所述第一端子接触，所述第一扩展走线的一部分与所述芯片的侧壁接触。
根据一些示例性的实施例，所述制造方法还包括：在所述芯片远离所述衬底的一侧形成第一平坦化层，所述第一平坦化层覆盖所述芯片的端子；以及
通过光刻工艺在所述第一平坦化层中形成多个过孔或凹槽，所述多个过孔或凹槽分别暴露所述芯片的端子的至少一部分，
其中，所述通过后对准工艺在所述芯片远离所述衬底的一侧形成端子扩展层包括：
在所述第一平坦化层远离所述衬底的一侧形成端子扩展层，通过后对准工艺形成位于所述端子扩展层中的扩展走线，使得所述扩展走线的一端通过所述过孔或凹槽与所述端子接触。
根据一些示例性的实施例，所述通过后对准工艺在芯片远离所述衬底的一侧形成端子扩展层包括：
通过所述后对准工艺形成端子扩展层；
在所述端子扩展层远离所述衬底的一侧形成第一平坦化层；
通过光刻工艺在所述第一平坦化层中形成多个过孔或凹槽，所述多个过孔或凹槽暴露所述端子扩展层的至少一部分；以及
在所述第一平坦化层远离所述衬底的一侧形成重布线层，
其中，所述制造方法还包括：
以所述端子扩展层为种子层，采用电化学方式镀金属层，以在所述多个过孔或凹槽中生长与所述第一平坦化层的厚度相等的导电连接部，其中，所述导电连接部用于电连接所述端子扩展层和所述重布线层。
根据一些示例性的实施例，所述制造方法还包括：
在所述后对准工艺中，采用图像识别技术确定不良点的坐标信息；以及
基于所述坐标信息并通过所述光刻工艺刻蚀所述导电材料层，以在所述端子扩展层中形成至少一个用于修复所述不良点的扩展走线。
在又一方面，提供一种半导体装置，所述半导体装置包括：衬底；设置于所述衬底的多个芯片，每个芯片包括芯片主体和设置于所述芯片主体上的多个端子；设置于所述衬底的多个固定连接部；设置于所述衬底的端子扩展层，所述端子扩展层包括导电材料，其中，所述多个固定连接部分别邻近所述多个芯片设置；所述半导体装置还包括位于所述端子扩展层中的多个扩展走线，所述扩展走线用于电连接所述多个芯片；以及用于电连接两个芯片的扩展走线至少包括第一走线段和第二走线段，所述第一走线段用于电连接一个芯片的端子与该芯片邻近的一个固定连接部，所述第二走线段用于连接两个芯片之间的两个固定连接部。
根据一些示例性的实施例，至少一个第二走线段沿第一方向延伸；以及在通过包括沿第一方向延伸的第二走线段的扩展走线电连接的两个芯片中，一个芯片在所述第一方向上的相对位置与另一个芯片在所述第一方向上的相对位置不相同。
根据一些示例性的实施例，在通过包括至少一个第二走线段的扩展走线电连接的两个芯片中，至少一个芯片相对于所述第二走线段的延长线倾斜。
根据一些示例性的实施例，在通过包括至少一个第二走线段的扩展走线电连接的两个芯片中，一个芯片相对于所述第二走线段的延长线的朝向与另一个芯片相对于所述第二走线段的延长线的朝向不相同。
根据一些示例性的实施例，在通过包括至少一个第二走线段的扩展走线电连接的两个芯片中，每一个芯片包括的多个端子至少包括第一端子和第二端子；用于电连接两个芯片的第一端子的扩展走线包括的第二走线段和用于电连接两个芯片的第二端子的扩展走线包括的第二走线段彼此平行，和/或，用于电连接两个芯片的第一端子的扩展走线包括的第二走线段和用于电连接两个芯片的第二端子的扩展走线包括的第二走线段的长度基本相等。
根据一些示例性的实施例，至少一个第一走线段和与它相邻且电连接的第二走线段之间具有夹角，所述夹角大于0°小于180°。
根据一些示例性的实施例，在与同一个第二走线段相邻且电连接的两个第一走线段中，一个第一走线段和与它相邻且电连接的第二走线段之间的夹角不同于另一个第一走线段和与它相邻且电连接的第二走线段之间的夹角。
根据一些示例性的实施例，在与同一个芯片的第一端子和第二端子电连接的两个第一走线段中，一个第一走线段和与它相邻且电连接的第二走线段之间的夹角不同于另一个第一走线段和与它相邻且电连接的第二走线段之间的夹角。
根据一些示例性的实施例，多个所述第一走线段位于同一层中；以及所述第二走线段与所述第一走线段位于相同或不同的层中。
根据一些示例性的实施例，提供一种显示装置，所述显示装置包括：衬底；设置于所述衬底的多个像素，所述多个像素沿第一方向和第二方向成阵列地布置；设置于所述衬底的多个芯片，每个芯片包括芯片主体和设置于所述芯片主体上的多个端子；设置于所述衬底的多个固定连接部；设置于所述衬底的至少一个端子扩展层，所述端子扩展层包括导电材料，其中，所述多个固定连接部分别邻近所述多个芯片设置；所述半导体装置还包括位于所述至少一个端子扩展层中的多个扩展走线，所述扩展走线用于电连接所述多个芯片；用于电连接两个芯片的扩展走线至少包括第一走线段和第二走线段，所述第一走线段用于电连接一个芯片的端子与该芯片邻近的一个固定连接部，所述第二走线段用于连接两个芯片之间的两个固定连接部；以及至少一个芯片相对于所述第一方向和所述第二方向倾斜。
根据一些示例性的实施例，所述多个芯片沿第一方向和第二方向成阵列地布置；以及至少一个第一走线段相对于所述第一方向和所述第二方向倾斜。
根据一些示例性的实施例，所述第二走线段沿所述第一方向或所述第二方向延伸。
在再一方面，提供一种半导体装置的制造方法，所述制造方法包括：
将多个芯片置于衬底上，其中，每个芯片包括芯片主体和设置于所述芯片主体上的多个端子；
在所述衬底上形成多个固定连接部；以及
通过后对准工艺在多个芯片远离所述衬底的一侧形成端子扩展层，其中，所述端子扩展层包括导电材料，
其中，所述通过后对准工艺在多个芯片远离所述衬底的一侧形成端子扩展层包括：
对设置有所述多个芯片和多个固定连接部的衬底进行拍照；
采用图像识别技术确定各个芯片的端子的坐标，以生成端子的图形文件；
在多个芯片远离所述衬底的一侧形成导电材料层；以及
根据所述图形文件，通过光刻工艺刻蚀所述导电材料层，以在所述端子扩展层中形成多个扩展走线，
其中，所述扩展走线用于电连接所述多个芯片，用于电连接两个芯片的扩展走线至少包括第一走线段和第二走线段，所述第一走线段用于电连接一个芯片的端子与该芯片邻近的一个固定连接部，所述第二走线段用于连接两个芯片之间的两个固定连接部。
根据一些示例性的实施例，所述生成端子的图形文件的步骤包括：
采用图像识别技术，确定各个芯片的端子的坐标；
读取各个固定连接部的预置坐标；以及
根据确定出的各个芯片的端子的坐标和读取的各个固定连接部的预置坐标，生成端子的图形文件。
根据一些示例性的实施例，所述对设置有所述多个芯片和多个固定连接部的衬底进行拍照包括：
对设置有所述多个芯片和多个固定连接部的衬底的第一拍照区域进行拍照；以及
以设置于所述衬底上的一个整体绝对坐标标定标记为原点，按固定的步进距离平移拍照设备，以对设置有所述多个芯片和多个固定连接部的衬底的第二拍照区域进行拍照，
其中，拍照的次数与所述芯片的分布密度相关，每一个拍照区域中设置有至少一个所述芯片。
根据一些示例性的实施例，至少两个拍照区域之间存在重叠的拍照区域。
根据一些示例性的实施例，所述制造方法还包括：
在所述衬底上形成整体绝对坐标标定标记和多个位置标定标记，
其中，所述多个位置标定标记分别与多个拍照区域一一对应。
在还再一方面，提供一种半导体装置，所述半导体装置包括：相对设置的第一衬底和第二衬底；设置于所述第一衬底的芯片，所述芯片包括芯片主体和设置于所述芯 片主体上的多个第一端子；设置于所述第一衬底的端子扩展层，所述端子扩展层包括导电材料；以及设置于所述第二衬底的多个第二端子，其中，所述端子扩展层和至少一个第一端子位于所述芯片主体的同一侧，所述半导体装置还包括位于所述端子扩展层中的多个扩展走线，所述多个扩展走线分别与所述多个第一端子电连接，用于引出所述多个第一端子；多个扩展走线在所述第一衬底上的正投影完全覆盖与该扩展走线电连接的第一端子在所述第一衬底上的正投影；以及所述多个第一端子分别通过所述多个扩展走线与所述多个第二端子电连接，所述多个第二端子在所述第一衬底上的正投影与所述多个扩展走线在所述第一衬底上的正投影至少部分重叠。
根据一些示例性的实施例，所述半导体装置还包括多个驱动元件，所述多个驱动元件设置于所述第二衬底上，所述多个第二端子位于所述多个驱动元件远离所述第二衬底的一侧，所述多个第二端子分别与所述多个驱动元件电连接。
根据一些示例性的实施例，所述芯片包括的多个第一端子均位于该芯片的芯片主体远离所述第一衬底的一侧；以及所述半导体装置还包括粘性层，所述粘性层设置在所述第一衬底与所述芯片主体之间，用于将所述至少一个芯片固定于所述第一衬底上。
根据一些示例性的实施例，所述芯片包括的多个第一端子分别位于该芯片的芯片主体沿平行于所述第一衬底的第一衬底表面的方向的两侧，其中，所述第一衬底的第一衬底表面为所述第一衬底设置所述芯片的表面；以及所述半导体装置还包括粘性层，所述粘性层设置在所述第一衬底与所述芯片主体之间，用于将所述芯片固定于所述第一衬底上。
根据一些示例性的实施例，所述芯片包括的多个第一端子分别位于该芯片的芯片主体沿垂直于所述第一衬底的第一衬底表面的方向的两侧，其中，所述第一衬底的第一衬底表面为所述第一衬底设置所述芯片的表面；以及所述半导体装置还包括粘性层和第一导电层，所述粘性层设置在所述第一衬底与所述芯片主体之间，所述第一导电层设置在所述粘性层与所述芯片之间之间，所述第一导电层与所述芯片的靠近所述第一衬底的至少一个第一端子电连接。
根据一些示例性的实施例，所述第一衬底包括第一衬底表面，所述芯片设置在该第一衬底表面上，所述第一衬底表面包括第一衬底边缘；以及至少一个扩展走线在所述第一衬底上的正投影相对于所述第一衬底边缘倾斜。
根据一些示例性的实施例，所述芯片主体具有远离所述第一衬底的第二表面，所述第二表面在所述第一衬底上的正投影具有规则形状，所述第二表面所述第一衬底上的正投影包括第一边缘；以及所述第一边缘相对于所述第一衬底边缘倾斜。
在还再一方面，提供一种半导体装置的制造方法，所述制造方法包括：
将芯片置于第一衬底上，其中，所述芯片包括芯片主体和设置于所述芯片主体上的多个第一端子；
通过后对准工艺在所述芯片远离所述第一衬底的一侧形成端子扩展层，其中，所述端子扩展层包括导电材料；
在第二衬底上形成多个第二端子；以及
对盒所述第一衬底和所述第二衬底，使得所述多个第一端子分别与多个第二端子电连接，
其中，所述通过后对准工艺在所述芯片远离所述第一衬底的一侧形成端子扩展层包括：
对设置有所述芯片的衬底进行拍照；
采用图像识别技术确定芯片的第一端子的坐标，以生成第一端子的图形文件；
在所述芯片远离所述第一衬底的一侧形成导电材料层；以及
根据所述图形文件，通过光刻工艺刻蚀所述导电材料层，以在所述端子扩展层中形成多个扩展走线，
其中，多个扩展走线在所述第一衬底上的正投影完全覆盖与该扩展走线电连接的第一端子在所述第一衬底上的正投影；以及
所述多个第一端子分别通过所述多个扩展走线与所述多个第二端子电连接，所述多个第二端子在所述第一衬底上的正投影与所述多个扩展走线在所述第一衬底上的正投影至少部分重叠。
根据一些示例性的实施例，所述将芯片置于第一衬底上包括：
在所述第一衬底上形成粘性层；以及
通过转移工工艺将所述芯片转移至所述粘性层上，使得所述芯片通过所述粘性层固定于所述第一衬底上。
附图说明
通过下文中参照附图对本公开所作的描述，本公开的其它目的和优点将显而易见，并可帮助对本公开有全面的理解。
图1示意性示出了根据本公开的一些示例性实施例的显示装置的方框图。
图2是示意性示出根据本公开实施例的显示基板中多个芯片的布置的示意图。
图3A至图3C分别是示意性示出根据本公开实施例的显示基板中功能单元组与显示区的相对位置关系的示意图。
图4是示意性示出本公开实施例的半导体装置(例如显示基板)中衬底上的端子(pad)与芯片上的端子(pad)之间的对位关系的示意图。
图5A至图5D是示意性示出根据本公开实施例的后对准工艺的一些步骤的示意图。
图6A和图6B分别是根据本公开实施例的微型芯片的截面示意图和俯视示意图。
图7A、图7B和图7C分别是根据本公开实施例的微型芯片和端子扩展层中的扩展走线的透视图和截面示意图。
图8A、图8B和图8C分别是根据本公开的一些实施例的微型芯片和端子扩展层中的扩展走线的截面示意图。
图9是示出根据本公开实施例的chip first工艺形成的结构的示意图。
图10是示出根据本公开实施例的chip later工艺形成的结构的示意图。
图11A和图11B分别是根据本公开的一些实施例的显示装置包括的芯片和显示单元的示例性布置的示意图。
图12A至图12F是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图。
图13A至图13G是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图。
图14是根据本公开的一些实施例的半导体装置(例如显示装置)的示意截面图，其中所述显示装置可以为大尺寸显示装置或拼接式显示装置。
图15是根据本公开的一些实施例的半导体装置(例如显示装置)的示意截面图，其示意性示出了朝上发光的实施方式。
图16是根据本公开的一些实施例的半导体装置(例如显示装置)的示意截面图。
图17A至图17I是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图。
图18示意性示出了根据本公开的一些实施例的半导体装置的示意截面图，其中芯片的端子位于芯片的两个相对侧面上。
图19A至图19H是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图，其中芯片的端子位于芯片的上、下表面上。
图20A至图20F是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图，其中所述显示装置的驱动元件包括TFT驱动电路，以及所述制造方法通过上述chip first工艺实现。
图21是图20E的部分I的局部当大图。
图22是根据本公开的一些实施例的显示装置的示意截面图，其中LED芯片和其他芯片位于不同的层中。
图23是图22中的部分II的局部放大图。
图24是根据本公开的一些实施例的显示装置的示意截面图，其中LED芯片和其他芯片位于不同的层中。
图25A至图25F是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图，其中所述显示装置的驱动元件包括TFT驱动电路，以及所述制造方法通过上述chip later工艺实现。
图26A和图26B分别示意性示出了根据本公开实施例的显示装置的过孔的示意截面图。
图27是根据本公开的一些实施例的显示装置的示意截面图，其中薄膜晶体管为底栅型薄膜晶体管。
图28A和图28B分别是根据本公开的一些实施例的声学传感器的示意方框图。
图28C示意性示出了根据本公开的一些实施例的声学传感器在显示器中的布置方式。
图29是根据本公开的一些实施例的集成有传感器的显示装置的示意截面图，其中所述传感器为Si基传感器。
图30示意性示出了在根据本公开的实施例的传感器中输出电压的增大倍数与串联的换能器的个数的关系。
图31是根据本公开的一些实施例的集成有传感器的显示装置的示意截面图，其中所述传感器为包含压电薄膜的压电传感器。
图32是图31中的部分III的局部放大图。
图33A至图33C是分别示意根据本公开的一些实施例的集成有传感器的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图，其中所述传感器为包含压电薄膜的压电传感器。
图34是根据本公开的一些实施例的集成有传感器的显示装置的示意截面图。
图35A至图35E是根据本公开的示例性实施例的半导体装置(例如显示装置)的制造方法的一些步骤被执行后形成的结构的示意截面图。
图36A示意性示出了在根据本公开的一些实施例的后对准工艺的过程中形成多个扩展走线的俯视图。
图36B和图36C分别示意性示出了在根据本公开的一些实施例的后对准工艺的过程中形成多个扩展走线的俯视图。
图37A和图37B是沿图36B中的线AA’截取的截面图。
图38示意性示出了两个芯片之间的布线的局部放大图。
图39A、图39B和图39C分别示意性示出了后对准工艺中形成的拍照区域。
图40A至图40C分别示意性示出了根据本公开实施例的显示装置的驱动芯片和各个像素的布置方式。
图41示意性示出了芯片和像素的投影关系。
图42是根据本公开实施例的选通芯片的选通TFT的原理图。
图43是根据本公开实施例的包括选通芯片的显示装置的局部平面图。
图44A和图44B分别是根据本公开实施例的包括选通芯片的显示装置的电路连接图。
需要注意的是，为了清晰起见，在用于描述本公开的实施例的附图中，层、结构或区域的尺寸可能被放大或缩小，即这些附图并非按照实际的比例绘制。
具体实施方式
在下面的描述中，出于解释的目的，阐述了许多具体细节以提供对各种示例性实施例的全面的理解。然而，明显的是，在不具有这些具体细节或者具有一个或多个等 同布置的情况下，可以实施各种示例性实施例。在其它情况下，以框图形式示出了公知的结构和装置，以避免使各种示例性实施例不必要地模糊。此外，各种示例性实施例可以是不同的，但不必是排他的。例如，在不脱离发明构思的情况下，可以在另一示例性实施例中使用或实施示例性实施例的具体形状、配置和特性。
在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。当可以不同地实施示例性实施例时，可以与描述的顺序不同地执行具体的工艺顺序。例如，可以基本上同时执行或者以与描述的顺序相反的顺序执行两个连续描述的工艺。此外，同样的附图标记表示同样的元件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在……之间”对“直接在……之间”、“相邻”对“直接相邻”或“在……上”对“直接在……上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。
应该理解的是，尽管在这里可使用术语第一、第二等来描述不同的元件，但是这些元件不应受这些术语的限制。这些术语仅是用来将一个元件与另一个元件区分开来。例如，在不脱离示例实施例的范围的情况下，第一元件可以被命名为第二元件，类似地，第二元件可以被命名为第一元件。
应该理解，集成电路(缩写为IC)是一种将电路(包括半导体装置、被动器件等)小型化的方式，例如，制造在半导体晶圆表面上的器件。例如，集成电路也可以称为微电路(microcircuit)、晶片、芯片(chip)等。通常情况下，集成电路是以大批方式，经光刻等多个步骤，制作在大片的半导体晶圆上，然后再分割成若干小片。这一小片就称为芯片，每个芯片就是一个集成电路的集合。晶圆所用的半导体材料通常是电子级的硅或其他半导体(例如砷化镓)的单晶。
应该理解，裸晶(英文表述为die，也称为裸芯片、裸芯片、晶粒或裸片)是以半 导体材料制作而成未经封装的一小块集成电路，该集成电路的既定功能就是在这一小片半导体上实现的。
应该理解，在集成电路领域中，封装是将集成电路装配为芯片最终产品的过程，例如，将集成电路裸片放在一块起到承载作用的基板上，把管脚引出来，然后固定包装成为一个整体。具体地，把集成电路裸片上的电路管脚，用导线接引到外部接头处，以便于其它器件连接。封装结构不仅起着安装、固定、密封、保护芯片及增强电热性能等方面的作用，而且还通过芯片上的接点用导线连接到封装结构的引脚上，这些引脚又通过印刷电路板上的导线与其他器件相连接，从而实现内部芯片与外部电路的连接。
在本文中，面板级封装技术是指将半导体裸晶黏于载具上，在裸晶的端点上拉出所需的电路到重分布层(简称为RDL)，进而形成封装，不需要封装载板，更不用打线以及凸块(英文表述为Bump)，进而得以降低生产成本。
在本文中，数字化曝光工艺指的是一种直写或是无掩模(maskless)的光刻工艺，通常可以采用数字曝光机实施。例如，可以采用数字化曝光工艺(即不使用掩模)在基板上形成电连接芯片的端子的布线层。具体地，可以通过低精度的转移工艺将多个芯片转移至基板上；芯片的各个端子在基板上的位置可以通过Mapping读取，或通过光学检测获取芯片图片，再通过算法获得各个端子的位置；获得各个端子的位置后，将各个端子的坐标信息形成数字曝光机可以识别的文件，数字曝光机可以根据该文件对导电层实施曝光工艺，以形成电连接芯片的端子的布线层。在上述过程中，数字化曝光工艺可以自动被校正各个芯片转移至基板上的位置偏移，例如，数字化曝光工艺的精度可以达到＜1μm，因此，可以大大降低键合所带来的工艺难度，提升工艺精度。
在本文中，表述“端子”表示芯片与外部引线、走线、电极等电连接的部分，包括但不限于，芯片的pad。
在本文中，“后对准工艺”表示一种用于对准芯片的端子(例如pad)的工艺。例如，在本公开的实施例中，可以先将多个芯片通过SMT或巨量转移等工艺转移至衬底上，然后通过图像分析技术确定转移至衬底上的各个芯片的pad的位置(例如各个pad的坐标信息)、面积和形貌等参数，基于所述参数并通过例如光刻工艺等高精度的构图工艺，形成电连接至各个芯片的pad的扩展走线或引线，以实现各个芯片的键合。应该理解，由于后对准工艺包括光刻工艺等高精度的构图工艺，所以其精度会高于巨量 转移工艺的精度。例如，光刻机形成的金属扩展走线的偏移精度一般小于0.6微米，而目前的巨量转移设备的精度为5-10微米左右，在本公开的实施例中，通过所述后对准工艺，可以解决微型芯片巨量转移时发生的转移精度不高的问题。
另外，在本文中，“后对准工艺”除了识别芯片的端子进行自动布线之外，还可以用于修复不良点。例如，在后对准工艺中，可以识别获得不良点，获得不良点的坐标信息；然后基于所述坐标信息并通过例如光刻工艺等高精度的构图工艺，形成电连接至各个不良点的的扩展走线或引线，以修复各个不良点。
需要说明的是，在本文中，表述“不良点”包括在其电连接路径中存在断路的端子。
在本文中，除非另有特别说明，表述“位置”、“相对位置”表示例如芯片、芯片主体等部件在空间坐标系中的位置，例如，在XYZ坐标系中，可以用X、Y、Z轴的坐标值表示。表述“朝向”表示芯片、芯片主体等部件在空间坐标系中相对于各个坐标轴的角度，例如，在XYZ坐标系中，可以用相对于X、Y、Z轴的角度表示。
例如，无掩模光刻技术大概可以分为两类：(1)带电粒子无掩模光刻，例如电子束直写和离子束光刻技术等。(2)光学无掩模技术，例如DMD无掩模光刻技术、激光直写、干涉光刻技术、衍射光学元件光刻技术等。具体地，DMD无掩模光刻技术是从传统光学光刻技术衍生出的一种技术，其曝光成像的方式与传统投影光刻基本相似，区别在于使用数字DMD代替传统的掩模，主要原理是通过计算机将所需的光刻图案通过软件输入到DMD芯片中，并根据图像中的黑白像素的分布来改变DMD芯片微镜的转角，并通过准直光源照射到DMD芯片上形成与所需图形一致的光图像投射到基片表面，并通过控制样品台的移动实现大面积的微结构制备。电子束光刻(通常缩写为EBL)是一种利用电子束在抗蚀剂覆盖的表面上绘制自定义图案的技术。电子束改变了抗蚀剂的溶解性，通过将其浸入溶剂中(即显影)，可以选择性地除去抗蚀剂的已曝光或未曝光区域。
还应该理解，引线键合(Wire Bonding)是一种利用热、压力或超声波能量使金属键合引线与基板焊盘紧密焊合的工艺。例如，在IC封装中，可以利用引线键合，将半导体芯片焊区与微电子封装的I/O键合引线或基板上的金属布线焊区用金属细丝连接起来。引线键合的原理是采用加热、加压或超声波等方式破坏被焊表面的氧化层和污染，产生塑性变形，使得金属键合引线与被焊面亲密接触，达到原子间的引力范围并 导致界面间原子扩散而形成焊合点。
在本文中，表述“发光芯片”表示被配置为可以发出特定波长的光的芯片，例如，所述发光芯片可以包括发光二极管芯片，所述发光二极管芯片包括但不限于MiniLED芯片或MicroLED芯片。
在本文中，无机发光二极管是指利用无机材料制成的发光元件，其中，LED表示有别于OLED的无机发光元件。具体地，无机发光元件可以包括次毫米发光二极管(Mini Light Emitting Diode，英文缩写为MiniLED)和微型发光二极管(Micro Light Emitting Diode，英文缩写为MicroLED)。其中，微型发光二极管(即MicroLED)指的是晶粒尺寸在100微米以下的超小型发光二极管，次毫米发光二极管(即MiniLED)是指晶粒尺寸在MicroLED与传统LED之间的小型发光二极管，例如，MiniLED的晶粒尺寸可以在100～300微米之间，MicroLED的晶粒尺寸可以在10～100微米之间。
在本文中，SMT或SMT工艺表示表面贴装技术，巨量转移或巨量转移工艺是一种将大量的微型芯片转移至目标衬底上的技术，例如，常见的巨量转移技术包括如下步骤：从预定位置以非常高的空间精度和方向拾取微型芯片；将这些微型芯片移动到预定位置，同时保持微型芯片的相对空间位置和方向；然后，在保持新的相对位置和方向的同时，有选择地在该新位置分配这些微型芯片至目标衬底上。
在本文中，PVDF指的是聚偏二氟乙烯材料，其具有压电特性。
关于“芯片尺寸”，发明人经研究发现，芯片经过封装后相对于原有裸晶尺寸增加至少20％，同时，芯片内集成了各种不同的功能模块，也导致芯片的尺寸会增加。在本公开的实施例中，通过对芯片的功能拆解，并对包括该芯片的装置(例如显示基板)进行封装，可以实现芯片尺寸的减小。随着芯片尺寸的减小，可以有效降低缺陷对每片晶圆(wafer)上芯片良率的影响。而且，随着芯片尺寸的减小，产率逐渐提升，单片晶圆的等效直径不断增大，每片晶圆产出的芯片数量增大，从而可以大大降低芯片的成本。
在本文中，除非另有特别说明，表述“芯片”、“芯片模块”、“微型芯片”、“微芯片”等表示尺寸相对较小的芯片，例如，未封装的微米级芯片。以显示基板为例，所述显示基板可以包括但不限于如下芯片：传感芯片、控制芯片、逻辑运算芯片、存储芯片、驱动芯片、LED芯片以及其他功能芯片，还可以包括数模转换电路、放大电路、比较器、计数器等更为细分的子模块芯片。应该理解，所述显示基板可以包括至少一 个上述芯片。
在本文中，除非另有特别说明，表述“功能器件”可以包括用于实现特定功能的器件，其可以包括单个芯片、多个芯片组成的芯片组或电路结构等多种形式，例如，功能器件可以包括通过薄膜制程制作的薄膜晶体管和传感器中的至少一种。
在本文中，除非另有特别说明，表述“规则形状”表示规则图形，包括但不限于，矩形、圆角矩形、菱形、正方形、六边形、八边形、圆形、椭圆形、矩形、三角形等。
本公开的一些示例性实施例提供一种半导体装置及其制造方法。所述半导体装置包括：衬底；设置于所述衬底的芯片，所述芯片包括芯片主体和设置于所述芯片主体上的多个端子；设置于所述衬底的端子扩展层，所述端子扩展层包括导电材料，其中，所述端子扩展层和至少一个端子位于所述芯片主体的同一侧，所述半导体装置还包括位于所述端子扩展层中的多个扩展走线，所述多个扩展走线分别与所述多个端子电连接，用于引出所述多个端子；以及至少一个扩展走线在所述衬底上的正投影完全覆盖与该扩展走线电连接的端子在所述衬底上的正投影。在所述半导体装置中，通过所述端子扩展层引出芯片的端子，有利于芯片的键合。
例如，所述半导体装置包括：衬底；设置于所述衬底的多个芯片，每个芯片包括芯片主体和设置于所述芯片主体上的多个端子；设置于所述衬底的多个固定连接部；设置于所述衬底的端子扩展层，所述端子扩展层包括导电材料，其中，所述多个固定连接部分别邻近所述多个芯片设置；所述半导体装置还包括位于所述端子扩展层中的多个扩展走线，所述扩展走线用于电连接所述多个芯片；以及用于电连接两个芯片的扩展走线至少包括第一走线段和第二走线段，所述第一走线段用于电连接一个芯片的端子与该芯片邻近的一个固定连接部，所述第二走线段用于连接两个芯片之间的两个固定连接部。在所述半导体装置中，通过设置固定连接部，有利于实现各个芯片之间的电连接。
例如，所述半导体装置包括：相对设置的第一衬底和第二衬底；设置于所述第一衬底的芯片，所述芯片包括芯片主体和设置于所述芯片主体上的多个第一端子；设置于所述第一衬底的端子扩展层，所述端子扩展层包括导电材料；以及设置于所述第二衬底的多个第二端子，其中，所述端子扩展层和至少一个第一端子位于所述芯片主体的同一侧，所述半导体装置还包括位于所述端子扩展层中的多个扩展走线，所述多个扩展走线分别与所述多个第一端子电连接，用于引出所述多个第一端子；多个扩展走 线在所述第一衬底上的正投影完全覆盖与该扩展走线电连接的第一端子在所述第一衬底上的正投影；以及所述多个第一端子分别通过所述多个扩展走线与所述多个第二端子电连接，所述多个第二端子在所述第一衬底上的正投影与所述多个扩展走线在所述第一衬底上的正投影至少部分重叠。在所述半导体装置中，通过所述端子扩展层引出芯片的端子，有利于实现芯片与其它部件之间的键合。
需要说明的是，在本文中，主要以显示基板、显示面板和显示装置等显示装置为例，对本公开的示例性实施例进行说明。本公开的实施例不局限于此，还可以应用于其他类型的包括至少一个芯片的半导体装置。在本文中，芯片的类型包含但不限于发光芯片、传感芯片、控制芯片和驱动芯片，例如，LED芯片、模拟电路芯片、数字电路芯片、存储芯片、数模转换芯片、传感(声、光、电等)芯片或其他功能模块芯片。
例如，图1示意性示出了根据本公开的一些示例性实施例的显示装置的方框图。参照图1，在本公开的实施例中，将用于所述显示装置的具有集成功能的芯片可以拆分为多个微型芯片，每一个微型芯片可以比具有集成功能的芯片具有更少的功能，即，可以根据功能将所述具有集成功能的芯片进行拆分，这样，在所述显示装置中设置多个微型芯片。应该理解，每一个微型芯片的尺寸比所述具有集成功能的芯片的尺寸小，例如，每一个微型芯片可以为未封装的微米级芯片。相应地，在本文中，微型芯片上的端子的尺寸比传统芯片的端子的尺寸小，例如，微型芯片上的端子的尺寸在十几微米的级别，甚至可能小于10微米。这样，传统的bonding工艺无法满足微型芯片上的端子的尺寸精度；而且，现有的巨量转移工艺的精度也无法满足微型芯片上的端子的尺寸精度。
例如，在所述显示装置中，可以设置多个芯片，每一个芯片可以用于实现一个功能。例如，所述多个芯片可以包括LED芯片和与显示相关的驱动芯片、存储芯片、数模转换芯片和信息处理芯片等芯片。如图1所示，可以设置控制芯片1、逻辑运算芯片2、存储芯片3、驱动芯片4以及其他功能芯片5。驱动芯片4可以与显示单元6电连接。
例如，显示单元6可以包括LCD显示(液晶显示)单元、OLED(有机发光二极管)显示单元或LED(无机发光二极管)显示单元中的一种。
图2是示意性示出根据本公开实施例的显示基板中多个芯片的布置的示意图。图3A～图3C分别是示意性示出根据本公开实施例的显示基板中功能单元组与显示区的 相对位置关系的示意图。
结合参照图1至图3C，具备特定功能的多个芯片之间可以互连形成功能单元组CU。例如，控制芯片1、逻辑运算芯片2、存储芯片3、驱动芯片4以及其他功能芯片5可以互连，以形成一个功能单元组CU。
例如，所述显示装置可以包括显示基板。所述显示基板可以包括显示区AA和非显示区NA。所述显示基板可以包括位于所述显示区AA中的多个像素PX。例如，所述多个功能单元组CU可以周期性地或非周期性地排列在显示基板的衬底基板上。所述多个功能单元组CU可以位于所述显示区AA中，也可以位于非显示区NA中。可选地，所述多个功能单元组CU中的一些可以位于所述显示区AA中，所述多个功能单元组CU中的另一些可以位于非显示区NA中。
例如，参照图3A，多个功能单元组CU可以分别位于多个像素PX中，例如，一个像素PX中可以设置一个功能单元组CU。参照图3B，可以两个或两个以上的像素PX共用一个功能单元组CU。参照图3C，可以在一些像素PX中设置一个功能单元组CU，另一些像素PX中可以不设置功能单元组CU。
例如，功能单元组CU可以仅设置在特定的像素PX中，以实现低数据量需求的应用，例如眼球追踪等应用场景中。
例如，多个功能单元组CU之间可以根据需要可以进行互连，以实现数据的交互。
也就是说，根据本公开实施例的半导体装置(例如显示装置)包括设置在衬底上的多个芯片。在本公开的实施例中，通过后对准工艺，可以实现芯片内部、多个芯片之间以及芯片与显示单元之间的电连接，解决了微型芯片布线精度的问题。
图4是示意性示出本公开实施例的半导体装置(例如显示基板)中衬底上的端子(pad)与芯片上的端子(pad)之间的对位关系的示意图。结合参照图1至图4，上述多个芯片可以通过巨量转移工艺转移到例如衬底基板的衬底上。通过巨量转移工艺，可以实现衬底上的端子p2与芯片上的端子p1的对位。受限于巨量转移工艺的精度，衬底上的端子p2与芯片上的端子p1之间可能产生一定的对位偏差。
需要说明的是，在本公开的实施例中，芯片上的端子(例如p1)与衬底上的端子(例如p2)不需要重合，至少有一部分区域中的芯片上的端子(例如p1)与衬底上的端子(例如p2)不是面对面接触的。上面的描述中所述的“衬底上的端子p2与芯片上的端子p1之间可能产生一定的对位偏差”可以理解为在芯片转移过程中可能发生的 芯片上的端子p1与其理想位置之间的对位偏差导致的位置偏差。
例如，图4中示意性示出了六对衬底上的端子p2与芯片上的端子p1。在图4中，小尺寸的虚线框表示端子p2所处的位置，大尺寸的虚线框表示端子p1所处的理想位置(即，与端子p2精准对位的端子p1所处的位置)。为了描述方便，按照从上至下且从左至右的方式，将所述端子分别描述为第一对端子、第二对端子、第三对端子、第四对端子、第五对端子和第六对端子。在第一对端子中，端子p1位于其理想位置，在此情况下，端子p2与端子p1精准对位；在第二对端子中，端子p1相对于其理想位置向左偏移了一定的距离，导致端子p1相对于端子p2向左偏移了一定的距离；在第三对端子中，端子p1相对于其理想位置向上偏移了一定的距离，导致端子p1相对于端子p2向上偏移了一定的距离；在第四对端子中，端子p1相对于其理想位置向右偏移了一定的距离，导致端子p1相对于端子p2向右且向上偏移了一定的距离；在第五对端子中，端子p1相对于其理想位置向顺时针偏转了一定的角度，导致端子p1相对于端子p2顺时针偏转了一定的角度；在第六对端子中，端子p1相对于其理想位置向逆时针偏转了一定的角度，导致端子p1相对于端子p2逆时针偏转了一定的角度。也就是说，在实际的巨量转移工艺中，可能出现如下的情况：端子p1与端子p2精准对位，端子p1相对于端子p2沿第一方向和第二方向中的至少一个方向偏移一定的距离，端子p1相对于端子p2偏转一定的角度。
继续参照图4，所述半导体装置可以包括多个重复单元PU，多个重复单元沿第一方向D1和第二方向D2成阵列地布置在所述衬底上。每个重复单元PU可以包括多个所述芯片，位于每个重复单元PU内的多个芯片沿第一方向D1和第二方向D2成阵列地布置在所述衬底上，或者，位于每个重复单元内的多个芯片中的至少一部分沿第一方向和第二方向成阵列地布置在所述衬底上。
需要说明的是，在图示的实施例中，示意性示出了2个重复单元PU，每个重复单元PU包括3个芯片，但是，这些数量不应视为对本公开的实施例的限制。
例如，在所述多个重复单元PU中的至少两个中，一个重复单元PU中的至少一个芯片在该重复单元中的相对位置与另一个重复单元中的对应芯片在该另一个重复单元中的相对位置不相同。
在所述多个重复单元PU中的至少两个中，一个重复单元中的至少一个芯片在该重复单元中的朝向与另一个重复单元中的对应芯片在该另一个重复单元中的朝向不相 同。
在所述多个重复单元PU中的至少两个中，用于引出一个重复单元中的至少一个芯片的至少一个端子的扩展走线的长度与用于引出另一个重复单元中的对应芯片的对应端子的扩展走线的长度不相等。
在所述多个重复单元PU中的至少两个中，用于引出一个重复单元中的至少一个芯片的至少一个端子的扩展走线的延伸方向与用于引出另一个重复单元中的对应芯片的对应端子的扩展走线的延伸方向不相同。
需要说明的是，在本公开的实施例中，表述“对应芯片”可以理解为各个重复单元内处于对应位置的芯片，例如，在图4所示的实施例中，位于上侧的一个重复单元内最左侧的芯片和位于下侧的另一个重复单元内最左侧的芯片互为对应芯片。
在本公开的实施例中，可以采用后对准工艺形成位于端子扩展层(即RDL)的扩展走线，以电连接所述端子p1和所述端子p2。例如，可以采用拍照的方法识别所述端子p1和所述端子p2的位置，根据所述端子p1和所述端子p2的位置进行光刻图形的设计，利用无掩模光刻技术进行曝光，在端子扩展层RDL中形成多个扩展走线RL。基于设计出的光刻图形，所述多个扩展走线RL根据设计需要电连接所述端子p1和所述端子p2。在本公开的实施例中，无需提高巨量转移工艺的对位精度，可以实现微型芯片内部以及微型芯片之间的电连接，提高了微型芯片的布线精度。
图5A～图5D是示意性示出根据本公开实施例的后对准工艺的一些步骤的示意图。参照图5A，多个芯片CP可以形成于承载板SUB1上，例如，多个芯片CP可以成阵列地形成于承载板SUB1上，或者，多个芯片CP可以非周期性地形成于承载板SUB1上。例如，此处的“芯片CP”可以是上述的微型芯片，包括但不限于，上述的LED芯片、控制芯片1、逻辑运算芯片2、存储芯片3、驱动芯片4以及其他功能芯片5等。
参照图5B，通过巨量转移工艺，将多个芯片CP转移到衬底SUB2上。例如，衬底SUB2上可以设置粘性层AD1。该粘性层AD1可以起到固定芯片的作用。该粘性层AD1可以是整面的，也可以是图案化的。然后，可以通过后对准工艺形成多个扩展走线。具体地，参照图5C，可以在芯片CP上沉积金属层ML1和光刻胶层PR1，然后，通过构图工艺，形成图案化的光刻胶层PR1。参照图5D，刻蚀金属层ML1，以形成图案化的金属层ML1，该图案化的金属层ML1为上述端子扩展层RDL，形成在该端子扩展层RDL中的多个图案形成为多个扩展走线RL，以电连接各个端子。
例如，在图5C所示的实施例中，所述构图工艺包括但不限于数字曝光机、激光直写、EBL等亚微米曝光技术。
在本公开的实施例中，可以通过低位置精度的巨量转移工艺将芯片转移至衬底上，然后通过后对准工艺对低位置精度的芯片进行识别及分析，例如，可以通过拍照和图像识别的方法对芯片的端子p1和衬底的端子p2进行识别和分析，确定各个端子之间的相对位置关系。基于识别和分析的结果，生成自动布线文件。在图5C所示的构图工艺中，可以根据所述自动布线文件图案化光刻胶层PR1。这样，可以实现自动布线及高精度的芯片键合，实现微型芯片与显示单元的集成。此外，所述后对准工艺还至少具有以下优点：所述后对准工艺的精度取决于光学曝光的对位精度，光学曝光的对位精度远高于巨量转移工艺的对位精度，更适合微型芯片的键合；以及，后对准工艺采用曝光、显影、刻蚀工艺，更适合大面积、高效率的批量芯片键合。
例如，同一衬底上的芯片的形状和功能可以相同或不同。芯片的端子p1的引脚向上且数量大于等于2个，各个端子p1的尺寸和形貌可以相同或不同。图6A和图6B分别是根据本公开实施例的微型芯片的截面示意图和俯视示意图。如图6A所示，在同一衬底SUB2上，设置多个芯片CP，多个芯片CP的功能可以不同。多个芯片CP在截面图和俯视图中的形状可以不同。例如，参照图6A，芯片CP在截面图中可以呈矩形、梯形等各种形状。参照图6B，芯片CP在俯视图中可以呈现梯形、矩形、菱形、三角形、圆形、椭圆形等各种形状。
图7A、图7B和图7C分别是根据本公开实施例的微型芯片和端子扩展层中的扩展走线的透视图和截面示意图。如图7A和图7B所示，芯片CP在截面图中具有梯形形状。换句话说，芯片CP的至少一个侧面较平缓，即，芯片CP的至少一个侧面的坡度角小于90°，例如，小于70°。在该情况下，可以直接从芯片CP的端子p1上引出扩展走线，如图7B所示，从芯片CP的端子p1引出的扩展走线RL可以形成在坡度角小于90°的侧面上。例如，可以设置端子扩展层和至少一个重布线层，为了方便描述，将它们分别称为端子扩展层RDL1和重布线层RDL2，相应地，将位于端子扩展层RDL1和重布线层RDL2中的扩展走线分别称为扩展走线RL1和第一走线RL2。如图7A所示，端子扩展层RDL1和重布线层RDL2之间可以设置平坦化层PLN1。扩展走线RL1从芯片CP的端子p1直接引出。第一走线RL2通过贯穿平坦化层PLN1的过孔与扩展走线RL1电连接。以此方式，可以实现引出芯片的端子，有利于芯片的 各个端子之间的电连接。
如图7C所示，芯片CP在截面图中具有大致矩形形状。换句话说，芯片CP的侧面较陡峭，即，芯片CP的侧面的坡度角基本等于90°或接近90°，例如，在70°～90°的范围内。在该情况下，扩展走线不适合直接形成在芯片CP的侧面上，即，不适合直接从芯片CP的端子p1上引出扩展走线。可以先在芯片CP远离衬底的一侧形成平坦化层PLN1，且平坦化层PLN1的高度大于芯片CP的高度，使得平坦化层PLN1可以覆盖芯片CP及其上的端子p1。然后，通过后对准工艺形成扩展走线RL1。如图7C所示，所述半导体装置可以包括衬底SUB2，设置在衬底SUB2上的粘性层AD1，设置在粘性层AD1上的芯片CP，设置在芯片CP远离衬底一侧的平坦化层PLN1，和设置在平坦化层PLN1远离衬底一侧的扩展走线RL1。扩展走线RL1可以通过贯穿平坦化层PLN1的过孔与端子p1电连接。以此方式，可以实现引出芯片的端子，有利于芯片的各个端子之间的电连接。
结合参照图32，在芯片CP在截面图中具有大致矩形形状的情况下，可以在芯片CP的至少一个侧面上形成平坦化层，以形成具有较小坡度的侧面。这样，与图7A和图7B类似，可以在具有较小坡度的平坦化层的侧面上形成扩展走线。
需要说明的是，平坦化层PLN1可以具有单层或多层的结构。
图8A、图8B和图8C分别是根据本公开的一些实施例的微型芯片和端子扩展层中的扩展走线的截面示意图。如图8A所示，在根据本公开实施例的半导体装置中，衬底SUB2上设置有多个芯片CP，至少两个芯片CP之间存在高度差。为了方便描述，将具有高度差的两个芯片分别成为芯片CP1和芯片CP2。
如图8A所示，在芯片CP1与芯片CP2之间的高度差小于后对准曝光工艺在垂直方向上的工艺极限的情况下，可以通过一步后对准工艺实现布线，即，通过一步后对准工艺形成一层端子扩展层RDL1，位于该端子扩展层RDL1中的多个扩展走线RL1可以将芯片CP1和芯片CP2的端子都引出。例如，所述半导体装置可以包括衬底SUB2，设置在衬底SUB2上的粘性层AD1，设置在粘性层AD1上的芯片CP1、CP2，设置在芯片CP1、CP2远离衬底一侧的平坦化层PLN1，和设置在平坦化层PLN1远离衬底一侧的端子扩展层RDL1。端子扩展层RDL1中设置有多个扩展走线RL1。平坦化层PLN1的高度大于芯片CP1、CP2中每一个的高度。一部分扩展走线RL1可以通过贯穿平坦化层PLN1的过孔与芯片CP1的端子p1电连接，另一部分扩展走线RL1可以通过贯 穿平坦化层PLN1的过孔与芯片CP2的端子p1电连接。以此方式，可以实现引出芯片CP1和芯片CP2的端子，有利于芯片的各个端子之间的电连接。以此类推，可以实现引出多个芯片的端子，有利于多个芯片的端子之间的电连接。
如图8B所示，在芯片CP1与芯片CP2之间的高度差大于后对准曝光工艺在垂直方向上的工艺极限的情况下，可以通过至少两步后对准工艺实现布线，即，对薄的芯片CP1先进行后对准工艺及布线，再依次对不同厚度范围(例如较厚)的芯片CP2进行后对准工艺及布线。后一次后对准工艺与前一次后对准工艺中间需增加一层平坦化层。例如，所述半导体装置可以包括衬底SUB2，设置在衬底SUB2上的粘性层AD1，设置在粘性层AD1上的芯片CP1、CP2，设置在芯片CP1远离衬底一侧的平坦化层PLN1，设置在平坦化层PLN1远离衬底一侧的端子扩展层RDL1，设置在端子扩展层RDL1远离衬底一侧的平坦化层PLN2，和设置在平坦化层PLN2远离衬底一侧的重布线层RDL2。端子扩展层RDL1中设置有扩展走线RL1，重布线层RDL2中设置有第一走线RL2。扩展走线RL1可以通过贯穿平坦化层PLN1的过孔与芯片CP1的端子p1电连接，第一走线RL2可以通过贯穿平坦化层PLN2的过孔与芯片CP2的端子p1电连接。以此方式，可以实现引出芯片CP1和芯片CP2的端子，有利于芯片的各个端子之间的电连接。
如图8C所示，在芯片CP1与芯片CP2之间的高度差大于后对准曝光工艺在垂直方向上的工艺极限的情况下，可以在衬底上先制备衬垫，其中，芯片的高度差-后对准曝光工艺在垂直方向上的工艺极限≤衬垫的高度≤芯片的高度差；然后，可以通过一步后对准工艺实现布线。例如，所述半导体装置可以包括衬底SUB2，设置在衬底SUB2上的粘性层AD1，设置在粘性层AD1上的衬垫PS、芯片CP2，设置在衬垫PS上的芯片CP1，设置在芯片CP1、CP2远离衬底一侧的平坦化层PLN1，和设置在平坦化层PLN1远离衬底一侧的端子扩展层RDL1。端子扩展层RDL1中设置有多个扩展走线RL1。平坦化层PLN1的高度大于芯片CP1、CP2中每一个的高度，即，平坦化层PLN1远离衬底SUB2的表面的高度大于芯片CP1、CP2中每一个远离衬底SUB2的表面的高度。芯片CP1在衬底上的正投影位于衬垫PS在衬底上的正投影内，且芯片CP1在衬底上的正投影的面积小于衬垫PS在衬底上的正投影的面积。这样，芯片CP1和衬垫PS之间的对位精度不需要较高，有利于将芯片CP1置于衬垫PS上。一部分扩展走线RL1可以通过贯穿平坦化层PLN1的过孔与芯片CP1的端子p1电连接，另一部分 扩展走线RL1可以通过贯穿平坦化层PLN1的过孔与芯片CP2的端子p1电连接。以此方式，可以实现引出芯片CP1和芯片CP2的端子，有利于芯片的各个端子之间的电连接。
需要说明的是，在图8C所示的实施例中，衬底PS的高度也可以略大于芯片的高度差，例如，衬底PS的高度减去芯片的高度差的差值可以小于后对准曝光工艺在垂直方向上的工艺极限。
在本公开的实施例中，可以采用chip first工艺或chip later工艺，在所述衬底上形成所述芯片。例如，以所述半导体装置为显示装置为例，可以先形成所述芯片，后形成所述显示装置的驱动单元，即chip first工艺；或者，可以先形成所述显示装置的驱动单元，后形成所述芯片，即chip later工艺。
参照图4至图8C，在本公开的实施例中，所述芯片可以包括芯片主体CPM和设置在芯片主体CPM上的多个端子p1、p2。所述芯片主体CPM可以包括第一表面CPM1、第二表面CPM2、第一侧表面CPM3和第二侧表面CPM4，所述第二表面CPM2和所述第一表面CPM1分别位于所述芯片主体的相对侧，所述第一侧表面CPM3和所述第二侧表面CPM4分别位于所述芯片主体的侧表面，所述第一侧表面CPM3和所述第二侧表面CPM4中的每一个均连接所述第一表面CPM1与所述第二表面CPM2，所述第一表面CPM1面向或接触所述粘性层AD1，至少一个端子p1、p2设置在所述芯片主体除该第一表面CPM1之外的表面(例如CPM2、CPM3、CPM4)上。
如图4和图6A所示，所述衬底可以包括第一衬底表面SUBP，所述芯片设置在该第一衬底表面SUBP上，所述第一衬底表面SUBP包括第一衬底边缘SUBP1。
在本公开的实施例中，至少一个扩展走线RL在所述衬底上的正投影相对于所述第一衬底边缘SUBP1倾斜。
例如，所述第二表面CPM2在所述衬底上的正投影具有规则形状，如图6B所示，所述规则形状包括但不限于，矩形、圆角矩形、菱形、正方形、六边形、八边形、圆形、椭圆形、矩形、三角形等。如图4所示，所述第二表面CPM2在所述衬底上的正投影包括第一边缘CPM21。所述第一边缘CPM21相对于所述第一衬底边缘SUBP1倾斜。
例如，所述至少一个扩展走线RL在所述衬底上的正投影的延长线与所述第一衬底边缘SUBP1的延长线之间形成第一夹角，所述第一夹角大于0°小于90°。
例如，所述第一边缘CPM21的延长线与所述第一衬底边缘SUBP1的延长线之间形成第二夹角，所述第二夹角大于0°小于90°。
在常规的半导体装置及其制造工艺中，芯片相对于衬底的朝向不能偏转或仅能偏转较小的角度，例如，偏转的角度需要小于10°。这样，才能保证芯片的各个端子的有效键合。在本公开的实施例中，芯片相对于衬底的朝向可以偏转一定的角度，该偏转的角度可以在0°～90°之间，例如，可以在0°～50°之间，可以在1°～60°之间，可以大于10°小于90°，可以为约10°、约20°、约30°、约40°、约15°、约25°、约35°、约45°、约50°、约60°、约70°、约80°等。即，在本公开的实施例中，芯片相对于衬底可以偏转较大的角度，例如，可以大于10°。在本公开的实施例中，即使在芯片相对于衬底偏转较大的角度的情况下，仍可以通过后续的后对准工艺形成扩展布线层，实现芯片的有效键合，避免形成不良点。
图9是示出根据本公开实施例的chip first工艺形成的结构的示意图。图10是示出根据本公开实施例的chip later工艺形成的结构的示意图。
如图9所示，所述显示装置可以包括衬底SUB2，设置在衬底SUB2上的粘性层AD1，设置在粘性层AD1上的芯片CP1，设置在芯片CP1远离衬底一侧的端子扩展层RDL1，设置在端子扩展层RDL1远离衬底一侧的平坦化层PLN1，设置在平坦化层PLN1远离衬底一侧的重布线层RDL2，设置在重布线层RDL2远离衬底一侧的平坦化层PLN2，和设置在平坦化层PLN2远离衬底一侧的重布线层RDL3和驱动单元DRU。端子扩展层RDL1中设置有扩展走线RL1，重布线层RDL2中设置有第一走线RL2，重布线层RDL3中设置有第二走线RL3。例如，扩展走线RL1的至少一部分设置于芯片CP1的侧壁上，直接与芯片CP1的端子p1电连接。第一走线RL2可以通过贯穿平坦化层PLN1的过孔与扩展走线RL1电连接，第二走线RL3可以通过贯穿平坦化层PLN2的过孔与第一走线RL2电连接。例如，第二走线RL3与驱动单元DRU可以位于同一层，第二走线RL3可以与驱动单元DRU电连接。以此方式，可以实现引出芯片CP1的端子，并且实现芯片CP1与驱动单元DRU的电连接。在该实施例中，芯片CP1比驱动单元DRU更靠近衬底SUB2。在实际制造时，可以先在衬底SUB2上形成芯片CP1，接着通过后对准工艺形成多个端子扩展层，然后形成所述驱动单元DRU。应该理解，微型芯片的加工工艺精度通常会高于例如薄膜晶体管等的驱动单元的加工工艺精度，在该实施例中，将芯片转移到衬底后，再采用后对准工艺进行键合集成， 有利于规避例如薄膜晶体管等的驱动单元的加工工艺的壁垒，从而实现高分辨率的显示。
可选地，如图10所示，所述显示装置可以包括衬底SUB2，设置在衬底SUB2上的驱动单元DRU，设置在驱动单元DRU远离衬底一侧的平坦化层PLN1，设置在平坦化层PLN1远离衬底一侧的端子扩展层RDL1，设置在端子扩展层RDL1远离衬底一侧的粘性层AD1，设置在粘性层AD1上的芯片CP1，设置在芯片CP1远离衬底一侧的重布线层RDL2。端子扩展层RDL1中设置有扩展走线RL1，重布线层RDL2中设置有第一走线RL2。例如，第一走线RL2的至少一部分设置于芯片CP1的侧壁上，直接与芯片CP1的端子p1电连接。第一走线RL2可以通过贯穿粘性层AD1的过孔与扩展走线RL1电连接，扩展走线RL1可以通过贯穿平坦化层PLN1的过孔与驱动单元DRU电连接。以此方式，可以实现芯片CP1与驱动单元DRU的电连接。在该实施例中，芯片CP1比驱动单元DRU更远离衬底SUB2。在实际制造时，可以先在衬底SUB2上形成驱动单元DRU，接着通过后对准工艺形成端子扩展层，然后形成芯片CP1。在该实施例中，先在衬底上转移或制备例如薄膜晶体管等的驱动单元，后转移芯片至衬底上，避免了例如薄膜晶体管等的驱动单元的加工过程影响芯片性能。
在本公开的实施例中，所述驱动单元DRU包括但不限于薄膜晶体管(TFT)驱动电路、MOS驱动电路、驱动芯片(IC)等。例如，所述驱动单元或驱动元件可以用于LED芯片提供电信号，控制其发光亮度。例如，在一些示例中，所述驱动单元或驱动元件可以为与每个发光二极管芯片一一对应连接的多个像素驱动电路，或者是与每个发光二极管芯片一一对应连接的多个微型芯片等结构，可以控制每个LED芯片发出不同的亮度灰阶。需要说明的是，所述驱动单元或驱动元件的具体电路结构可以根据实际需要进行设置，本公开的实施例对此不作限制。
下面，以所述半导体装置为显示装置为例，进一步描述本公开的一些示例性实施例。
图11A和图11B分别是根据本公开的一些实施例的显示装置包括的芯片和显示单元的示例性布置的示意图。例如，芯片CP1可以是用于驱动显示单元的驱动芯片，显示单元DU可以是可以发光的LED芯片。
参照图11A，一个像素可以包括3个LED芯片，例如，对应R、G、B子像素。一个芯片CP1可以对应一个像素，即，一个驱动芯片用于驱动一个像素。可选地，参 照图11B，一个芯片CP1可以对应多个像素，即，一个驱动芯片用于驱动多个像素。通过这样的布置，可以利用驱动芯片以有源矩阵方式(AM方式)驱动多个像素。
参照图11A，多个发光二极管沿第一方向X和第二方向Y成阵列地排列。例如，第一方向X为行方向且第二方向Y为列方向。当然，本公开的实施例不限于此，第一方向和第二方向可以为任意的方向，只需使第一方向和第二方向交叉即可。并且，多个LED芯片也不限于沿直线排列，也可以沿曲线排列、沿环形排列或按照任意的方式排列，这可以根据实际需求而定，本公开的实施例对此不作限制。
需要说明的是，在本公开的实施例中，芯片CP1不局限于用于驱动显示单元的驱动芯片，还可以包括控制芯片、逻辑运算芯片、存储芯片以及其他功能芯片等。
在本文中，为了描述方便，将用于驱动或控制LED的芯片称为芯片CP1，将用于发光的LED芯片称为CP3。
根据芯片CP1的尺寸大小，根据本公开实施例的显示装置的制造方法可以包括至少两种工艺路线。
图12A至图12F是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图。在芯片CP1的尺寸较小的情况下，根据本公开的示例性实施例的显示装置的制造方法可以至少包括以下步骤。需要说明的是，芯片CP1的尺寸较小的情况可以包括：芯片CP1的尺寸基本等于或小于LED芯片的尺寸，或者说，芯片CP1在衬底上的正投影的面积与LED芯片在衬底上的正投影的面积之比小于等于1.2。
参照图12A，在衬底SUB2上涂覆或者粘贴粘性层AD1。例如，衬底SUB2可以是玻璃衬底。粘性层AD1的材料可以包括热熔胶、激光固化胶或紫外固化胶等。
参照图12B，将驱动芯片CP1和/或LED芯片CP3通过SMT或者巨量转移工艺转移至衬底SUB2上，并通过粘性层AD1固定于衬底上。
例如，驱动芯片CP1和LED芯片CP3可以均位于粘性层AD1上，驱动芯片CP1和LED芯片CP3的端子p1可以朝上，即位于芯片远离衬底的一侧。
例如，驱动芯片CP1可以采用Si基COMS工艺，本公开的实施例对此不做限定。
参照图12C，在驱动芯片CP1和LED芯片CP3远离衬底的一侧沉积钝化层PVX1，并且在钝化层PVX1远离衬底的一侧涂覆平坦化层PLN1。
例如，钝化层PVX1可以包括二氧化硅等材料，用于绝缘及增加覆盖层OC1的粘 附力。平坦化层PLN1可以包括树脂类材料，用于填平驱动芯片CP1和LED芯片CP3等各个芯片之间的段差，实现平坦化。可选地，在其他实施例中，可以不制备所述钝化层PVX1。
可选地，可以在平坦化层PLN1远离衬底的一侧制备钝化层PVX2。例如，钝化层PVX2可以包括氮化硅等材料，用于隔绝平坦化层PLN1中的水汽，防止平坦化层PLN1中的水汽腐蚀上层的端子扩展层。
参照图12D，对形成有所述芯片的衬底(可以称为背板)进行拍照，并采用图像识别技术确定设置在所述背板上的各个驱动芯片CP1和LED芯片CP3的端子p1的位置，按照相应的逻辑生成端子区(即pad区)的开孔的图形文件。接着，在背板上涂覆光刻胶，并根据上述图形文件通过数字直写或者数字曝光机图案化光刻胶，然后，刻蚀钝化层PVX2、平坦化层PLN1和钝化层PVX2未被光刻胶的图案覆盖的部分，以形成暴露各个驱动芯片CP1和LED芯片CP3的端子p1的一部分的过孔VH3。可选地，也可以直接用EBL刻蚀钝化层PVX2、平坦化层PLN1和钝化层PVX2位于端子上方的部分，以形成暴露各个驱动芯片CP1和LED芯片CP3的端子p1的一部分的过孔VH3。
参照图12E，在钝化层PVX2远离衬底的一侧制备端子扩展层RDL1。然后，根据各个端子的连接关系，且基于之前确定的各个驱动芯片CP1和LED芯片CP3的端子p1的位置，自动生成端子扩展层RDL1的图形文件。采用数字曝光或者EBL图案化端子扩展层RDL1，以形成多个扩展走线RL1。即，通过后对准工艺，在端子扩展层RDL1中形成用于电连接各个芯片的扩展走线RL1。
例如，端子扩展层RDL1可以包括单个膜层结构或多个膜层组成的叠层结构。在端子扩展层RDL1包括单个膜层结构的情况下，端子扩展层RDL1可以包含铜(Cu)等金属材料。在端子扩展层RDL1包括多个膜层组成的叠层结构的情况下，端子扩展层RDL1可以包含钛/铝/钛(Ti/Al/Ti)、钼铝钼(Mo/Al/Mo)等材料。
可选地，参照图12F，在完成上述后对准工艺后，根据线路互连的需求，可以制备重布线层RDL2。
例如，可以在端子扩展层RDL1远离衬底的一侧形成覆盖层PLN2。然后，在覆盖层PLN2远离衬底的一侧形成重布线层RDL2。
例如，重布线层RDL2可以通过传统的光刻工艺制备，以在重布线层RDL2中形 成用于电连接各个芯片的第一走线RL2。本公开的实施例不局限于此，重布线层RDL2也可以通过后对准工艺制备。
例如，覆盖层PLN2可以包括氮化硅、氧化硅或者氮化硅和氧化硅组成的叠层结构，也可以包括聚合物材料，用于隔离和绝缘端子扩展层RDL1与重布线层RDL2。
例如，根据走线需求，还可以制备第三层布线、第四层布线等，本公开的实施例在此不做特别限制。
参照图12F，根据本公开的一些实施例的半导体装置可以是显示装置，它可以包括：衬底SUB2；设置在衬底SUB2上的粘性层AD1；设置在粘性层AD1远离衬底一侧的多个芯片CP1、CP3，每一个芯片可以包括至少一个端子p1；设置在多个芯片CP1、CP3远离衬底一侧的钝化层PVX1；设置在钝化层PVX1远离衬底一侧的平坦化层PLN1；设置在平坦化层PLN1远离衬底一侧的钝化层PVX2；设置在钝化层PVX2远离衬底一侧的端子扩展层RDL1；设置在端子扩展层RDL1远离衬底一侧的覆盖层PLN2；和设置在覆盖层PLN2远离衬底一侧的重布线层RDL2。多个扩展走线RL1位于端子扩展层RDL1中，多个第一走线RL2位于重布线层RDL2中。
例如，多个芯片CP1、CP3可以位于同一层，即，芯片CP1、CP3面向衬底的表面均可以与粘性层AD1接触。芯片CP1、CP3中的一些端子p1可以通过多个扩展走线RL1电连接。芯片CP1、CP3中的另一些端子p1可以通过多个第一走线RL2电连接。
图13A至图13G是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图。在芯片CP1的尺寸较大的情况下，根据本公开的示例性实施例的显示装置的制造方法可以至少包括以下步骤。需要说明的是，芯片CP1的尺寸较大的情况可以包括：芯片CP1的尺寸大于LED芯片的尺寸，或者说，芯片CP1在衬底上的正投影的面积与LED芯片在衬底上的正投影的面积之比大于1.2。
参照图13A，在衬底SUB2上涂覆或者粘贴粘性层AD1。
参照图13B，将LED芯片CP3通过SMT或者巨量转移工艺转移至衬底SUB2上，并通过粘性层AD1固定于衬底上。
例如，LED芯片CP3的端子p1可以朝上，即位于芯片远离衬底的一侧。
参照图13C，在驱动芯片CP1和LED芯片CP3远离衬底的一侧沉积钝化层PVX1，并且在钝化层PVX1远离衬底的一侧涂覆平坦化层PLN1。
可选地，可以在平坦化层PLN1远离衬底的一侧制备钝化层PVX2。
参照图13D，对形成有所述芯片的衬底(可以称为背板)进行拍照，并采用图像识别技术确定设置在所述背板上的各个LED芯片CP3的端子p1的位置，按照相应的逻辑生成端子区(即pad区)的开孔的图形文件。接着，在背板上涂覆光刻胶，并根据上述图形文件通过数字直写或者数字曝光机图案化光刻胶，然后，刻蚀钝化层PVX2、平坦化层PLN1和钝化层PVX2未被光刻胶的图案覆盖的部分，以形成暴露各个LED芯片CP3的端子p1的一部分的过孔VH3。可选地，也可以直接用EBL刻蚀钝化层PVX2、平坦化层PLN1和钝化层PVX2位于端子上方的部分，以形成暴露各个LED芯片CP3的端子p1的一部分的过孔VH3。
参照图13E，在钝化层PVX2远离衬底的一侧制备端子扩展层RDL1。然后，根据各个端子的连接关系，且基于之前确定的各个LED芯片CP3的端子p1的位置，自动生成端子扩展层RDL1的图形文件。采用数字曝光或者EBL图案化端子扩展层RDL1，以形成多个扩展走线RL1。即，通过后对准工艺，在端子扩展层RDL1中形成用于电连接各个芯片的扩展走线RL1。
可选地，参照图13F，在完成上述后对准工艺后，根据线路互连的需求，可以制备重布线层RDL2。
例如，可以在端子扩展层RDL1远离衬底的一侧形成覆盖层PLN2。然后，在覆盖层PLN2远离衬底的一侧形成重布线层RDL2。
例如，重布线层RDL2可以通过传统的光刻工艺制备，以在重布线层RDL2中形成用于电连接各个芯片的第一走线RL2。本公开的实施例不局限于此，重布线层RDL2也可以通过后对准工艺制备。
例如，根据走线需求，还可以制备第三层布线、第四层布线等，本公开的实施例在此不做特别限制。
参照图13G，将驱动芯片CP1通过SMT或者巨量转移工艺转移到衬底SUB2上。例如，驱动芯片CP1的端子p1可以通过共晶焊、锡膏焊、导电胶等与位于重布线层RDL2中的第一走线RL2电连接，从而实现驱动芯片CP1与LED芯片CP3之间的电连接。
参照图13G，根据本公开的一些实施例的半导体装置可以是显示装置，它可以包括：衬底SUB2；设置在衬底SUB2上的粘性层AD1；设置在粘性层AD1远离衬底一 侧的多个LED芯片CP3，每一个LED芯片CP3可以包括至少一个端子p1；设置在多个LED芯片CP3远离衬底一侧的钝化层PVX1；设置在钝化层PVX1远离衬底一侧的平坦化层PLN1；设置在平坦化层PLN1远离衬底一侧的钝化层PVX2；设置在钝化层PVX2远离衬底一侧的端子扩展层RDL1；设置在端子扩展层RDL1远离衬底一侧的覆盖层PLN2；设置在覆盖层PLN2远离衬底一侧的重布线层RDL2；和设置在重布线层RDL2远离衬底一侧的至少一个芯片CP1。多个扩展走线RL1位于端子扩展层RDL1中，多个第一走线RL2位于重布线层RDL2中。
例如，芯片CP1和芯片CP3可以位于不同的层。多个LED芯片CP3可以位于同一层，均与粘性层AD1接触。驱动芯片CP1可以位于多个LED芯片CP3远离衬底的一侧。位于下层的LED芯片CP3通过扩展走线RL1和第一走线RL2与位于上层的驱动芯片CP1电连接。
图14是根据本公开的一些实施例的半导体装置(例如显示装置)的示意截面图，其中所述显示装置可以为大尺寸显示装置或拼接式显示装置。结合参照图13G和图14，可以在图13G示出的2个结构之间设置用于电连接电路板(例如柔性电路板FPC)的绑定区BND。在本公开的实施例中，绑定区BND无需打孔或者引线，绑定区BND处于LED的发光区的背侧，从而有利于实现无缝拼接显示。而且，显示装置的边缘无需设置扩展走线区，这样，形成的显示装置的边缘尺寸仅与衬底的切割工艺边有关。例如，在采用激光切割工艺的情况下，激光切割崩边的宽度可以控制在20微米以内，热影响区的宽度可以小于50微米，因此，可以实现更小的边框，且可以实现显示装置的四边等宽，有利于应用于拼接显示。
返回参照图13G，LED的主发光面可以面向衬底SUB2，即，驱动芯片CP1可以位于LED的发光侧的背面，这样，驱动芯片CP1可以不占用发光区的面积，即，驱动芯片CP1在衬底SUB2上的正投影可以与LED芯片CP3在衬底SUB2上的正投影至少部分重叠。因此，可以较小的间距设置多个驱动芯片CP1，从而有利于实现高分辨率显示。
需要说明的是，本公开的实施例不局限于朝下发光这样的实施方式。图15是根据本公开的一些实施例的半导体装置(例如显示装置)的示意截面图，其示意性示出了朝上发光的实施方式。参照图15，LED芯片CP3可以朝上发光，即，驱动芯片CP1可以位于LED的发光侧。即，驱动芯片CP1在衬底SUB2上的正投影与LED芯片CP3 在衬底SUB2上的正投影不重叠。
图16是根据本公开的一些实施例的半导体装置(例如显示装置)的示意截面图。结合参照图13G和图16，所述显示装置还可以包括：设置在重布线层RDL2远离衬底一侧的粘性层AD2；设置在粘性层AD2远离衬底一侧的驱动芯片CP1；设置在驱动芯片CP1远离衬底一侧的钝化层PVX3；设置在钝化层PVX3远离衬底一侧的平坦化层PLN3；和设置在平坦化层PLN3远离衬底一侧的重布线层RDL3。多个第二走线RL3可以设置在重布线层RDL3中。驱动芯片CP1的多个端子p1可以朝上，即面向远离衬底的一侧。驱动芯片CP1设置在粘性层AD2上，有利于驱动芯片CP1的固定。
例如，制备重布线层RDL3和第二走线RL3的工艺可以与制备端子扩展层RDL1和扩展走线RL1的工艺相似，即，也采用后对准工艺制备重布线层RDL3和第二走线RL3。
驱动芯片CP1可以通过第二走线RL3与第一走线RL2电连接，第一走线RL2与扩展走线RL1电连接，以及扩展走线RL1与LED芯片CP3的端子p1电连接。这样，可以实现驱动芯片CP1与LED芯片CP3之间的电连接。
下面，进一步以显示装置为例，详细描述本公开的一些示例性实施例。
图17A至图17I是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图。
参照图17A和图17B，在衬底SUB2上涂覆或者粘贴粘性层AD1。例如，衬底SUB2可以是玻璃衬底、聚酰亚胺(即PI)衬底或石英衬底。粘性层AD1可以采用激光解离胶、温度变化解离胶、UV解离胶等，这样，可以在后续工艺中采用特定手段进行剥离，以去除该衬底SUB2。
例如，在本公开的实施例中，所述衬底的材料可以包括但不限于玻璃，石英，塑料，硅，聚酰亚胺等。所述端子可以为柱状结构。所述端子的材料可以包括导电材料，例如金属材料等，具体地，可以为金、银、铜、铝、钼、金合金、银合金、铜合金、铝合金、钼合金等中选择的至少一种或者至少两种的组合，本公开的实施例对此不作限制。
然后，将LED芯片CP3和/或功能元件CP4通过SMT或者巨量转移工艺转移至衬底SUB2上，并通过粘性层AD1固定于衬底上。
例如，LED芯片CP3和功能元件CP4可以均位于粘性层AD1上，LED芯片CP3 和功能元件CP4的端子p1可以朝上，即位于芯片远离衬底的一侧。例如，此处的功能元件CP4可以是上述的微型芯片，用于实现特定的功能，包括但不限于，控制芯片、存储芯片、逻辑运算芯片、传感芯片等。
参照图17B和图17C，对设置有所述LED芯片CP3和功能元件CP4的衬底(可以称为背板)进行拍照，并采用图像识别技术确定设置在所述背板上的各个LED芯片CP3和功能元件CP4的端子p1的坐标和面积，生成端子区(即pad区)的图形文件。接着，在整个背板上沉积金属层，在金属层上涂布光刻胶，并根据上述图形文件通过数字直写或者数字曝光机图案化光刻胶。然后，根据图案化的光刻胶，对金属层进行刻蚀，以形成端子扩展层RDL1。在该端子扩展层RDL1中形成有多个扩展走线RL1，该多个扩展走线RL1可以分别与各个LED芯片CP3和功能元件CP4的端子p1电连接，以将各个端子p1引出。即，通过后对准工艺，在端子扩展层RDL1中形成用于电连接各个芯片的扩展走线RL1。
例如，端子扩展层RDL1可以包括单个膜层结构或多个膜层组成的叠层结构。在端子扩展层RDL1包括单个膜层结构的情况下，端子扩展层RDL1可以包含铜(Cu)等金属材料。在端子扩展层RDL1包括多个膜层组成的叠层结构的情况下，端子扩展层RDL1可以包含钛/铝/钛(Ti/Al/Ti)、钼铝钼(Mo/Al/Mo)等材料。
参照图17D，在端子扩展层RDL1远离衬底的一侧涂覆平坦化层PLN1。
例如，平坦化层PLN1可以包括树脂类材料，用于填平各个LED芯片CP3和功能元件CP4之间的段差，实现平坦化。
可选地，可以在平坦化层PLN1远离衬底的一侧制备钝化层PVX2。例如，钝化层PVX2可以包括氮化硅等材料，用于隔绝平坦化层PLN1中的水汽，防止平坦化层PLN1中的水汽腐蚀上层的端子扩展层。
继续参照图17D，可以形成贯穿平坦化层PLN1和钝化层PVX2的过孔，以暴露各个扩展走线RL1的至少一部分。然后，在钝化层PVX2远离衬底的一侧沉积金属层，通过包括涂覆光刻胶、曝光、显影、刻蚀等步骤的构图工艺，形成重布线层RDL2。例如，在该重布线层RDL2中形成有多个第一走线RL2。该多个第一走线RL2可以分别通过上述过孔与多个扩展走线RL1电连接，以进一步将各个端子p1引出。
参照图17E，在重布线层RDL2远离衬底的一侧形成粘性层AD2。接着，粘性层AD2远离衬底的一侧形成驱动元件DRU。驱动元件DRU可以通过粘性层AD2固定于 衬底上。
例如，所述驱动元件DRU可以包括驱动芯片CP1，所述驱动芯片CP1可以通过SMT或者巨量转移工艺转移至衬底SUB2上，并通过粘性层AD2固定于衬底上。再例如，所述驱动元件DRU可以包括薄膜晶体管等电子元件，即，可以通过制备TFT的工艺在衬底SUB2上形成多个薄膜晶体管。
接着，在驱动元件DRU远离衬底的一侧形成平坦化层PLN2。例如，平坦化层PLN2可以包括树脂类材料，用于填平各个驱动元件DRU之间的段差，实现平坦化。
然后，可以形成贯穿平坦化层PLN2和粘性层AD2的过孔，以暴露各个第一走线RL2的至少一部分。在平坦化层PLN2远离衬底的一侧沉积金属层，通过包括涂覆光刻胶、曝光、显影、刻蚀等步骤的构图工艺，形成重布线层RDL3。例如，在该重布线层RDL3中形成有多个第二走线RL3。该多个第二走线RL3可以分别通过上述过孔与多个第一走线RL2电连接，以进一步将各个端子p1引出，并且电连接驱动元件DRU与各个LED芯片CP3和各个功能元件CP4。
参照图17F，在重布线层RDL3远离衬底的一侧形成平坦化层PLN3。然后，衬底SUB4通过粘性层AD3贴附在平坦化层PLN3远离衬底SUB2的表面上。
参照图17G，通过激光解离、温度解离或者UV解离等方式将衬底SUB2与其上形成的器件分离。
参照图17H，在各个LED芯片CP3和各个功能元件CP4远离衬底SUB4的一侧涂布保护层PTL。
参照图17I，对保护层PTL执行构图工艺，以暴露各个LED芯片CP3和各个功能元件CP4靠近保护层PTL的表面。这样，保护层PTL可以保护例如扩展走线RL1的金属层，使得金属层可以不暴露于空气中，同时，使得各个LED芯片CP3的主发光面以及各个功能元件CP4的功能表面可以暴露出来，有利于发光和实现各自的功能。
需要说明的是，在本公开的实施例中，对保护层PTL执行构图工艺这一步骤是可选的。例如，在一些实施例中，至少一部分芯片或功能元件面向保护层PTL的表面可以不暴露出来，此时，不需要对于这些芯片或功能元件对应的保护层PTL的部分执行构图工艺。
例如，所述保护层PTL可以包括绝缘层，即起到绝缘的作用。
在上述实施例中，各个芯片的端子p1位于芯片的一个表面上，例如，LED芯片 CP3包括至少两个端子p1，该至少两个端子p1均位于LED芯片CP3的远离出光面的表面上，即位于出光侧的背面。但是，本公开的实施例不局限于这样的端子布置方式。
图18示意性示出了根据本公开的一些实施例的半导体装置的示意截面图，其中芯片的端子位于芯片的两个相对侧面上。参照图18，芯片CP包括至少两个端子p1，至少两个端子p1分别位于芯片CP的两个相对侧面上。芯片CP包括面向衬底SUB2的表面(即图18中的下表面)，所述芯片CP的两个相对侧面分别位于该下表面的两侧。例如，图18中所示的芯片CP可以是上述的LED芯片CP3和/或功能元件CP4。
在图18所示的实施例中，位于端子扩展层RDL1中的扩展走线RL1也可以分别与至少两个端子p1电连接，从而将芯片的端子p1引出。
图19A至图19H是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图，其中芯片的端子位于芯片的上、下表面上。
参照图19A，在衬底SUB2上涂覆或者粘贴粘性层AD1。例如，衬底SUB2可以是玻璃衬底、聚酰亚胺(即PI)衬底或石英衬底。粘性层AD1可以采用激光解离胶、温度变化解离胶、UV解离胶等，这样，可以在后续工艺中采用特定手段进行剥离，以去除该衬底SUB2。
接着，在粘性层AD1远离衬底的一侧形成导电层CDL1。例如，该导电层CDL1可以包括金属、导电氧化物等导电材料。
在导电层CDL1远离衬底的一侧形成粘性层AD2。例如，粘性层AD2可以具有粘性，并可以通过加热回流的方式蒸发掉。例如，粘性层AD2可以包含阻焊剂。
然后，将芯片CP(例如LED芯片CP3和/或功能元件CP4)通过SMT或者巨量转移工艺转移至衬底SUB2上。如图19A所示，芯片CP在靠近衬底SUB2的表面(即图中的下表面)和远离衬底SUB2的表面(即图中的上表面)上均具有端子。此处，为了方便描述，将位于下表面上的端子称为端子p11，将位于上表面上的端子称为端子p12。
参照图19B，通过加热回流的方式，蒸发掉粘性层AD2，使得端子p11可以与导电层ADL1电连接。这样，芯片CP与下方的导电层ADL1实现良好的导通。
参照图19C，在芯片CP远离衬底的一侧形成钝化层PVX1，在钝化层PVX1远离衬底的一侧形成平坦化层PLN1。
参照图19C和图19D，对设置有所述芯片CP的衬底(可以称为背板)进行拍照， 并采用图像识别技术确定设置在所述背板上的各个芯片CP的端子p12的坐标和面积，生成端子区(即pad区)的图形文件。接着，在整个背板上沉积金属层，在金属层上涂布光刻胶，并根据上述图形文件通过数字直写或者数字曝光机图案化光刻胶。然后，根据图案化的光刻胶，对金属层进行刻蚀，以形成端子扩展层RDL1。在该端子扩展层RDL1中形成有多个扩展走线RL1，该多个扩展走线RL1可以通过过孔分别与各个芯片CP的端子p12电连接，以将各个端子p12引出。即，通过后对准工艺，在端子扩展层RDL1中形成用于电连接各个芯片的扩展走线RL1。
参照图19E，在端子扩展层RDL1远离衬底的一侧形成粘性层AD3。接着，在粘性层AD3远离衬底的一侧形成驱动元件DRU。驱动元件DRU可以通过粘性层AD3固定于衬底上。
接着，在驱动元件DRU远离衬底的一侧形成平坦化层PLN2。
然后，可以形成贯穿平坦化层PLN2和/或粘性层AD3的过孔，以暴露各个扩展走线RL1和驱动元件DRU的端子的至少一部分。在平坦化层PLN2远离衬底的一侧沉积金属层，通过包括涂覆光刻胶、曝光、显影、刻蚀等步骤的构图工艺，形成重布线层RDL2。例如，在该重布线层RDL2中形成有多个第一走线RL2。该多个第一走线RL2可以分别通过上述过孔与多个扩展走线RL1电连接，以进一步将各个端子p12引出，并且电连接驱动元件DRU与各个芯片CP。
参照图19F，在重布线层RDL2远离衬底的一侧形成平坦化层PLN3。然后，衬底SUB4通过粘性层AD4贴附在平坦化层PLN3远离衬底SUB2的表面上。
参照图19G，通过激光解离、温度解离或者UV解离等方式将衬底SUB2与其上形成的器件分离。
参照图19H，在导电层CDL1远离衬底SUB4的一侧涂布保护层PTL。然后，对保护层PTL执行构图工艺，以暴露导电层CDL1的一部分(例如对应各个芯片CP的部分)靠近保护层PTL的表面。这样，通过导电层CDL1暴露的一部分，可以将芯片CP的端子p11引出。
下面，进一步以所述半导体装置为显示装置以及所述显示装置的驱动元件包括TFT驱动电路为例，详细描述本公开的一些示例性实施例。
图20A至图20F是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图，其中所述显示装置的驱动元件包括TFT驱动电路， 以及所述制造方法通过上述chip first工艺实现。
参照图20A，在衬底SUB2上涂覆或者粘贴粘性层AD1。例如，衬底SUB2可以是玻璃衬底、聚酰亚胺(即PI)衬底或石英衬底。粘性层AD1可以采用激光解离胶、温度变化解离胶、UV解离胶等，这样，可以在后续工艺中采用特定手段进行剥离，以去除该衬底SUB2。
参照图20B，将多个芯片CP通过SMT或者巨量转移工艺转移至衬底SUB2上，并通过粘性层AD1固定于衬底上。例如，所述多个芯片CP可以包括但不限于LED芯片、驱动芯片、存储芯片、控制芯片、数模转换芯片、信息处理芯片、传感器芯片等。例如，所述LED芯片可以为去除蓝宝石衬底的LED芯片，所述驱动芯片、存储芯片、控制芯片、数模转换芯片、信息处理芯片、传感器芯片可以为Si基芯片，该Si基芯片可以为无封装结构的裸芯片，芯片的高度可以在100微米以下。
在图20B的实施例中，示意性示出了4个芯片，为了方便描述，将4个芯片分别称为芯片CP1、CP2、CP3和CP4，例如，芯片CP1可以是控制芯片，芯片CP2可以是存储芯片，芯片CP3可以是LED芯片，芯片CP4可以是传感器芯片。应该理解，本公开的实施例不局限于图20B所示的布置方式。
例如，芯片CP1、CP2、CP3、CP4可以均位于粘性层AD1上，各个芯片CP1、CP2、CP3、CP4的端子p1可以朝上，即位于芯片远离衬底的一侧。
参照图20C，对设置有所述芯片CP1、CP2、CP3、CP4的衬底(可以称为背板)进行拍照，并采用图像识别技术确定设置在所述背板上的各个芯片CP1、CP2、CP3、CP4的端子p1的坐标和面积，生成端子区(即pad区)的图形文件。接着，在整个背板上沉积金属层，在金属层上涂布光刻胶，并根据上述图形文件通过数字直写或者数字曝光机图案化光刻胶。然后，根据图案化的光刻胶，对金属层进行刻蚀，以形成端子扩展层RDL1。在该端子扩展层RDL1中形成有多个扩展走线RL1，该多个扩展走线RL1可以分别与各个芯片CP1、CP2、CP3、CP4的端子p1电连接，以将各个端子p1引出。即，通过后对准工艺，在端子扩展层RDL1中形成用于电连接各个芯片的扩展走线RL1。
继续参照图20C，在端子扩展层RDL1远离衬底的一侧涂覆平坦化层PLN1。
可选地，可以在平坦化层PLN1靠近衬底的一侧制备钝化层PVX1，在平坦化层PLN1远离衬底的一侧制备钝化层PVX2。例如，钝化层PVX1和钝化层PVX2可以包 括氮化硅、氧化硅等材料，用于隔绝平坦化层PLN1中的水汽，防止平坦化层PLN1中的水汽腐蚀端子扩展层。
继续参照图20C，可以形成贯穿钝化层PVX1、平坦化层PLN1和钝化层PVX2的过孔VH1，以暴露各个扩展走线RL1的至少一部分。
在本公开的一些实施例中，平坦化层PLN1可以包含树脂类材料，例如，聚酰亚胺(即PI)等材料，用于填平各个芯片CP1、CP2、CP3、CP4之间的段差，实现平坦化。
在本公开的一些实施例中，平坦化层PLN1可以包含可低温固化的平坦化材料，例如，丙烯酸树脂类材料。可低温固化的平坦化材料的成本低于聚酰亚胺类材料的成本，从而有利于降低产品的成本。
还需要说明的是，在芯片转移完成后采用可低温固化的平坦化材料，然后可以采用低温氧化物TFT制程或者其他可低温制作的半导体装置，完成整个TFT器件的制作。例如，可低温固化的平坦化材料的固化温度可以小于250℃，相应地，在TFT制程中可以在250℃以下制备所述TFT器件，这样，可以降低TFT制程中的高温对微型芯片的性能造成损伤的风险。
例如，平坦化层PLN1的厚度比各个芯片CP1、CP2、CP3、CP4的最大高度高10微米以上。
参照图20D，在钝化层PVX2远离衬底的一侧沉积金属层，通过包括涂覆光刻胶、曝光、显影、刻蚀等步骤的构图工艺，形成重布线层RDL2。例如，在该重布线层RDL2中形成有多个第一走线RL2。该多个第一走线RL2可以分别通过上述过孔与多个扩展走线RL1电连接，以进一步将各个端子p1引出。
图26A和图26B分别示意性示出了根据本公开实施例的显示装置的过孔的示意截面图。
在形成重布线层RDL2的过程中，金属层的一部分需要沉积于过孔VH1中，以使得位于重布线层RDL2中的多个第一走线RL2可以分别通过过孔VH1与位于端子扩展层RDL1中的多个扩展走线RL1电连接。在这种情况下，可以采用传统的有机材料形成端子扩展层RDL1与重布线层RDL2之间的绝缘层。参照图26A，过孔VH1在截面图中的形状为倒梯形的形状，以有利于金属层的一部分沉积于过孔VH1中。
可选地，在本公开的一些实施例中，可以以端子扩展层RDL1为种子层，采用电 化学方式或化学镀方式镀所述金属层(例如铜层)，这样，可以在过孔VH1中生长与钝化层PVX1、平坦化层PLN1和钝化层PVX2的组合等厚度的金属层，以填平所述过孔VH1，使得位于重布线层RDL2中的多个第一走线RL2可以分别通过过孔VH1与位于端子扩展层RDL1中的多个扩展走线RL1电连接。
在这种情况下，可以采用耐高温有机材料形成端子扩展层RDL1与重布线层RDL2之间的绝缘层。在此基础上，可以使用硬掩模层-曝光显影-干刻-去除硬掩模层的方式形成较垂直的过孔。参照图26B，过孔VH1在截面图中的形状可以为矩形。即，过孔VH1在靠近端子扩展层RDL1一侧的开口的面积基本等于过孔VH1在靠近重布线层RDL2一侧的开口的面积。所以，在该实施例中，对过孔的轮廓要求较低，可以形成开口尺寸在10微米以下的过孔，有利于提高显示装置的PPI。
需要说明的是，根据电路逻辑设计需求，也可以增加走线层的层数，例如，还可以在重布线层RDL2远离衬底的一侧形成重布线层RDL3和RDL4等，相邻的两层走线层之间可以采用绝缘层隔离和绝缘。
这样，形成了包括各个芯片CP1、CP2、CP3、CP4以及端子扩展层的背板，然后，可以在该背板上形成包括TFT驱动电路的驱动元件。即，在该实施例中，采用chip first工艺形成所述显示装置。
图21是图20E的部分I的局部放大图。例如，参照图20E和图21，可以在重布线层RDL2远离衬底的一侧依次形成阻挡层BRL和缓冲层BFL。然后，可以在缓冲层BFL远离衬底的一侧形成TFT的膜层结构。例如，可以在缓冲层BFL远离衬底的一侧依次形成有源层、栅绝缘层GI1、导电层CDL1、栅绝缘层GI2、导电层CDL2、层间介电层IDL和导电层CDL3。例如，TFT驱动电路可以包括至少一个薄膜晶体管和至少一个存储电容器，薄膜晶体管(即TFT)的栅极以及存储电容器的一个电极可以位于导电层CDL1中，存储电容器的另一个电极可以位于导电层CDL2中，薄膜晶体管的源极和漏极可以位于导电层CDL3中。例如，多个第二走线RL3可以位于导电层CDL3中。第二走线RL3可以通过贯穿栅绝缘层GI1、栅绝缘层GI2和层间介电层IDL的过孔与第一走线RL2电连接。薄膜晶体管的源极和漏极可以通过贯穿栅绝缘层GI1、栅绝缘层GI2和层间介电层IDL的过孔与有源层的源极区和漏极区电连接。
例如，可以在导电层CDL3远离衬底的一侧形成平坦化层PLN2。
应该理解，在该实施例中，可以采用已知的TFT制备工艺来形成包括TFT驱动电 路的驱动元件，在此不再赘述。
需要说明的是，在本公开的实施例中，上述TFT驱动电路中包括的薄膜晶体管可以包括但不限于多晶硅TFT、低温多晶硅TFT、氧化物TFT等。
例如，如上所述，结合参照图17F至图17I，衬底SUB4可以通过粘性层AD3贴附在平坦化层PLN3远离衬底SUB2的表面上。通过激光解离、温度解离或者UV解离等方式将衬底SUB2与其上形成的器件分离。在各个芯片CP1、CP2、CP3、CP4远离衬底SUB4的一侧涂布保护层PTL。对保护层PTL执行构图工艺，以暴露各个芯片CP1、CP2、CP3、CP4靠近保护层PTL的表面。这样，保护层PTL可以保护例如扩展走线RL1的金属层，使得金属层可以不暴露于空气中，同时，使得各个芯片CP1、CP2、CP3、CP4的功能表面可以暴露出来，有利于实现各个芯片的功能。
图20F是根据本公开的一些实施例的显示装置的示意截面图。参照图20F、图20E和图21，根据本公开的一些实施例的半导体装置可以是显示装置，例如，该显示装置可以是μLED显示装置。它可以包括：衬底SUB4；设置在衬底SUB4上的粘性层AD3；设置在粘性层AD3远离衬底一侧的平坦化层PLN2；设置在平坦化层PLN2远离衬底一侧的导电层CDL3；设置在导电层CDL3远离衬底一侧的层间介电层IDL；设置在层间介电层IDL远离衬底一侧的导电层CDL2；设置在导电层CDL2远离衬底一侧的栅绝缘层GI2；设置在栅绝缘层GI2远离衬底一侧的导电层CDL1；设置在导电层CDL1远离衬底一侧的有源层ACT；设置在有源层ACT远离衬底一侧的缓冲层BFL；设置在缓冲层BFL远离衬底一侧的阻挡层BRL；设置在阻挡层BRL远离衬底一侧的重布线层RDL2；设置在重布线层RDL2远离衬底一侧的钝化层PVX2；设置在钝化层PVX2远离衬底一侧的平坦化层PLN1；设置在平坦化层PLN1远离衬底一侧的钝化层PVX1；设置在钝化层PVX1远离衬底一侧的端子扩展层RDL1；设置在端子扩展层RDL1远离衬底一侧的多个芯片CP1、CP2、CP3、CP4；和设置在芯片CP1、CP2、CP3、CP4远离衬底一侧的保护层PTL。
例如，TFT驱动电路可以包括至少一个薄膜晶体管和至少一个存储电容器，薄膜晶体管(即TFT)的栅极以及存储电容器的一个电极可以位于导电层CDL1中，存储电容器的另一个电极可以位于导电层CDL2中，薄膜晶体管的源极和漏极可以位于导电层CDL3中。
例如，多个扩展走线RL1可以位于端子扩展层RDL1中。多个第一走线RL2可以 位于重布线层RDL2中。多个第二走线RL3可以位于导电层CDL3中。芯片CP1、CP2、CP3、CP4中的每一个可以包括至少一个端子p1。各个芯片CP1、CP2、CP3、CP4的端子p1通过扩展走线RL1引出。多个第一走线RL2可以通过贯穿钝化层PVX1、平坦化层PLN1和钝化层PVX2的过孔分别与多个扩展走线RL1电连接。多个第二走线RL3可以通过贯穿栅绝缘层GI1、栅绝缘层GI2和层间介电层IDL的过孔分别与第一走线RL2电连接。薄膜晶体管的源极和漏极可以通过贯穿栅绝缘层GI1、栅绝缘层GI2和层间介电层IDL的过孔与有源层的源极区和漏极区电连接。这样，可以实现TFT驱动电路与芯片之间的电连接，以及实现多个芯片之间的电连接。
图22是根据本公开的一些实施例的显示装置的示意截面图，其中LED芯片和其他芯片位于不同的层中。图23是图22中的部分II的局部放大图。结合参照图22和图23，考虑到LED芯片与显示相关和传感相关的Si基芯片在工艺和性能(例如耐温性)上的差异性，LED芯片和其他芯片可以设置在TFT的不同侧。例如，LED芯片可以设置在薄膜晶体管靠近衬底SUB2的一侧，其他芯片可以设置在薄膜晶体管远离衬底SUB2的一侧。在该实施例中，位于上层的芯片CP1、CP2、CP4可以通过位于重布线层RDL3中的多个第二走线RL3与位于下层的LED芯片CP3电连接。
具体地，所述显示装置可以是μLED(即miniLED)显示装置，它可以包括：衬底SUB2；设置在衬底SUB2上的粘性层AD1；设置在粘性层AD1远离衬底一侧的LED芯片CP3；设置在LED芯片CP3远离衬底一侧的端子扩展层RDL1；设置在端子扩展层RDL1远离衬底一侧的钝化层PVX1；设置在钝化层PVX1远离衬底一侧的平坦化层PLN1；设置在平坦化层PLN1远离衬底一侧的钝化层PVX2；设置在钝化层PVX2远离衬底一侧的重布线层RDL2；设置在重布线层RDL2远离衬底一侧的阻挡层BRL和/或缓冲层BFL；设置在缓冲层BFL远离衬底一侧的有源层ACT；设置在有源层ACT远离衬底一侧的栅绝缘层GI1；设置在栅绝缘层GI1远离衬底一侧的导电层CDL1；设置在导电层CDL1远离衬底一侧的栅绝缘层GI2；设置在栅绝缘层GI2远离衬底一侧的导电层CDL2；设置在导电层CDL2远离衬底一侧的层间介电层IDL；设置在层间介电层IDL远离衬底一侧的导电层CDL3；设置在导电层CDL3远离衬底一侧的平坦化层PLN2；设置在平坦化层PLN2远离衬底一侧的粘性层AD2；设置在粘性层AD2远离衬底一侧的多个芯片CP1、CP2、CP4；设置在多个芯片CP1、CP2、CP4远离衬底一侧的重布线层RDL3；设置在重布线层RDL3远离衬底一侧的钝化层PVX3；设置 在钝化层PVX3远离衬底一侧的平坦化层PLN3。
例如，TFT驱动电路可以包括至少一个薄膜晶体管和至少一个存储电容器，薄膜晶体管(即TFT)的栅极以及存储电容器的一个电极可以位于导电层CDL1中，存储电容器的另一个电极可以位于导电层CDL2中，薄膜晶体管的源极和漏极可以位于导电层CDL3中。
例如，多个扩展走线RL1可以位于端子扩展层RDL1中。多个第一走线RL2可以位于重布线层RDL2中。多个第二走线RL3可以位于导电层CDL3中。多个第三走线RL4可以位于重布线层RDL3中。芯片CP1、CP2、CP3、CP4中的每一个可以包括至少一个端子p1。各个芯片CP1、CP2、CP4的端子p1可以通过第二走线RL3引出。芯片CP1、CP2、CP4的端子p1可以通过第二走线RL3电连接。至少一个第三走线RL4可以通过贯穿粘性层AD2和平坦化层PLN2的过孔与第二走线RL3、薄膜晶体管的源极和漏极中的至少一个电连接。多个第一走线RL2可以通过贯穿钝化层PVX1、平坦化层PLN1和钝化层PVX2的过孔分别与多个扩展走线RL1电连接。多个第二走线RL3可以通过贯穿栅绝缘层GI1、栅绝缘层GI2和层间介电层IDL的过孔分别与第一走线RL2电连接。薄膜晶体管的源极和漏极可以通过贯穿栅绝缘层GI1、栅绝缘层GI2和层间介电层IDL的过孔与有源层的源极区和漏极区电连接。这样，可以实现TFT驱动电路与芯片之间的电连接，以及实现多个芯片之间的电连接。
在该实施例中，芯片CP1、CP2、CP4与LED芯片CP3位于薄膜晶体管的相对侧。通过采用后对准工艺形成的多个端子扩展层，仍可以实现TFT驱动电路与芯片之间的电连接，以及实现多个芯片之间的电连接。
图24是根据本公开的一些实施例的显示装置的示意截面图，其中LED芯片和其他芯片位于不同的层中。参照图24，可以设置多个端子扩展层来实现位于上层的多个芯片CP1、CP2、CP4之间的电连接。例如，在钝化层PVX3和平坦化层PLN3之间可以设置端子扩展层RDL4和钝化层PVX4。钝化层PVX4设置在平坦化层PLN3远离衬底SUB4的一侧，端子扩展层RDL4设置在钝化层PVX4和钝化层PVX3之间。多个扩展走线RL5可以位于端子扩展层RDL4中。
例如，芯片CP1、CP2、CP4可以包括至少3个端子p1。位于重布线层RDL3中的第三走线RL4可以将位于两侧的端子p1引出。位于端子扩展层RDL4中的扩展走线RL5可以电连接一个芯片的位于中间的端子p1与另一个芯片的位于中间的端子p1。
通过设置多个端子扩展层，有利于实现位于上层的多个芯片CP1、CP2、CP4之间的电连接。应该理解，可以根据实际布线的需要，设置更多个端子扩展层来实现位于上层的多个芯片CP1、CP2、CP4之间的电连接。
图25A至图25F是根据本公开的示例性实施例的显示装置的制造方法的一些步骤被执行后形成的结构的示意截面图，其中所述显示装置的驱动元件包括TFT驱动电路，以及所述制造方法通过上述chip later工艺实现。
参照图25A，可以在衬底SUB2上形成TFT驱动电路。例如，在本公开的实施例中，上述TFT驱动电路中的薄膜晶体管可以包括但不限于多晶硅TFT、低温多晶硅TFT、氧化物TFT等。以多晶硅TFT工艺为例，可以在衬底SUB4上依次形成阻挡层BRL和缓冲层BFL。然后，可以在缓冲层BFL远离衬底的一侧形成TFT的膜层结构。例如，可以在缓冲层BFL远离衬底的一侧依次形成有源层ACT、栅绝缘层GI1、导电层CDL1、栅绝缘层GI2、导电层CDL2、层间介电层IDL和导电层CDL3。例如，TFT驱动电路可以包括至少一个薄膜晶体管和至少一个存储电容器，薄膜晶体管(即TFT)的栅极以及存储电容器的一个电极可以位于导电层CDL1中，存储电容器的另一个电极可以位于导电层CDL2中，薄膜晶体管的源极和漏极可以位于导电层CDL3中。例如，多个第二走线RL3可以位于导电层CDL3中。薄膜晶体管的源极和漏极可以通过贯穿栅绝缘层GI1、栅绝缘层GI2和层间介电层IDL的过孔与有源层的源极区和漏极区电连接。
例如，可以在导电层CDL3远离衬底的一侧形成平坦化层PLN1，在平坦化层PLN1远离衬底的一侧形成导电层CDL4。例如，多个第三走线RL4可以位于导电层CDL4中。多个第三走线RL4可以分别通过贯穿平坦化层PLN1的过孔与多个第二走线RL3以及薄膜晶体管的源极和漏极电连接。
应该理解，在该实施例中，可以采用已知的TFT制备工艺来形成包括TFT驱动电路的驱动元件，在此不再赘述。
这样，在该实施例中，先在衬底SUB4上形成TFT驱动电路，然后再在形成有TFT驱动电路的背板上形成各个芯片以及至少一个端子扩展层，即，采用chip later工艺形成所述显示装置。
参照图25B和图25C，在导电层CDL4远离衬底的一侧形成粘性层AD2。然后，将多个芯片CP通过SMT或者巨量转移工艺转移至衬底SUB4上，并通过粘性层AD2 固定于衬底SUB4上。每个芯片CP可以包括至少两个端子p1，在图示的实施例中，每个芯片CP的端子p1朝上，即朝向芯片远离衬底SUB4的一侧。
例如，所述多个芯片CP可以包括但不限于LED芯片、驱动芯片、存储芯片、控制芯片、数模转换芯片、信息处理芯片、传感器芯片等。例如，所述LED芯片可以为去除蓝宝石衬底的LED芯片，所述驱动芯片、存储芯片、控制芯片、数模转换芯片、信息处理芯片、传感器芯片可以为Si基芯片，该Si基芯片可以为无封装结构的裸芯片。在图25C的实施例中，示意性示出了4个芯片，为了方便描述，将4个芯片分别称为芯片CP1、CP2、CP3和CP4，例如，芯片CP1可以是控制芯片，芯片CP2可以是存储芯片，芯片CP3可以是LED芯片，芯片CP4可以是传感器芯片。应该理解，本公开的实施例不局限于图25C所示的布置方式。
例如，衬底SUB4可以是玻璃衬底、聚酰亚胺(即PI)衬底或石英衬底。
例如，粘性层AD2可以包括但不限于热敏胶、激光固化胶、光刻胶、UV固化胶等胶材。
参照图25D，可以采用构图工艺在粘性层AD2中形成多个过孔VH2，以暴露位于导电层CDL4的第三走线RL4的至少一部分。例如，此处的构图工艺可以采用已知的光刻工艺，包括光刻胶涂覆、曝光、显影和刻蚀等步骤，并且在曝光的过程中可以使用掩模板。
参照图25E，对设置有所述芯片CP1、CP2、CP3、CP4的衬底(可以称为背板)进行拍照，并采用图像识别技术确定设置在所述背板上的各个芯片CP1、CP2、CP3、CP4的端子p1的坐标和面积，生成端子区(即pad区)的图形文件。接着，在整个背板上沉积金属层，在金属层上涂布光刻胶，并根据上述图形文件通过数字直写或者数字曝光机图案化光刻胶。然后，根据图案化的光刻胶，对金属层进行刻蚀，以形成端子扩展层RDL1。在该端子扩展层RDL1中形成有多个扩展走线RL1，该多个扩展走线RL1可以分别与各个芯片CP1、CP2、CP3、CP4的端子p1电连接，以将各个端子p1引出。即，通过后对准工艺，在端子扩展层RDL1中形成用于电连接各个芯片的扩展走线RL1。
例如，至少一个扩展走线RL1可以通过位于导电层CDL4中的第三走线RL4与TFT驱动电路电连接，例如，与薄膜晶体管的源极或漏极电连接。至少一个扩展走线RL1还可以电连接芯片CP1、CP2、CP3、CP4中的至少两个。以此方式，可以实现 TFT驱动电路与芯片之间的电连接，以及实现多个芯片之间的电连接。
参照图25F，可以在端子扩展层RDL1远离衬底的一侧依次形成钝化层PVX1和平坦化层PLN2。
需要说明的是，根据电路逻辑设计需求，也可以增加走线层的层数，例如，还可以在端子扩展层RDL1远离衬底的一侧形成重布线层RDL2和RDL3等，相邻的两层走线层之间可以采用绝缘层隔离和绝缘。
参照图25F，根据本公开的一些实施例的半导体装置可以是显示装置，例如，该显示装置可以是μLED显示装置。它可以包括：衬底SUB4；设置在衬底SUB4上的阻挡层BRL；设置在阻挡层BRL远离衬底一侧的缓冲层BFL；设置在缓冲层BFL远离衬底一侧的有源层ACT；设置在有源层ACT远离衬底一侧的栅绝缘层GI1；设置在栅绝缘层GI1远离衬底一侧的导电层CDL1；设置在导电层CDL1远离衬底一侧的栅绝缘层GI2；设置在栅绝缘层GI2远离衬底一侧的导电层CDL2；设置在导电层CDL2远离衬底一侧的层间介电层IDL；设置在层间介电层IDL远离衬底一侧的导电层CDL3；设置在导电层CDL3远离衬底一侧的平坦化层PLN1；设置在平坦化层PLN1远离衬底一侧的导电层CDL4；设置在导电层CDL4远离衬底一侧的粘性层AD2；设置在粘性层AD2远离衬底一侧的多个芯片；设置在多个芯片远离衬底一侧的端子扩展层RDL1；设置在端子扩展层RDL1远离衬底一侧的钝化层PVX1；和设置在钝化层PVX1远离衬底一侧的平坦化层PLN2。
例如，TFT驱动电路可以包括至少一个薄膜晶体管和至少一个存储电容器，薄膜晶体管(即TFT)的栅极以及存储电容器的一个电极可以位于导电层CDL1中，存储电容器的另一个电极可以位于导电层CDL2中，薄膜晶体管的源极和漏极可以位于导电层CDL3中。
例如，多个扩展走线RL1可以位于端子扩展层RDL1中。芯片CP1、CP2、CP3、CP4中的每一个可以包括至少一个端子p1。各个芯片CP1、CP2、CP3、CP4的端子p1通过扩展走线RL1引出。
多个第二走线RL3可以位于导电层CDL3中。薄膜晶体管的源极和漏极可以通过贯穿栅绝缘层GI1、栅绝缘层GI2和层间介电层IDL的过孔与有源层的源极区和漏极区电连接。多个第三走线RL4可以位于导电层CDL4中。多个第三走线RL4可以分别通过贯穿平坦化层PLN1的过孔与多个第二走线RL3以及薄膜晶体管的源极和漏极电 连接。
例如，至少一个扩展走线RL1可以通过位于导电层CDL4中的第三走线RL4与TFT驱动电路电连接，例如，与薄膜晶体管的源极或漏极电连接。至少一个扩展走线RL1还可以电连接芯片CP1、CP2、CP3、CP4中的至少两个。以此方式，可以实现TFT驱动电路与芯片之间的电连接，以及实现多个芯片之间的电连接。
在上述实施例中，薄膜晶体管为顶栅型薄膜晶体管，应该理解，本公开的实施例不局限于此。例如，所述薄膜晶体管也可以为底栅型薄膜晶体管，例如采用背沟道刻蚀型结构(即BCE型TFT)。
图27是根据本公开的一些实施例的显示装置的示意截面图，其中薄膜晶体管为底栅型薄膜晶体管。参照图27，在缓冲层BFL远离衬底的一侧形成TFT的膜层结构的过程中，可以先制备栅极材料层CDL1，再形成栅绝缘层GI1，然后形成有源层ACT。例如，所述栅极材料层CDL1可以包含Mo/Al/Mo或Mo/Cu等材料，厚度可以为3000～6000埃。所述栅绝缘层GI1可以包含氮化硅或氧化硅，厚度可以为2000～5000埃。所述有源层ACT可以包含IGZO、IGTO、IZO等氧化物半导体材料，厚度可以为300～1000埃。
下面，将结合附图详细描述根据本公开实施例的半导体装置在传感器场景中的应用。需要说明的是，在下面的说明中，将主要描述应用于传感器场景中的半导体装置的结构，其制造工艺可以参照上文的描述，在此不再赘述。
在本公开的实施例中，通过对具有集成功能的芯片进行功能拆分，变为多个微型芯片。在传感器应用场景中，可以在前端部分多设置一些芯片，提高采集信息的能力，而且这些前端的微型在后端部分(例如控制部分)可以共用控制芯片，通过芯片拆分和部分功能增强，有利于实现传感器件功能优化。
例如，随着显示屏的巨幕化、3D显示、虚拟现实等需求不断增加，对物体的空间探测技术的需求也不断增加，例如，需要在多个深度和多个位置探测物体，以实现集成多区域空间探测的智慧显示屏。例如，在现有的空间探测技术中，通常采用外模组方案。即，用于空间探测的传感器通常放置在显示器上边框中间位置处或者显示器前的桌面上，应用空间有限，存在识别盲区。对于现有的2D显示，人站在最佳识别范围里可以实现手势的操控。但是，对于3D显示，显示图像多层次、多位置分布，用户希望的体验是在不同位置触摸虚拟物体，所以，用于空间探测的传感器与显示元件 集成的器件方案逐渐成为研发人员关注的重要课题之一。
在下面的实施例中，以声学传感器为例，来描述根据本公开实施例的用于空间探测的传感器与显示元件集成的器件方案。
在本公开的实施例中，可以对声学传感器进行功能拆分，形成多个微型芯片。例如，所述声学传感器可以至少包括信号采集芯片和信号处理芯片。图28A和图28分别是根据本公开的一些实施例的声学传感器的示意方框图，图28C示意性示出了根据本公开的一些实施例的声学传感器在显示器中的布置方式。参照图28A和图28B，通过将声学传感器进行功能拆分，可以形成多个微型芯片。例如，一个声学传感器中可以设置多个信号采集芯片SNC1，多个信号采集芯片SNC1可以与至少一个信号处理芯片电连接。多个信号采集芯片SNC1可以串联，以增大采集到的信号的信噪比，从而增加信号探测灵敏度，实现远距离探测。
例如，一个信号处理芯片可以包括LC滤波电路、放大电路、数模转换电路和控制电路。LC滤波电路可以对信号采集芯片采集的信号进行滤波处理。放大电路可以对经滤波的信号进行放大、整流等处理。数模转换电路可以对经放大的信号进行数模转换。控制电路可以接收经数模转换的信号并且基于该信号执行相应的控制功能。
可选地，所述信号处理芯片也可以进行功能拆分，使得一个信号处理芯片可以包括多个微型芯片，例如，LC滤波电路、放大电路、数模转换电路和控制电路可以分别形成独立的微型芯片，以便可以灵活地布置各个微型芯片。即，所述声学传感器可以包括LC滤波芯片SNP1、放大器芯片SNP2、数模转换芯片SNP3和控制芯片SNP4。
例如，多个信号采集芯片SNC1可以彼此串联，然后电连接至LC滤波芯片SNP1、放大器芯片SNP2、数模转换芯片SNP3和控制芯片SNP4，多个信号采集芯片SNC1、LC滤波芯片SNP1、放大器芯片SNP2、数模转换芯片SNP3和控制芯片SNP4可以排列成直线，如图28A所示。这样，具有这样排列方式的声学传感器SR1可以设置在显示器的上边框中间位置处。多个信号采集芯片SNC1、LC滤波芯片SNP1、放大器芯片SNP2、数模转换芯片SNP3和控制芯片SNP4可以排列成矩形，如图28B所示。这样，具有这样排列方式的声学传感器SR2可以设置在显示器的显示区中。在本公开的实施例中，所述传感器可以放置在显示器的显示区中，也可以放置在显示器的边框上。而且，由于将所述传感器拆分成多个微型芯片，所以可以灵活布置所述传感器，例如，可以以一排、一圈、蛇形、矩形区域、圆形区域、椭圆形区域等方式布置所述传感器； 可以在空白区密排多个微型芯片，也可以在像素之间的间隙插空放置多个微型芯片。也就是说，根据本公开实施例的传感器可以灵活布置在显示器上，提高了器件性能和安装灵活度，从而解决了现有器件探测局限和只能以外模组方式放置的问题。
在本公开的实施例中，所述传感器可以为Si基传感器。例如，所述信号采集芯片可以包括换能器，用于采集声学信号并将其转换成电信号。图29是根据本公开的一些实施例的集成有传感器的显示装置的示意截面图，其中所述传感器为Si基传感器。参照图29，所述显示装置可以包括衬底SUB5；设置在衬底SUB5上的驱动元件；设置在所述驱动元件远离衬底一侧的平坦化层PLN1；设置在所述平坦化层PLN1远离衬底一侧的导电层CDL4；设置在导电层CDL4远离衬底一侧的平坦化层PLN2；设置在平坦化层PLN2远离衬底一侧的钝化层PVX1；设置在所述钝化层PVX1远离衬底一侧的端子扩展层RDL1；设置在端子扩展层RDL1远离衬底一侧的钝化层PVX2；和设置在钝化层PVX2远离衬底一侧的多个芯片。例如，所述多个芯片可以是所述传感器的信号采集芯片SNC1、LC滤波芯片SNP1、放大器芯片SNP2、数模转换芯片SNP3和控制芯片SNP4。
多个扩展走线RL1可以位于端子扩展层RDL1中。多个信号采集芯片SNC1可以通过多个扩展走线RL1串联，多个扩展走线RL1还可以将串联的多个信号采集芯片SNC1、LC滤波芯片SNP1、放大器芯片SNP2、数模转换芯片SNP3和控制芯片SNP4依次电连接。
在该实施例中，所述驱动元件可以包括上述的TFT驱动电路，具体膜层结构可以参照上文的描述，在此不再赘述。
图30示意性示出了在根据本公开的实施例的传感器中输出电压的增大倍数与串联的换能器的个数的关系。参照图30，在本公开的实施例中，将换能器和滤波放大等其他信号处理电路拆分，并将多个换能器进行串联以增加接收信号量，如图30所示，再经过滤波放大等电路。这样，可增大器件灵敏度，实现更远距离的探测。另外，在本公开的实施例中，信号处理芯片可以与换能器紧密放置，减少RC负载和噪音，增加信号探测灵敏度，从而有利于实现更远距离的探测。
需要说明的是，在图29所示的实施例中，先制作TFT背板和端子扩展层，再键合芯片。但是，本公开的实施例不局限于此，各个芯片可以并排/堆叠键合、芯片面朝下或芯片面朝上(即face down/up)、芯片优先或RDL优先(即die first/RDL first)。衬 底SUB5的类型包括但不限于玻璃衬底、PCB、FPC等。
图31是根据本公开的一些实施例的集成有传感器的显示装置的示意截面图，其中所述传感器为包含压电薄膜的压电传感器。参照图31，在该实施例中，在包括TFT驱动电路的背板上制作多个压电传感单元，所述多个压电传感单元串联，并键合信号处理芯片。
需要说明的是，在该实施例中，以“压电薄膜”为了进行了说明，本公开的实施例不局限于此，例如，根据本公开实施例的半导体装置包括的传感芯片可以包括其他类型的传感器，该传感器可以包括其他类型的功能薄膜。即，在本文中，表述“功能薄膜”包括但不限于压电薄膜。
具体地，所述显示装置可以包括衬底SUB5；设置在衬底SUB5上的驱动元件；设置在所述驱动元件远离衬底一侧的平坦化层PLN1；设置在所述平坦化层PLN1远离衬底一侧的导电层CDL4；设置在导电层CDL4远离衬底一侧的压电薄膜PVL；和设置在压电薄膜PVL远离衬底一侧的导电层CDL5。
所述压电传感单元包括第一电极E1、第二电极E2和夹设在第一电极E1与第二电极E2之间的压电薄膜PVL。例如，所述压电薄膜PVL可以为PVDF压电薄膜。多个第一电极E1位于导电层CDL4中，多个第二电极E2位于导电层CDL5中。每个压电传感单元的第一电极E1和第二电极E2相对且间隔地设置。
图32是图31中的部分III的局部放大图。结合参照图31和图32，在相邻的2个压电传感单元中，一个压电传感单元的第一电极E1通过过孔或凹槽与另一个压电传感单元的第二电极E2电连接。以此方式，可以实现多个压电传感单元的串联。
在形成多个压电传感单元的过程中，可以先沉积一层导电层，通过构图工艺形成多个第一电极E1；然后，旋涂PVDF压电薄膜层，并固化和干刻PVDF压电薄膜层，以形成图案化的PVDF压电薄膜；然后，可以沉积一层导电层，通过构图工艺形成多个第二电极E2。例如，PVDF压电薄膜层的厚度较厚，例如为数微米级，所以，可以在压电薄膜层上制作一层平坦层，然后再形成第二电极E2。
所述信号处理芯片可以包括至少两个端子p1。例如，端子p1可以朝下，一个端子p1与邻近的一个压电传感单元的第一电极E1电连接，另一个端子p1可以与位于导电层CDL4中的扩展走线电连接。
图33A至图33C是分别示意根据本公开的一些实施例的集成有传感器的显示装置 的制造方法的一些步骤被执行后形成的结构的示意截面图，其中所述传感器为包含压电薄膜的压电传感器。
参照图33A，可以单独制作出压电传感器，然后通过切割的方式形成多个压电传感单元。
参照图33B，可以单独制作出包括TFT驱动电路的背板，例如，该背板包括衬底SUB5；设置在衬底SUB5上的驱动元件；和设置在所述驱动元件远离衬底一侧的平坦化层PLN1。例如，可以在平坦化层PLN1远离衬底的一侧形成导电层CDL4。
参照图33C，将多个压电传感单元和芯片置于背板上。例如，至少2个导电部形成在导电层CDL4中，且至少2个导电部间隔设置。2个相邻的压电传感单元以极性相反的方式放置在同一个导电部上。在放置于同一个导电部上的2个压电传感单元中，一个压电传感单元的第一电极E1和另一个压电传感单元的第二电极E2与导电层CDL4电接触。
继续参照图33C，在多个压电传感单元和芯片远离衬底一侧的平坦化层PLN2，并且在平坦化层PLN2远离衬底一侧的重布线层RDL2。多个第一走线RL2形成于重布线层RDL2中。在放置于不同导电部上的2个压电传感单元中，一个压电传感单元的第二电极E2通过一个第一走线RL2与另一个压电传感单元的第一电极E1电连接。以此方式，可以实现多个压电传感单元的串联。
所述信号处理芯片可以包括至少两个端子p1。例如，端子p1可以朝上，一个端子p1通过一个第一走线RL2与邻近的一个压电传感单元的第二电极E2电连接，另一个端子p1可以与位于重布线层RDL2中的扩展走线电连接。
图34是根据本公开的一些实施例的集成有传感器的显示装置的示意截面图。参照图34，多个压电传感单元可以以上下叠置键合的方式设置。例如，一个压电传感单元放置在上述导电部上，其第一电极E1与导电部接触，其第二电极E2朝上；另一个压电传感单元防止在该压电传感单元上，该另一个压电传感单元的第一电极E1与上述压电传感单元的第二电极E2接触。以此方式，也可以实现多个压电传感单元的串联。
在该实施例中，通过单独制作压电传感器，可以解决可能存在的产线不兼容问题，且避免了在大厚度的压电薄膜层中形成过孔，解决了奇偶极化难题，降低了压电薄膜的工艺要求。
在上面的各个实施例中，例如TFT驱动元件的驱动电路和各个芯片均设置在同一 个衬底上，并以chip first和chip later工艺为例进行了详细说明。但是，本公开的实施例不局限于此，例如，例如TFT驱动元件的驱动电路和各个芯片可以制作在不同的衬底上，然后通过对盒的方式形成所述半导体装置。
图35A至图35E是根据本公开的示例性实施例的半导体装置(例如显示装置)的制造方法的一些步骤被执行后形成的结构的示意截面图。
参照图35A，在衬底SUB7上涂覆或者粘贴粘性层AD1。
参照图35B，将各个芯片(例如LED芯片CP3和功能元件CP4)通过SMT或者巨量转移工艺转移至衬底SUB7上，并通过粘性层AD1固定于衬底上。
例如，各个芯片可以均位于粘性层AD1上，各个芯片的端子p1可以朝上，即位于芯片远离衬底的一侧。
对设置有所述LED芯片CP3和功能元件CP4的衬底(可以称为背板)进行拍照，并采用图像识别技术确定设置在所述背板上的各个LED芯片CP3和功能元件CP4的端子p1的坐标和面积，生成端子区(即pad区)的图形文件。接着，在整个背板上沉积金属层，在金属层上涂布光刻胶，并根据上述图形文件通过数字直写或者数字曝光机图案化光刻胶。然后，根据图案化的光刻胶，对金属层进行刻蚀，以形成端子扩展层RDL1。在该端子扩展层RDL1中形成有多个扩展走线RL1，该多个扩展走线RL1可以分别与各个LED芯片CP3和功能元件CP4的端子p1电连接，以将各个端子p1引出。即，通过后对准工艺，在端子扩展层RDL1中形成用于电连接各个芯片的扩展走线RL1。
参照图35C，在端子扩展层RDL1远离衬底的一侧涂覆平坦化层PLN1。
例如，平坦化层PLN1可以包括树脂类材料，用于填平各个LED芯片CP3和功能元件CP4之间的段差，实现平坦化。
可选地，可以在平坦化层PLN1远离衬底的一侧制备钝化层PVX2。例如，钝化层PVX2可以包括氮化硅等材料，用于隔绝平坦化层PLN1中的水汽，防止平坦化层PLN1中的水汽腐蚀上层的端子扩展层。
继续参照图35C，可以形成贯穿平坦化层PLN1和钝化层PVX2的过孔，以暴露各个扩展走线RL1的至少一部分。然后，在钝化层PVX2远离衬底的一侧沉积金属层，通过包括涂覆光刻胶、曝光、显影、刻蚀等步骤的构图工艺，形成重布线层RDL2。例如，在该重布线层RDL2中形成有多个第一走线RL2。该多个第一走线RL2可以分 别通过上述过孔与多个扩展走线RL1电连接，以进一步将各个端子p1引出。
可选地，参照图35C，在完成上述后对准工艺后，根据线路互连的需求，可以制备重布线层RDL3。
例如，可以在重布线层RDL2远离衬底的一侧形成覆盖层PLN2。然后，在覆盖层PLN2远离衬底的一侧形成重布线层RDL3。
例如，重布线层RDL3可以通过传统的光刻工艺制备，以在重布线层RDL3中形成用于电连接各个芯片的第二走线RL3。本公开的实施例不局限于此，重布线层RDL3也可以通过后对准工艺制备。
例如，根据扩展走线需求，还可以制备第四层布线、第五层布线等，本公开的实施例在此不做特别限制。
参照图35D，制备包括TFT驱动元件的背板。例如，所述背板可以包括衬底SUB8；设置在衬底SUB8上的驱动元件；和设置在所述驱动元件远离衬底一侧的多个端子p2。
参照图35E，对盒所述背板和设置有所述芯片的衬底SUB7。例如，使所述背板上的多个端子p2与位于重布线层RDL3中的多个第二走线RL3分别电连接，以实现驱动元件与芯片的电连接。
如上所述，在本公开的实施例中，可以先对芯片进行一定精度的排布，然后通过后对准工艺对芯片及端子(即pad)的位置、面积、形貌进行识别与分析，并结合光刻工艺，实现高精度自动布线与芯片键合。通过所述后对准工艺，可以提升微型芯片的键合精度，有利于芯片与其他电路的集成。而且，由于设置有所述后对准工艺，所以对芯片转移工艺的精度的要求可以降低，即有利于降低芯片转移工艺的难度。此外，自动布线工艺可对大面积内转移的巨量芯片同时进行高精度键合，提升了键合效率，更适合大批量、大面积的芯片键合。
图36A示意性示出了在根据本公开的一些实施例的后对准工艺的过程中形成多个扩展走线的俯视图。在图36A示出的实施例中，以显示装置为例，示出了显示基板的局部俯视图。参照图36A，衬底SUB9上设置有多个像素PX，例如，所述多个像素PX可以包括但不限于，用于实现显示功能的显示像素，用于实现探测功能的传感器像素等。所述显示像素包括但不限于OLED、microLED、miniLED、LCD等显示元件。
衬底SUB9上还设置有多个芯片CP。例如，多个芯片CP可以通过SMT或巨量转移工艺转移至衬底SUB9上。然后，可以使用所述后对准工艺形成多个扩展走线RL1， 以电连接多个芯片CP。具体地，对设置有所述芯片CP的衬底(可以称为背板)进行拍照，并采用图像识别技术确定设置在所述背板上的各个芯片CP的端子p11的坐标、面积和形貌等参数，生成端子区(即pad区)的图形文件。例如，图36A示意性示出了各个芯片CP对应的拍照区域PTA。根据各个芯片CP的端子p11相对于衬底SUB9上的原点的坐标，可以确定出各个芯片CP的端子p11的坐标；并且，采用图像识别技术可以确定各个芯片CP的端子p11的面积和形貌。
此外，在对图片进行识别和分析的过程中，可对背板上的可视化图形进行不良判断和检测，以鉴别背板上存在的断路的连线，利用后对准工艺的金属扩展走线对背板上不良点进行修复，并筛选转移后由于偏移过大而无法连接的芯片。例如，可以采用图像识别技术确定各个不良点的坐标信息。
接着，在整个背板上沉积金属层，在金属层上涂布光刻胶，并根据上述图形文件通过数字直写或者数字曝光机图案化光刻胶。然后，根据图案化的光刻胶，对金属层进行刻蚀，以形成端子扩展层RDL1。在该端子扩展层RDL1中形成有多个扩展走线RL1，该多个扩展走线RL1可以通过过孔分别与各个芯片CP的端子p11电连接，以将各个端子p11引出。即，通过后对准工艺，在端子扩展层RDL1中形成用于电连接各个芯片的扩展走线RL1。
例如，参照图36A，软件可以根据各个芯片CP的端子p11的坐标并结合每个衬底上的芯片的实际转移情况确定出自动布线的路径。例如，在确定自动布线的路径的过程中，可以考虑避开显示像素等功能区域，使得布线路径分布在像素之间的间隙区域，从而电连接各个芯片。
例如，可以根据各个不良点的坐标信息，通过数字直写或者数字曝光机图案化光刻胶。然后，根据图案化的光刻胶，对金属层进行刻蚀，以形成端子扩展层RDL1。在该端子扩展层RDL1中形成有多个扩展走线RL1，该多个扩展走线RL1可以通过过孔分别与各个不良点电连接，以修复各个不良点。
图39A、图39B和图39C分别示意性示出了后对准工艺中形成的拍照区域。参照图39A，背板上的各个芯片可以为整屏密排的芯片，例如，显示装置中的microLED芯片。在这种情况下，显微镜以整面背板的一个位置标定标记(MARK)为原点，按固定的步进距离拍照后平移到下一拍照区域，实际拍照次数与背板大小和芯片密度有关。一个拍照区域中可以设置有一个或多个芯片。参照图39B，各个芯片在背板上不 是密排的，即芯片的个数较少。在这种情况下，拍照区域可以为围绕芯片的理想位置的区域，一个拍照区域的覆盖范围可以大于芯片可能偏移的范围，保证芯片在拍照区域中。背板上可制作标定标记(MARK)为原点，用来确定芯片转移后的实际坐标。参照图39C，可在背板上制作有规律排布的位置标定标记(MARK1)，每一张单图中的位置标定标记(MARK1)与背板整体绝对坐标标定标记(MARK0)之间的位置是相对固定的，用于将每一张拍照的单图中的芯片位置换算成相对于整个背板的绝对位置坐标。当一次拍照区域中有多个芯片且排布密度较大时，为防止机台移动误差导致相邻图像无法完全密接，以及避免单张图像由于镜头成像方式导致的边缘图像畸变问题，可以使相邻的拍照区域之间存在重叠拍照区域，保证所有芯片的图像被完整拍摄。由于每一张单图中均有位置标定标记(MARK1)，因此在对芯片坐标进行图像识别时无需做图像拼接，仅需通过图像识别后计算单图中芯片的位置相对于单图中位置标定标记(MARK1)的坐标，并通过单图中位置标定标记(MARK1)和背板整体绝对坐标标定标记(MARK0)之间的位置关系做换算，得到单图中芯片的位置相对于背板整体绝对坐标标定标记(MARK0)的绝对坐标。
图36B和图36C分别示意性示出了在根据本公开的一些实施例的后对准工艺的过程中形成多个扩展走线的俯视图。图37A和图37B是沿图36B中的线AA’截取的截面图。图38示意性示出了两个芯片之间的布线的局部放大图。
参照图36B和图38，在本公开的实施例中，在衬底SUB9上可以设置多个固定连接部12。例如，各个芯片CP所在的位置附近可以设置至少两个固定连接部12。用于电连接两个芯片CP的扩展走线可以至少包括连接一个芯片的端子p1与该芯片邻近的一个固定连接部12的第一走线段RL11、用于连接两个芯片之间的两个固定连接部12的第二走线段RL12和用于连接另一个芯片的端子p1与该另一个芯片邻近的一个固定连接部12的第三走线段RL13。
需要说明的是，在该实施例中，为了描述方便，使用了第一走线段、第二走线段和第三走线段这样的表述，应该理解，所述第一走线段和所述第三走线段都是用于电连接芯片的一个端子和固定连接部的，所以它们可以都称为第一走线段；所述第二走线段是用于电连接两个固定连接部的。也就是说，在本文中，也可以使用第一走线段、第二走线段这样的表述来区分一个扩展走线的不同部分。
例如，各个芯片CP可以具有可以根据图片区分不同pad的标志，各个芯片的实 际坐标由拍照后的图像经识别分析后计算确定。芯片上的标志可以包括但不限于芯片上pad的形貌、形状、尺寸、方向等特征。可选地，可以制作专门的特征来区分不同芯片的pad。
例如，上述第二走线段RL12可利用常规的光刻工艺制作在背板上，上述后对准工艺仅形成第一走线段RL11和第三走线段RL13。参照图37A，第一走线段RL11和第三走线段RL13可以位于端子扩展层RDL1中，第二走线段RL12位于与端子扩展层RDL1不同的层中。
例如，上述第一走线段RL11、第二走线段RL12和第三走线段RL13均可以通过后对准工艺形成。参照图37B，上述第一走线段RL11、第二走线段RL12和第三走线段RL13可以位于端子扩展层RDL1中。即，上述第一走线段RL11、第二走线段RL12和第三走线段RL13可以为同层金属扩展走线。
例如，固定连接部12与芯片的理想转移位置的中心之间的间距可以大于芯片转移过程中可能发生的最大偏移量。例如，在芯片转移过程中可能发生的最大偏移量为约10微米的情况下，固定连接部12与芯片的理想转移位置的中心之间的间距大于10微米。
应该理解，各个固定连接部12之间的布线的路径是相对固定的，例如，对于同一产品而言，各个固定连接部12之间的布线的路径可以设置为相同，即第二走线段RL12的布线路径相同。这样，在计算确定布线路径时，不需要计算各个第二走线段RL12的布线路径，从而可以减小自动布线的复杂度。在确定布线路径时，可以根据转移后各个芯片的实际位置，精确计算各个芯片的端子与固定连接部之间的布线路径，即，根据芯片的实际位置对布线路径进行局部更新，有利于提高自动布线的精度和效率。
结合参照图4、图36B和图36C，至少一个第二走线段RL12沿第一方向或第二方向延伸；以及在通过包括沿第一方向或第二方向延伸的第二走线段的扩展走线电连接的两个芯片中，一个芯片在所述第一方向上的相对位置与另一个芯片在所述第一方向上的相对位置不相同。
例如，在通过包括至少一个第二走线段的扩展走线电连接的两个芯片中，至少一个芯片相对于所述第二走线段RL12的延长线倾斜。例如，图36C中所示的4个芯片。
例如，在通过包括至少一个第二走线段的扩展走线电连接的两个芯片中，一个芯片相对于所述第二走线段RL12的延长线的朝向与另一个芯片相对于所述第二走线段 RL12的延长线的朝向不相同。例如，图36B中所述的左侧的两个芯片。
例如，在通过包括至少一个第二走线段的扩展走线电连接的两个芯片中，每一个芯片包括的多个端子至少包括第一端子(例如图36B、图36C中所示的芯片的左侧端子)和第二端子(例如图36B、图36C中所示的芯片的右侧端子)。用于电连接两个芯片的第一端子的扩展走线包括的第二走线段RL12和用于电连接两个芯片的第二端子的扩展走线包括的第二走线段RL12彼此平行，和/或，用于电连接两个芯片的第一端子的扩展走线包括的第二走线段RL12和用于电连接两个芯片的第二端子的扩展走线包括的第二走线段RL12的长度基本相等。
例如，至少一个第一走线段RL11、RL13和与它相邻且电连接的第二走线段RL12之间具有夹角，所述夹角大于0°小于180°。
例如，在与同一个第二走线段RL12相邻且电连接的两个第一走线段RL11、RL13中，一个第一走线段RL113和与它相邻且电连接的第二走线段RL12之间的夹角不同于另一个第一走线段RL13和与它相邻且电连接的第二走线段RL12之间的夹角。
例如，在与同一个芯片的第一端子和第二端子电连接的两个第一走线段中，一个第一走线段RL11和与它相邻且电连接的第二走线段RL12之间的夹角不同于另一个第一走线段RL11和与它相邻且电连接的第二走线段RL12之间的夹角。
例如，各个固定连接部12之间的第二走线段RL12可以根据产品的共同特征，例如转移精度偏差或芯片连接方式等，设置为不同产品可共用的总线；或与芯片或背板上的选通电路电连接，使其作为具有选通功能的智能总线。
结合参照图36B和图36C，对于相同的产品，在转移工艺的精度的影响下，各个芯片的实际位置可能不同。由于设置有固定连接部12，这样，在各个固定连接部12之间的第二走线段RL12的路径可以是相同的。在计算实际的布线路径时，只需要布局更新上述第一走线段RL11和第三走线段RL13的路径。
在本公开的实施例中，所述半导体装置可以为显示装置。所述显示装置的驱动元件可以设置为驱动芯片的形式。图40A至图40C分别示意性示出了根据本公开实施例的显示装置的驱动芯片和各个像素的布置方式。
例如，用作驱动元件的驱动芯片CP1可以与像素对应的部分进行电连接，以使得所述驱动芯片CP1可以驱动多个像素PX。也就是说，在本公开的实施例中，无需在背板上设置驱动电路。例如，所述多个像素PX可以包括但不限于，用于实现显示功 能的显示像素，用于实现探测功能的传感器像素等。所述显示像素包括但不限于OLED、microLED、miniLED、LCD等显示元件。
参照图40A，一个芯片CP可以包括至少2个端子p1，例如4个端子p1。围绕一个芯片CP可以设置至少2个像素PX，例如4个像素PX。一个芯片CP的4个端子p1分别通过扩展走线RL7与围绕它的4个像素PX电连接。例如，如果像素PX为显示像素，那么一个芯片CP的1个端子p1通过扩展走线RL7与该显示像素的阳极电连接，该芯片CP可以给该显示像素供应驱动信号。如果像素PX为传感器像素，那么一个芯片CP的1个端子p1通过扩展走线RL7与该传感器像素的一个电极电连接，该芯片CP可以从该传感器像素接收感应信号并进行一定的处理(例如滤波、放大)。
例如，多个芯片CP可以通过扩展走线RL8与总控芯片CP10电连接。
例如，对应显示像素，芯片CP可以为驱动芯片；对应传感器像素，芯片CP可以为功放芯片，总控芯片CP10可以为ADC芯片。
在本公开的实施例中，扩展走线RL7和扩展走线RL8可以位于相同的端子扩展层中，或者，扩展走线RL7和扩展走线RL8可以位于不同的端子扩展层中。例如，可以通过上述后对准工艺形成扩展走线RL7和扩展走线RL8。
各个扩展走线RL7和RL8的布线方式可以根据芯片之间的间距确定。如果芯片之间的间距离较近，例如所述间距为多个像素大小的间距，则可以根据芯片的实际坐标采用直接扩展走线的方式。如果芯片之间的间距较远，且相连路径较为复杂，则可采用上述实施例中提出的固定扩展走线加灵活扩展走线结合的方式。例如，芯片之间的扩展走线RL8可以采用固定扩展走线方式，芯片与像素之间的扩展走线RL7可以采用灵活扩展走线方式。
例如，一个总控芯片CP10和多个芯片CP可以组成一个芯片组，所述背板上可以设置一个或多个这样的芯片组。
需要说明的是，可以根据显示装置的PPI及所能提供的扩展走线空间确定具有驱动电路的芯片CP与像素PX的数量对应关系，例如，可以使芯片CP与像素PX一一对应，或者可以使一个芯片CP对应背板上的所有像素PX。
参照图40B，所述背板上的像素PX可以为不同类型的像素，例如所述像素PX可以包括红色子像素(即R子像素)、绿色子像(即G子像素)素和蓝色子像素(即B子像素)。在这种情况下，一个芯片CP可以具有6个端子p1(即6个接口)。6个端 子p1分别通过扩展走线RL7与两个像素的R/G/B子像素电连接。
参照图40C，所述背板上可以既设置所述显示像素，又设置所述传感器像素。在该情况下，一个芯片CP可以具有驱动接口和功放接口等功能不同的接口(即端子)。通过上述后对准工艺，图像识别后判断芯片pad的位置，将芯片CP与各像素PX进行正确的连接。例如，显示像素PX可以与芯片CP的端子p11电连接，传感器像素PX可以与芯片CP的端子p12电连接。
在本公开的实施例中，所述显示装置可以包括发光元件。例如，所述发光元件可以为顶发射发光元件，上述芯片CP可以设置在发光元件的下方；或者，所述发光元件可以为底发射发光元件，上述芯片CP可以设置在发光元件的上方。图41示意性示出了芯片和像素的投影关系。参照图41，芯片CP在衬底上的正投影可以与多个像素PX在衬底上的正投影部分重叠。这样，可以实现具有更高PPI的显示装置。
在本公开的实施例中，可以实现更小尺度上的芯片驱动方式。此外，由于可以设置多个总控芯片，总控芯片还可以电连接至更高一级的控制芯片，因此，可以实现各区域的分别控制。
在本公开的实施例中，所述显示装置可以包括设置于所述背板上的选通芯片CP12。例如，所述选通芯片CP12可以包括选通TFT或门级电路。图42是根据本公开实施例的选通芯片的选通TFT的原理图。图43是根据本公开实施例的包括选通芯片的显示装置的局部平面图。图44A和图44B分别是根据本公开实施例的包括选通芯片的显示装置的电路连接图。
结合参照图42至图44B，所述显示装置可以包括选通芯片CP12、芯片CP和总控芯片CP10。一个所述选通芯片CP12可以包括至少2个端口(例如4个端口MUX1/MUX2/MUX3/MUX4)，一个所述芯片CP可以包括至少2个端子p1(例如4个端子p1)。位于同一行的多个像素PX可以通过行信号连接线L1电连接，位于同一列的多个像素PX可以通过列信号连接线L2电连接。一个选通芯片CP12的多个端口MUX1～MUX4可以分别通过扩展走线RL13与多个行信号连接线L1电连接。一个芯片CP的一个端子p1可以分别通过多个选通TFT与同一列的多个像素电连接。选通芯片CP12和多个芯片CP还可以通过扩展走线RL14电连接至总控芯片CP10。例如，多个选通芯片、至少一个总控芯片和多个芯片可以组成一个芯片组，在背板上可以设置多个这样的芯片组。
例如，在选通芯片CP12的某一端口发出的行选通信号的控制下，可以控制某一行的像素导通。在列选通信号的控制下，可以控制相应的芯片CP发送驱动信号给某一列的像素。这样，可以在选通信号的控制下，实现背板上的像素的分区显示和单独控制。
类似地，例如，所述像素PX可以包括但不限于，用于实现显示功能的显示像素，用于实现探测功能的传感器像素等。所述显示像素包括但不限于OLED、microLED、miniLED、LCD等显示元件。
例如，对应显示像素，芯片CP可以为驱动芯片；对应传感器像素，芯片CP可以为功放芯片，总控芯片CP10可以为ADC芯片。
需要说明的是，上述制造方法的一些步骤可以单独执行或组合执行，以及可以并行执行或顺序执行，并不局限于图中所示的具体操作顺序。
如这里所使用的，术语“基本上”、“大约”、“近似”和其它类似的术语用作近似的术语而不是用作程度的术语，并且它们意图解释将由本领域普通技术人员认识到的测量值或计算值的固有偏差。考虑到工艺波动、测量问题和与特定量的测量有关的误差(即，测量系统的局限性)等因素，如这里所使用的“大约”或“近似”包括所陈述的值，并表示对于本领域普通技术人员所确定的特定值在可接受的偏差范围内。例如，“大约”可以表示在一个或更多个标准偏差内，或者在所陈述的值的±10％或±5％内。
虽然根据本公开的总体发明构思的一些实施例已被图示和说明，本领域普通技术人员将理解，在不远离本公开的总体发明构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (54)

  1. 一种半导体装置，其特征在于，所述半导体装置包括：
    衬底；
    设置于所述衬底的芯片，所述芯片包括芯片主体和设置于所述芯片主体上的多个端子；
    设置于所述衬底的端子扩展层，所述端子扩展层包括导电材料，
    其中，所述端子扩展层和至少一个端子位于所述芯片主体的同一侧，所述半导体装置还包括位于所述端子扩展层中的多个扩展走线，所述多个扩展走线分别与所述多个端子电连接，用于引出所述多个端子；以及
    至少一个扩展走线在所述衬底上的正投影完全覆盖与该扩展走线电连接的端子在所述衬底上的正投影。
  2. 根据权利要求1所述的半导体装置，其特征在于，所述半导体装置还包括粘性层，所述粘性层设置在所述衬底与所述芯片主体之间，用于将所述芯片固定于所述衬底上；以及
    所述芯片主体包括第一表面，所述第一表面面向或接触所述粘性层，至少一个端子设置在所述芯片主体除该第一表面之外的表面上。
  3. 根据权利要求1所述的半导体装置，其特征在于，所述衬底包括第一衬底表面，所述芯片设置在该第一衬底表面上，所述第一衬底表面包括第一衬底边缘；以及
    至少一个扩展走线在所述衬底上的正投影相对于所述第一衬底边缘倾斜。
  4. 根据权利要求3所述的半导体装置，其特征在于，所述芯片主体具有远离所述衬底的第二表面，所述第二表面在所述衬底上的正投影具有规则形状，所述第二表面所述衬底上的正投影包括第一边缘；以及
    所述第一边缘相对于所述第一衬底边缘倾斜。
  5. 根据权利要求4所述的半导体装置，其特征在于，所述至少一个扩展走线在所 述衬底上的正投影的延长线与所述第一衬底边缘的延长线之间形成第一夹角，所述第一夹角大于0°小于90°；和/或，
    所述第一边缘的延长线与所述第一衬底边缘的延长线之间形成第二夹角，所述第二夹角大于0°小于90°。
  6. 根据权利要求2所述的半导体装置，其特征在于，所述衬底包括第一衬底表面，所述芯片设置在该第一衬底表面上；
    所述芯片的芯片主体包括第二表面、第一侧表面和第二侧表面，所述第二表面和所述第一表面分别位于所述芯片主体的相对侧，所述第一侧表面和所述第二侧表面分别位于所述芯片主体的侧表面，所述第一侧表面和所述第二侧表面中的每一个均连接所述第一表面与所述第二表面；以及
    所述第一侧表面和所述第二侧表面中的至少一个相对于所述第一衬底表面倾斜。
  7. 根据权利要求6所述的半导体装置，其特征在于，至少一个扩展走线与至少一个端子直接接触，并且所述至少一个扩展走线的一部分与所述第一侧表面和所述第二侧表面中的一个直接接触。
  8. 根据权利要求2所述的半导体装置，其特征在于，所述半导体装置还包括设置于所述芯片的一侧且覆盖所述端子的第一平坦化层；以及
    所述端子扩展层位于所述第一平坦化层远离所述芯片的一侧，所述扩展走线的一端通过贯穿所述第一平坦化层的过孔或凹槽与所述端子电连接。
  9. 根据权利要求2所述的半导体装置，其特征在于，所述半导体装置还包括衬垫，所述衬垫位于所述芯片主体靠近所述衬底的一侧，所述衬垫在所述衬底上的正投影与所述芯片主体在所述衬底上的正投影至少部分重叠。
  10. 根据权利要求2所述的半导体装置，其特征在于，所述半导体装置还包括设置于所述芯片的一侧且覆盖所述端子的第一平坦化层和设置于所述第一平坦化层远离所述衬底一侧的第二平坦化层；
    所述半导体装置还包括第一走线，所述第一走线位于重布线层中；以及
    所述重布线层位于所述第二平坦化层远离所述芯片的一侧，所述第一走线的一端通过贯穿所述第一平坦化层和所述第二平坦化层两者的过孔或凹槽与所述扩展走线电连接。
  11. 根据权利要求1所述的半导体装置，其特征在于，所述半导体装置还包括功能器件，所述功能器件与所述芯片的至少一个端子电连接；以及
    所述功能器件与所述芯片位于不同的层。
  12. 根据权利要求1所述的半导体装置，其特征在于，所述半导体装置包括多个重复单元，多个重复单元沿第一方向和第二方向成阵列地布置在所述衬底上；
    每个重复单元包括多个所述芯片，位于每个重复单元内的多个芯片沿第一方向和第二方向成阵列地布置在所述衬底上，或者，位于每个重复单元内的多个芯片中的至少一部分沿第一方向和第二方向成阵列地布置在所述衬底上；以及
    在所述多个重复单元中的至少两个中，一个重复单元中的至少一个芯片在该重复单元中的相对位置与另一个重复单元中的对应芯片在该另一个重复单元中的相对位置不相同；和/或，在所述多个重复单元中的至少两个中，一个重复单元中的至少一个芯片在该重复单元中的朝向与另一个重复单元中的对应芯片在该另一个重复单元中的朝向不相同。
  13. 根据权利要求12所述的半导体装置，其特征在于，在所述多个重复单元中的至少两个中，用于引出一个重复单元中的至少一个芯片的至少一个端子的扩展走线的长度与用于引出另一个重复单元中的对应芯片的对应端子的扩展走线的长度不相等；和/或，
    在所述多个重复单元中的至少两个中，用于引出一个重复单元中的至少一个芯片的至少一个端子的扩展走线的延伸方向与用于引出另一个重复单元中的对应芯片的对应端子的扩展走线的延伸方向不相同。
  14. 根据权利要求12所述的半导体装置，其特征在于，对于位于沿所述第一方向 或所述第二方向的同一排的两个芯片，每一个芯片的芯片主体具有远离所述衬底的第二表面，所述第二表面在所述衬底上的正投影具有规则形状，所述两个芯片的芯片主体的第二表面在所述衬底上的正投影的几何中心之间的连线与所述第一方向或所述第二方向之间形成第三夹角，所述第三夹角大于0°小于90°。
  15. 根据权利要求6所述的半导体装置，其特征在于，所述芯片包括的多个端子均位于该芯片的芯片主体的第二表面上；或者，
    所述芯片包括的多个端子分别位于该芯片的芯片主体的第一侧表面和第二侧表面上；或者，
    所述芯片包括的多个端子分别位于该芯片的芯片主体的第一表面和第二表面上。
  16. 根据权利要求1-15中任一项所述的半导体装置，其特征在于，所述芯片包括第一芯片和第二芯片，所述第一芯片包括至少两个第一端子，所述第二芯片包括至少两个第二端子；
    其中，所述第一芯片和所述第二芯片被配置为实现不同的功能，所述第一芯片包括发光芯片和传感芯片中的至少一种，所述第二芯片包括传感芯片和控制芯片中的至少一种；以及
    所述至少一个扩展走线的一端与所述第一芯片电连接，所述至少一个扩展走线的另一端与所述第二端子电连接。
  17. 根据权利要求16所述的半导体装置，其特征在于，所述第一芯片包括发光芯片，所述第一芯片和所述第二芯片布置在同一层。
  18. 根据权利要求16所述的半导体装置，其特征在于，所述第一芯片包括发光芯片，所述第一芯片和所述第二芯片布置在不同的层；以及
    所述半导体装置还包括驱动元件，所述驱动元件和所述第一芯片通过至少一个扩展走线电连接。
  19. 根据权利要求18所述的半导体装置，其特征在于，所述驱动元件为驱动芯片， 所述驱动芯片在所述衬底上的正投影与所述第一芯片在所述衬底上的正投影至少部分重叠；以及
    所述第一芯片包括主发光面，所述主发光面位于所述第一芯片远离所述驱动芯片的一侧。
  20. 根据权利要求18所述的半导体装置，其特征在于，所述驱动元件为驱动芯片，所述驱动芯片在所述衬底上的正投影与所述第一芯片在所述衬底上的正投影不重叠；以及
    所述第一芯片包括主发光面，所述主发光面位于所述第一芯片靠近所述驱动芯片的一侧。
  21. 根据权利要求18所述的半导体装置，其特征在于，所述驱动元件包括用于驱动所述第一芯片的驱动电路，所述驱动电路至少包括薄膜晶体管，所述薄膜晶体管位于与所述第一芯片和所述第二芯片不同的层；以及
    所述薄膜晶体管至少包括源极和漏极，所述源极或所述漏极通过过孔或凹槽与至少一个扩展走线电连接。
  22. 根据权利要求16所述的半导体装置，其特征在于，所述芯片还包括第三芯片，所述第一芯片、所述第二芯片和所述第三芯片被配置为彼此实现不同的功能；
    所述半导体装置包括至少一个芯片组，每个芯片组包括至少一个第二芯片和至少一个第三芯片；以及
    多个芯片组以一一对应的方式与多个第一芯片电连接；或者，一个芯片组与多个第一芯片电连接。
  23. 根据权利要求16所述的半导体装置，其特征在于，所述第一芯片包括传感芯片，多个传感芯片串联连接；以及
    所述第二芯片包括控制芯片。
  24. 根据权利要求23所述的半导体装置，其特征在于，每一个所述传感芯片包括 第一电极、第二电极和夹设在所述第一电极与所述第二电极之间的功能薄膜；
    所述半导体装置包括多个传感芯片组和多个导电部，每一个传感芯片组包括至少两个传感芯片；
    多个传感芯片组分别设置在多个导电部上，多个导电部间隔设置；以及
    在一个传感芯片组中，任意两个相邻的传感芯片中的一个传感芯片的第一电极和另一个传感芯片的第二电极与同一个导电部接触。
  25. 根据权利要求23所述的半导体装置，其特征在于，每一个所述传感芯片包括第一电极、第二电极和夹设在所述第一电极与所述第二电极之间的功能薄膜；
    所述半导体装置包括多个传感芯片组和至少一个导电部，每一个传感芯片组包括至少两个传感芯片；
    至少两个传感芯片组设置在同一个导电部上；以及
    在一个传感芯片组中，至少两个传感芯片堆叠放置于导电部上，最靠近所述导电部的一个传感芯片的第一电极或第二电极与所述导电部接触，任意两个相邻的传感芯片中的一个传感芯片的第一电极和另一个传感芯片的第二电极接触。
  26. 根据权利要求1所述的半导体装置，其特征在于，所述半导体装置包括多个所述芯片和设置于所述衬底的多个固定连接部，所述多个固定连接部分别邻近所述多个芯片设置；以及
    所述扩展走线用于电连接所述多个芯片；用于电连接两个芯片的扩展走线至少包括第一走线段和第二走线段，所述第一走线段用于电连接一个芯片的端子与该芯片邻近的一个固定连接部，所述第二走线段用于连接两个芯片之间的两个固定连接部。
  27. 根据权利要求26所述的半导体装置，其特征在于，至少一个第二走线段沿第一方向延伸；以及
    在通过包括沿第一方向延伸的第二走线段的扩展走线电连接的两个芯片中，一个芯片在所述第一方向上的相对位置与另一个芯片在所述第一方向上的相对位置不相同。
  28. 根据权利要求26或27所述的半导体装置，其特征在于，在通过包括至少一个第二走线段的扩展走线电连接的两个芯片中，至少一个芯片相对于所述第二走线段的延长线倾斜。
  29. 根据权利要求28所述的半导体装置，其特征在于，在通过包括至少一个第二走线段的扩展走线电连接的两个芯片中，一个芯片相对于所述第二走线段的延长线的朝向与另一个芯片相对于所述第二走线段的延长线的朝向不相同。
  30. 根据权利要求26、27或29所述的半导体装置，其特征在于，在通过包括至少一个第二走线段的扩展走线电连接的两个芯片中，每一个芯片包括的多个端子至少包括第一端子和第二端子；
    用于电连接两个芯片的第一端子的扩展走线包括的第二走线段和用于电连接两个芯片的第二端子的扩展走线包括的第二走线段彼此平行，和/或，用于电连接两个芯片的第一端子的扩展走线包括的第二走线段和用于电连接两个芯片的第二端子的扩展走线包括的第二走线段的长度基本相等。
  31. 根据权利要求26、27或29所述的半导体装置，其特征在于，至少一个第一走线段和与它相邻且电连接的第二走线段之间具有夹角，所述夹角大于0°小于180°。
  32. 根据权利要求31所述的半导体装置，其特征在于，在与同一个第二走线段相邻且电连接的两个第一走线段中，一个第一走线段和与它相邻且电连接的第二走线段之间的夹角不同于另一个第一走线段和与它相邻且电连接的第二走线段之间的夹角。
  33. 根据权利要求31所述的半导体装置，其特征在于，在与同一个芯片的第一端子和第二端子电连接的两个第一走线段中，一个第一走线段和与它相邻且电连接的第二走线段之间的夹角不同于另一个第一走线段和与它相邻且电连接的第二走线段之间的夹角。
  34. 根据权利要求26、27或29所述的半导体装置，其特征在于，多个所述第一走线段位于同一层中；以及
    所述第二走线段与所述第一走线段位于相同或不同的层中。
  35. 根据权利要求26所述的半导体装置，其特征在于，所述多个芯片沿第一方向和第二方向成阵列地布置；以及
    至少一个第一走线段相对于所述第一方向和所述第二方向倾斜。
  36. 根据权利要求35所述的半导体装置，其特征在于，所述第二走线段沿所述第一方向或所述第二方向延伸。
  37. 根据权利要求1所述的半导体装置，，其特征在于，所述衬底包括相对设置的第一衬底和第二衬底，所述芯片和所述端子扩展层设置于所述第一衬底上，所述芯片包括设置于所述芯片主体上的多个第一端子，所述半导体装置包括：
    设置于所述第二衬底的多个第二端子，
    其中，所述端子扩展层和至少一个第一端子位于所述芯片主体的同一侧，所述多个扩展走线分别与所述多个第一端子电连接，用于引出所述多个第一端子；
    多个扩展走线在所述第一衬底上的正投影完全覆盖与该扩展走线电连接的第一端子在所述第一衬底上的正投影；以及
    所述多个第一端子分别通过所述多个扩展走线与所述多个第二端子电连接，所述多个第二端子在所述第一衬底上的正投影与所述多个扩展走线在所述第一衬底上的正投影至少部分重叠。
  38. 根据权利要求37所述的半导体装置，其特征在于，所述半导体装置还包括多个驱动元件，所述多个驱动元件设置于所述第二衬底上，所述多个第二端子位于所述多个驱动元件远离所述第二衬底的一侧，所述多个第二端子分别与所述多个驱动元件电连接。
  39. 根据权利要求37所述的半导体装置，其特征在于，所述芯片包括的多个第一 端子均位于该芯片的芯片主体远离所述第一衬底的一侧；以及
    所述半导体装置还包括粘性层，所述粘性层设置在所述第一衬底与所述芯片主体之间，用于将所述至少一个芯片固定于所述第一衬底上。
  40. 根据权利要求37所述的半导体装置，其特征在于，所述芯片包括的多个第一端子分别位于该芯片的芯片主体沿平行于所述第一衬底的第一衬底表面的方向的两侧，其中，所述第一衬底的第一衬底表面为所述第一衬底设置所述芯片的表面；以及
    所述半导体装置还包括粘性层，所述粘性层设置在所述第一衬底与所述芯片主体之间，用于将所述芯片固定于所述第一衬底上。
  41. 根据权利要求37所述的半导体装置，其特征在于，所述芯片包括的多个第一端子分别位于该芯片的芯片主体沿垂直于所述第一衬底的第一衬底表面的方向的两侧，其中，所述第一衬底的第一衬底表面为所述第一衬底设置所述芯片的表面；以及
    所述半导体装置还包括粘性层和第一导电层，所述粘性层设置在所述第一衬底与所述芯片主体之间，所述第一导电层设置在所述粘性层与所述芯片之间之间，所述第一导电层与所述芯片的靠近所述第一衬底的至少一个第一端子电连接。
  42. 一种半导体装置的制造方法，其特征在于，所述制造方法包括：
    将芯片置于衬底上，其中，所述芯片包括芯片主体和设置于所述芯片主体上的多个端子；以及
    通过后对准工艺在所述芯片远离所述衬底的一侧形成端子扩展层，其中，所述端子扩展层包括导电材料，
    其中，所述通过后对准工艺在芯片远离所述衬底的一侧形成端子扩展层包括：
    对设置有所述芯片的衬底进行拍照；
    采用图像识别技术确定多个端子的坐标，生成端子的图形文件；
    在所述芯片远离所述衬底的一侧形成导电材料层；以及
    根据所述图形文件，通过光刻工艺刻蚀所述导电材料层，以在所述端子扩展层中形成多个扩展走线，
    其中，所述多个扩展走线分别与所述多个端子电连接，用于引出所述多个端子； 以及
    至少一个扩展走线在所述衬底上的正投影完全覆盖与该扩展走线电连接的端子在所述衬底上的正投影。
  43. 根据权利要求42所述的制造方法，其特征在于，所述对设置有所述芯片的衬底进行拍照包括：
    对设置有所述芯片的衬底的第一拍照区域进行拍照；以及
    以设置于所述衬底上的一个位置标定标记为原点，按固定的步进距离平移拍照设备，以对设置有所述芯片的衬底的第二拍照区域进行拍照，
    其中，拍照的次数与所述芯片的分布密度相关，每一个拍照区域中设置有至少一个所述芯片。
  44. 根据权利要求42或43所述的制造方法，其特征在于，所述将芯片置于衬底上包括：
    在所述衬底上形成粘性层；以及
    通过转移工工艺将芯片转移至所述粘性层上，使得所述芯片通过所述粘性层固定于所述衬底上。
  45. 根据权利要求42或43所述的制造方法，其特征在于，所述制造方法还包括：在所述芯片远离所述衬底的一侧形成第一平坦化层，所述第一平坦化层覆盖所述芯片的端子；以及
    通过光刻工艺在所述第一平坦化层中形成多个过孔或凹槽，所述多个过孔或凹槽分别暴露所述芯片的端子的至少一部分，
    其中，所述通过后对准工艺在所述芯片远离所述衬底的一侧形成端子扩展层包括：
    在所述第一平坦化层远离所述衬底的一侧形成端子扩展层，通过后对准工艺形成位于所述端子扩展层中的扩展走线，使得所述扩展走线的一端通过所述过孔或凹槽与所述端子接触。
  46. 根据权利要求42或43所述的制造方法，其特征在于，所述通过后对准工艺 在芯片远离所述衬底的一侧形成端子扩展层包括：
    通过所述后对准工艺形成端子扩展层；
    在所述端子扩展层远离所述衬底的一侧形成第一平坦化层；
    通过光刻工艺在所述第一平坦化层中形成多个过孔或凹槽，所述多个过孔或凹槽暴露所述端子扩展层的至少一部分；以及
    在所述第一平坦化层远离所述衬底的一侧形成重布线层，
    其中，所述制造方法还包括：
    以所述端子扩展层为种子层，采用电化学方式镀金属层，以在所述多个过孔或凹槽中生长与所述第一平坦化层的厚度相等的导电连接部，其中，所述导电连接部用于电连接所述端子扩展层和所述重布线层。
  47. 根据权利要求42或43所述的制造方法，其特征在于，所述制造方法还包括：
    在所述后对准工艺中，采用图像识别技术确定不良点的坐标信息；以及
    基于所述坐标信息并通过所述光刻工艺刻蚀所述导电材料层，以在所述端子扩展层中形成至少一个用于修复所述不良点的扩展走线。
  48. 一种半导体装置的制造方法，其特征在于，所述制造方法包括：
    将多个芯片置于衬底上，其中，每个芯片包括芯片主体和设置于所述芯片主体上的多个端子；
    在所述衬底上形成多个固定连接部；以及
    通过后对准工艺在多个芯片远离所述衬底的一侧形成端子扩展层，其中，所述端子扩展层包括导电材料，
    其中，所述通过后对准工艺在多个芯片远离所述衬底的一侧形成端子扩展层包括：
    对设置有所述多个芯片和多个固定连接部的衬底进行拍照；
    采用图像识别技术确定各个芯片的端子的坐标，以生成端子的图形文件；
    在多个芯片远离所述衬底的一侧形成导电材料层；以及
    根据所述图形文件，通过光刻工艺刻蚀所述导电材料层，以在所述端子扩展层中形成多个扩展走线，
    其中，所述扩展走线用于电连接所述多个芯片，用于电连接两个芯片的扩展走线 至少包括第一走线段和第二走线段，所述第一走线段用于电连接一个芯片的端子与该芯片邻近的一个固定连接部，所述第二走线段用于连接两个芯片之间的两个固定连接部。
  49. 根据权利要求48所述的制造方法，其特征在于，所述生成端子的图形文件的步骤包括：
    采用图像识别技术，确定各个芯片的端子的坐标；
    读取各个固定连接部的预置坐标；以及
    根据确定出的各个芯片的端子的坐标和读取的各个固定连接部的预置坐标，生成端子的图形文件。
  50. 根据权利要求48或49所述的制造方法，其特征在于，所述对设置有所述多个芯片和多个固定连接部的衬底进行拍照包括：
    对设置有所述多个芯片和多个固定连接部的衬底的第一拍照区域进行拍照；以及
    以设置于所述衬底上的一个整体绝对坐标标定标记为原点，按固定的步进距离平移拍照设备，以对设置有所述多个芯片和多个固定连接部的衬底的第二拍照区域进行拍照，
    其中，拍照的次数与所述芯片的分布密度相关，每一个拍照区域中设置有至少一个所述芯片。
  51. 根据权利要求50所述的制造方法，其特征在于，至少两个拍照区域之间存在重叠的拍照区域。
  52. 根据权利要求50所述的制造方法，其特征在于，所述制造方法还包括：
    在所述衬底上形成整体绝对坐标标定标记和多个位置标定标记，
    其中，所述多个位置标定标记分别与多个拍照区域一一对应。
  53. 一种半导体装置的制造方法，其特征在于，所述制造方法包括：
    将芯片置于第一衬底上，其中，所述芯片包括芯片主体和设置于所述芯片主体上 的多个第一端子；
    通过后对准工艺在所述芯片远离所述第一衬底的一侧形成端子扩展层，其中，所述端子扩展层包括导电材料；
    在第二衬底上形成多个第二端子；以及
    对盒所述第一衬底和所述第二衬底，使得所述多个第一端子分别与多个第二端子电连接，
    其中，所述通过后对准工艺在所述芯片远离所述第一衬底的一侧形成端子扩展层包括：
    对设置有所述芯片的衬底进行拍照；
    采用图像识别技术确定芯片的第一端子的坐标，以生成第一端子的图形文件；
    在所述芯片远离所述第一衬底的一侧形成导电材料层；以及
    根据所述图形文件，通过光刻工艺刻蚀所述导电材料层，以在所述端子扩展层中形成多个扩展走线，
    其中，多个扩展走线在所述第一衬底上的正投影完全覆盖与该扩展走线电连接的第一端子在所述第一衬底上的正投影；以及
    所述多个第一端子分别通过所述多个扩展走线与所述多个第二端子电连接，所述多个第二端子在所述第一衬底上的正投影与所述多个扩展走线在所述第一衬底上的正投影至少部分重叠。
  54. 根据权利要求53所述的制造方法，其特征在于，所述将芯片置于第一衬底上包括：
    在所述第一衬底上形成粘性层；以及
    通过转移工工艺将所述芯片转移至所述粘性层上，使得所述芯片通过所述粘性层固定于所述第一衬底上。
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