WO2021219069A1 - 一种堆叠结构、显示屏及显示装置 - Google Patents

一种堆叠结构、显示屏及显示装置 Download PDF

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Publication number
WO2021219069A1
WO2021219069A1 PCT/CN2021/090892 CN2021090892W WO2021219069A1 WO 2021219069 A1 WO2021219069 A1 WO 2021219069A1 CN 2021090892 W CN2021090892 W CN 2021090892W WO 2021219069 A1 WO2021219069 A1 WO 2021219069A1
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Prior art keywords
layer
driving chip
sub
pixel
terminal
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PCT/CN2021/090892
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English (en)
French (fr)
Inventor
何大鹏
黄文进
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to JP2022565957A priority Critical patent/JP7477647B2/ja
Priority to KR1020227041264A priority patent/KR20230006528A/ko
Priority to EP21797561.4A priority patent/EP4131385A4/en
Publication of WO2021219069A1 publication Critical patent/WO2021219069A1/zh
Priority to US17/975,696 priority patent/US12020630B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • This application relates to the technical field of display devices, and in particular to a stack structure, a display screen and a display device.
  • Micro LED is an emerging display technology. Micro LED actually thins, miniaturizes, and arrays the luminescent particles (luminescent particles) of LEDs, so that each unit is smaller than 100 microns and can realize each The pixel is individually addressed and driven to emit light, which is what we often call self-illumination. Micro LED is similar to OLED (Organic Electroluminesence Display, organic light-emitting semiconductor), but it has a longer life than OLED screen, and its response speed can reach the nanosecond level, which is faster than OLED. Not only that, Micro LED also has many advantages such as high brightness, low power consumption, ultra-high resolution, etc., comprehensively speaking, it has more advantages than OLED.
  • OLED Organic Electroluminesence Display
  • the general structure of the existing Micro LED display panel Panel is as follows:
  • the display panel is composed of a number of display pixels, each of which contains three color light-emitting particles (light-emitting particles) of R, G, and B, or a micro-drive unit ( ⁇ IC).
  • ⁇ IC micro-drive unit
  • the application provides a stack structure, a display screen and a display device to improve the display effect of the display screen.
  • a stack structure is provided, and the stack structure is applied to a display screen as a display structure in the display screen.
  • the structure mainly includes: a substrate, a driving chip and a pixel unit, the substrate, the driving chip and the pixel unit are stacked, and each driving chip corresponds to at least one pixel unit.
  • the substrate has a first surface, the first surface is provided with a circuit layer, the driving chip is arranged on the surface of the circuit layer facing away from the first surface, and the pixel unit and the corresponding driving chip are stacked and arranged.
  • the sub-pixels located in each pixel unit are respectively electrically connected with the circuit layer and the corresponding driving chip to form a light-emitting loop.
  • the driving chip and the pixel unit can be located on different layers, more driving chips can be arranged on the substrate, and more driving chips can be arranged on the driving chip.
  • the pixel unit, the entire stacked structure can form a whole layer of pixel unit, the driver chip does not occupy the layout area of the pixel unit, which increases the number of pixel units arranged, thereby improving the display effect of the display screen.
  • the area where the driver chip is provided on the circuit layer is not electrically connected to the driver chip, or is insulated.
  • the area corresponding to the driver chip is not electrically connected or insulated from the driver chip, maintenance can be facilitated.
  • no inner layer wiring is provided in the area where the driver chip is provided on the circuit layer. Easy to maintain.
  • each driver chip away from the circuit layer is provided with a connecting post, and the connecting post is electrically connected to the driver chip and the circuit layer. Realize the connection with the circuit layer through the terminal.
  • the sub-pixels corresponding to each driving chip are arranged on the surface of the corresponding driving chip away from the circuit layer.
  • the sub-pixels in the corresponding pixel unit are directly carried by the driving chip.
  • each driving chip further includes a first packaging layer corresponding to each driving chip one-to-one, and each first packaging layer encapsulates the corresponding driving chip;
  • the sub-pixels corresponding to each driving chip are arranged on the first packaging layer.
  • the area where the pixel unit is arranged is increased by the first encapsulation layer, and the number of pixel units connected to the driving chip is increased.
  • each driving chip corresponds to a plurality of pixel units; and the plurality of pixel units are arranged in two rows. The installation area of the pixel unit is increased.
  • each second packaging layer encapsulates the corresponding driving chip and the plurality of sub-pixels.
  • the second packaging layer improves the protection of the sub-pixels and the driving chip.
  • it further includes a separation layer disposed between the circuit layer and the substrate. It is convenient to replace or repair the circuit layer.
  • each pixel unit includes three sub-pixels, and the three sub-pixels are sub-pixels that can emit red, blue, and green colors.
  • each sub-pixel includes a light-emitting layer and a P terminal and an N terminal respectively connected to the light-emitting layer; wherein, the P terminal is connected to a corresponding driving chip, and the N terminal is connected to the The circuit layer is connected; or, the P terminal is connected to the circuit layer, and the N terminal is connected to the corresponding driving chip.
  • Display is realized by using sub-pixels.
  • the P terminal, the light-emitting layer, and the N terminal are stacked, and the light-emitting layer is located between the P terminal and the N terminal.
  • the laminated structure is adopted to reduce the volume of sub-pixels.
  • the P terminal, the light-emitting layer, and the N terminal are arranged in a stack, and the P terminal and the N terminal are arranged in the same layer. Power is supplied in a horizontal direction.
  • a display screen in a second aspect, includes a housing and the stacking structure of any one of the above arranged in the housing. It can be seen from the above description that when the pixel unit and the driving chip are stacked, the driving chip and the pixel unit can be located on different layers, more driving chips can be arranged on the substrate, and more driving chips can be arranged on the driving chip.
  • the pixel unit, the entire stacked structure can form a whole layer of pixel unit, the driver chip does not occupy the layout area of the pixel unit, which increases the number of pixel units arranged, thereby improving the display effect of the display screen.
  • a display device in a third aspect, includes a body and the stack structure of any one of the above arranged in the body. It can be seen from the above description that when the pixel unit and the driving chip are stacked, the driving chip and the pixel unit can be located on different layers, more driving chips can be arranged on the substrate, and more driving chips can be arranged on the driving chip.
  • the pixel unit, the entire stacked structure can form a whole layer of pixel unit, the driver chip does not occupy the layout area of the pixel unit, which increases the number of pixel units arranged, thereby improving the display effect of the display screen.
  • FIG. 1 is a schematic structural diagram of a display screen provided by an embodiment of the application.
  • FIG. 2 is a top view of a stack structure provided by an embodiment of the application.
  • FIG. 3 is a side view of a stack structure provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of the structure of the light-emitting particles provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of another structure of the luminescent particles provided by the embodiment of the application.
  • FIG. 6 is a side view of a stack structure provided by an embodiment of the application.
  • Figure 7 is a side view of a stack structure in the prior art
  • FIG. 8a is a top view of the substrate during the preparation of the stacked structure provided by an embodiment of the application.
  • Figure 8b is a cross-sectional view at A-A in Figure 8a;
  • FIG. 9a is a top view of a component when the stacked structure is prepared according to an embodiment of the application.
  • Figure 9b is a cross-sectional view at A-A in Figure 9a;
  • FIG. 10a is a top view of a component when the stacked structure is prepared according to an embodiment of the application.
  • Figure 10b is a cross-sectional view at A-A in Figure 10a;
  • FIG. 11a is a top view of a component when the stacked structure is prepared according to an embodiment of the application.
  • Figure 11b is a cross-sectional view at A-A in Figure 11a;
  • FIG. 12a is a top view of a component when the stacked structure is prepared according to an embodiment of the application.
  • Figure 12b is a cross-sectional view at A-A in Figure 12a;
  • 13-17 are flow charts for preparing the stack structure provided by the embodiments of the application.
  • FIG. 18 is a schematic diagram of another stack structure provided by an embodiment of the application.
  • 19 is a schematic structural diagram of another stack structure provided by an embodiment of the application.
  • FIG. 20 is a top view of another stack structure provided by an embodiment of the application.
  • the stack structure 2 provided by the embodiment of the present application is applied to a display screen.
  • the current existing display screen panel is composed of several display pixels, and the display screen has a plurality of display pixels 2 and a plurality of display pixels 2 They are arranged in rows along the direction a and in columns along the direction b.
  • Multiple display pixels 2 are located in the display area of the display screen, and realize the display function of the display screen through the light emission of the display pixels 2.
  • the multiple display pixels 2 are connected to the display driving integrated circuit (DDIC1) of the display screen, The driving signal of DDIC1 controls the voltage of the stack structure 2, thereby realizing the image display of the entire display screen.
  • DDIC1 display driving integrated circuit
  • FIG. 2 shows a top view of a stack structure provided by an embodiment of the present application.
  • the stack structure provided by the embodiment of the present application includes a substrate (not shown in FIG. 2), a circuit layer 50, a driving chip 20, and a pixel unit 30.
  • the driving chip 20 and the pixel unit 30 form a light emitting unit in the stack structure.
  • the substrate serves as a bearing structure and provides a base (support) function for the light-emitting unit (drive chip 20 and pixel unit 30).
  • the substrate can be made of a material with a certain supporting strength.
  • the material of the substrate can be glass, silicon, sapphire, PI (polyimide, a polymer containing imido groups in the main chain) and the like.
  • the circuit layer 50 is laminated with the substrate and connected to the driving chip 20 and the pixel unit 30.
  • the circuit layer 50 is also connected to the DDIC to realize the electrical connection between the DDIC and the light-emitting unit.
  • the driving chip 20 is arranged on a substrate. As shown in FIG. 2, a driving chip 20 is carried on the substrate.
  • the driving chip 20 adopts a rectangular shape, and the length direction of the driving chip 20 is along the direction a.
  • the driving chip 20 may be a micro integrated circuit (micro integrated circuit, ⁇ IC).
  • the number of driving chips 20 carried on the substrate is not specifically limited.
  • the substrate may also carry two, three, four, five, and other different numbers of driving chips 20.
  • all stacked structures in the display screen can share a substrate, and the drive chips 20 in the display screen are arrayed on the substrate, and the drive chips 20 are electrically connected to the substrate and connected to the DDIC through the substrate.
  • the pixel unit 30 is disposed on the driving chip 20.
  • the driving chip 20 shown in FIG. 2 carries two pixel units 30, and the two pixel units 30 are arranged along the direction a.
  • the number of pixel units 30 carried on the driving chip 20 is not limited.
  • the driving chip 20 can carry one pixel unit 30, three pixel units 30, four pixel units 30 and other different numbers.
  • Pixel unit 30 When the driving chip 20 carries a plurality of pixel units 30, the plurality of pixel units 30 are arranged in a single row along the direction a.
  • Each pixel unit 30 includes three sub-pixels arranged in the same layer, and the three sub-pixels are arranged in a single row along the direction a.
  • the three sub-pixels are sub-pixels that can emit red, blue, and green colors.
  • the three sub-pixels shown in FIG. 2 are respectively: a first sub-pixel 31a that can emit red light, a second sub-pixel 31b that can emit blue light, and a third sub-pixel 31c that can emit green light.
  • the driving chip 20 can control the pixel unit 30 to emit light of different colors by controlling the working state of the three sub-pixels.
  • the pixel unit 30 may further include other sub-pixels that can achieve the requirements of the display screen to emit light of different colors, for example, the sub-pixels adopt single-color or RGB three-color sub-pixels.
  • the number of sub-pixels in each pixel unit 30 and the light-emitting color of each sub-pixel are not specifically limited. In specific settings, the sub-pixels can be set as required.
  • FIG. 3 shows a side view of the stack structure shown in FIG. 2, which can directly reflect the specific stacking situation of the stack structure provided by the embodiment of the present application.
  • the direction z is defined: the direction from the inside of the display screen to the display surface of the display screen.
  • the substrate 10, the driving chip 20, and the pixel unit are stacked in a three-layer structure along the direction z, and the pixel unit is close to the display surface of the display screen.
  • the substrate 10 has a first surface, the first surface is provided with a circuit layer 50, and the circuit layer 50 has a circuit layer 52 connecting the DDIC, the driving chip 20 and the sub-pixel 31.
  • the circuit layer 50 as shown in FIG. 3 includes a support layer 51 and a circuit layer 52.
  • the support layer 51 can be made of different materials.
  • the material of the circuit layer 50 can be PI, epoxy resin or the like.
  • the circuit layer 52 may be wired in multiple layers within the support layer 51 or may be wired on the surface of the circuit layer 50.
  • the circuit layer 52 can be directly disposed on the substrate 10, and the substrate 10 is used as a supporting structure for the circuit layer 52, so that no additional support layer 51 is required to support the circuit layer 52, such as a printed circuit board or a circuit with circuit. Of the substrate.
  • the driving chip 20 is arranged on the surface of the circuit layer 50 away from the first surface, and can be bonded by film, metal bonding, or paste-like material bonding to fix the driving chip 20 on the circuit layer 50. surface.
  • the driver chip 20 has a terminal 21, the terminal 21 is arranged on the side of the driver chip 20 away from the circuit layer 50, and the terminal 21 is electrically connected to the circuit layer 52. Specifically, the terminal 21 is connected to the IO Pad 22 of the driver chip 20 through the connection line 70.
  • the terminal 21 can be connected to the IO (Input Output, electrical signal input and output) Pad 54 of the circuit layer 50 through RDL (Redistribution Layer).
  • the material of the connecting wire 70 may be Cu pillar (copper pillar bump), ITO (Information Technology Outsourcing, indium tin oxide), or conductive materials such as Cu and Au.
  • the sub-pixels 31 located in each pixel unit are respectively electrically connected to the circuit layer 50 and the corresponding driving chip 20 to form a light-emitting circuit.
  • the sub-pixel 31 is assembled on the surface of the driving chip 20 (the surface away from the first surface) through a transfer process and a bonding process.
  • the sub-pixels corresponding to each driving chip are arranged on the surface of the corresponding driving chip away from the circuit 50; and the vertical projection of the plurality of sub-pixels on the first surface is located on the first surface Inside the vertical projection.
  • the above-mentioned correspondence refers to the correspondence between the driving chip and the sub-pixel forming an electrical connection loop.
  • the sub-pixel 31 may use micro light-emitting diodes ( ⁇ LEDs).
  • the sub-pixel 31 provided by the embodiment of the present application includes a light-emitting layer 312 and a P terminal 313 and an N terminal 311 respectively connected to the light-emitting layer 312.
  • the P terminal 313, the light-emitting layer 312 and the N terminal 311 of the sub-pixel 31 are stacked, and the light-emitting layer 312 is located between the P terminal 313 and the N terminal 311.
  • the volume of the sub-pixel 31 can be reduced, and the size of the sub-pixel 31 can be controlled between 5*5um and 100*100um.
  • the structure of another sub-pixel 31, the sub-pixel 31 is a flip-chip type: the P terminal 313, the light-emitting layer 312, and the N terminal 311 are stacked, and the P terminal 313 and the N terminal 311 are in the same layer. set up.
  • Both the structures shown in FIG. 4 and FIG. 5 can be applied to the stack structure provided in the embodiment of the present application.
  • the sub-pixel 31 shown in FIG. 4 is applied to the stack structure shown in FIG.
  • the P terminal 313 of the sub-pixel 31 is connected to the P Pad 23 of the driving chip.
  • the N terminal 311 of the sub-pixel 31 is connected to the GND Pad53 of the circuit layer 50 through the connection line 60.
  • the N terminal 311 of the sub-pixel 31 can be connected to the GND Pad53 of the circuit layer 50 through the RDL, or a fan out circuit can be used to connect to the circuit layer.
  • the GND Pad53 of 50 is connected to realize the electrical connection between the sub-pixel 31 and the circuit layer 52.
  • the material of the connecting wire 60 may be conductive materials such as Cu pillar, ITO, Cu, Au, etc.
  • the driving chip 20 and the sub-pixel 31 are connected to the corresponding electrodes (GND Pad 53 and IO Pad 54) of the sub-pixel 31 and the driving chip 20 on the circuit layer 52 through the RDL process or the Fan Out process to realize the circuit loop of the entire stack structure.
  • the sub-pixels can also be connected to the IO Pad of the circuit layer, and the IO Pad of the driving chip is connected to the GND Pad of the circuit layer.
  • the electrical connection between the driving chip and the sub-pixels and the circuit layer can also be realized.
  • the stack structure further includes a separation layer 40 disposed on the substrate, and the separation layer 40 may be used as an optional layer structure in the embodiment of the present application.
  • the circuit layer 50 is disposed on the separation layer 40, and the separation layer 40 can be peeled from the substrate.
  • the separation layer 40 can be separated by a laser lift-off method, so as to replace the damaged pixel unit.
  • the aforementioned separation layer 40 may be a laser photosensitive material (such as potassium nitride, arsenic nitride) or a chemically corroded material.
  • the area of the circuit layer 50 where the driving chip 20 is provided is insulated from the driving chip 20. That is, when the driving chip 20 is fixed on the circuit layer 50, the area covered by the driving chip 20 is not provided with a circuit. As an optional solution, the area of the circuit layer 50 where the driver chip 20 is provided is not provided with inner layer wiring. As shown in FIG. 3, the first area 53 is the area covering the driving chip 20 when the driving chip 20 is arranged on the circuit layer 50. As can be seen from FIG. 3, when the light-emitting unit is separated by a separation layer, it needs to be connected The circuit layer 50 is separated together.
  • the driving chip 20 can be directly placed in the original position.
  • the stacked structure further includes a second encapsulation layer 80 corresponding to each driver chip 20 one-to-one, and each second encapsulation layer 80 encapsulates the corresponding driver chip 20 and a plurality of sub-pixels 31 to protect The driver chip 20 and the sub-pixel 31.
  • the second packaging layer 80 has a trapezoidal structure and wraps the driving chip 20 and the sub-pixels 31.
  • the second encapsulation layer 80 is made of a transparent plastic molding compound so as to transmit the light emitted by the sub-pixels 31.
  • the material of the second encapsulation layer 80 may be COF (Chip On Flex, or, Chip On Film, chip on film) material, or may be a transparent photoresist material or other transparent epoxy resin materials.
  • COF Chip On Flex, or, Chip On Film, chip on film
  • the connecting lines connecting the driving chip 20 and the sub-pixels 31 to the circuit layer can be arranged in the second encapsulation layer 80, and connect them to the driving chip 20 and the sub-layer through the second encapsulation layer 80.
  • the pixels 31 are packaged together, and the connecting wires as shown in FIG. 3 can also be attached to the surface of the second package layer 80.
  • the circuit layer 51 of the circuit layer 50 is not provided with a circuit in the area corresponding to the second encapsulation layer 80 to ensure that the circuit layer will not be damaged when the circuit layer is cut.
  • the terminal 21 may be provided on the second encapsulation layer 80 in the form of a metal via, or may also be in the form of a pillar structure.
  • a via hole can be opened in the second encapsulation layer 80, a metal via hole can be formed by a metal plating layer as a connection post, or a metal material can be filled in the via hole to form a post structure as a connection post.
  • the stack structure provided by the embodiments of the present application can effectively reduce the area occupied by the light-emitting unit on the substrate when the driver chip and the pixel unit are stacked.
  • the stacked structure is compared.
  • the stack structure of the present application and the stack structure in the prior art will be described below with reference to FIG. 6 and FIG. 7. To facilitate understanding, the difference between the two stacked structures is illustrated by a comparison in the length direction.
  • Fig. 6 shows a side view of a stack structure provided by an embodiment of the present application.
  • the length of the substrate 10 of the stacked structure is H1
  • the length of the driving chip 20 is H2
  • the length of the pixel unit (the length of the sub-pixel 31) is H3.
  • the total length on the substrate 10 occupied by the light-emitting unit is H2: the length occupied by the light-emitting part (pixel unit) in the light-emitting unit is H3, and the length occupied by the non-light-emitting part is H2-H3. It can be seen that in the length direction of the substrate 10, the number of light-emitting units can be determined according to the values of H1 and H2.
  • Fig. 7 shows a side view of a stack structure in the prior art.
  • the length of the substrate 3 of the stacked structure is H4, the length of the driving chip 4 is H2, and the length of the pixel unit (the length of the sub-pixel 6) is H3.
  • the total length of the substrate 3 occupied by the light-emitting unit is H3+H2 (the size after removing the gap between the components), where,
  • the length occupied by the light-emitting part (pixel unit) of the light-emitting unit is H3, and the size occupied by the non-light-emitting part is H2.
  • the number of light-emitting units can be determined according to the values of H4 and (H2+H3).
  • the light-emitting unit in FIG. 7 occupies a larger size than the light-emitting unit in FIG. 6. And in the light-emitting unit shown in FIG. 6 and FIG. 7, the light-emitting part in the light-emitting unit shown in FIG. 7 accounted for H3/(H2+H3) less than the light-emitting part in the light-emitting unit shown in FIG. Compared with H3/H2, at the same time, the size H2+H3 of the light-emitting unit in FIG. 7 is larger than the size H2 of the light-emitting unit shown in FIG. Light-emitting unit. When applied in a display screen, the number of pixel units can be increased in the same display area, thereby improving the display accuracy of the display screen and improving the display effect.
  • Step 001 Provide a substrate.
  • Fig. 8a shows a top view of the substrate 10
  • Fig. 8b shows a cross-sectional view at A-A in Fig. 8a.
  • the circuit layer 50 and the separation layer 40 have been provided on the substrate 10.
  • the wiring and pad (not shown in the figure) connecting the DDIC control signal in the circuit layer 50 have been processed;
  • the separation layer 40 between the circuit layer 50 and the substrate 10 is made of a laser sacrificial layer material.
  • the circuit layer 50 has IO Pad54 and GND Pad53, where IOpad54 is made of In with a thickness of 3um, and GNDPad53 is made of Au with a thickness of 0.05um, and the DDIC trace connection pad plating layer can adopt the same plating structure.
  • Step 002 Set up the driver chip.
  • Fig. 9a shows a top view of the component
  • Fig. 9b shows a cross-sectional view at A-A in Fig. 9a.
  • Part of the reference numerals in FIGS. 9a and 9b can refer to the same reference numerals in FIGS. 8a and 8b.
  • the driving chip 20 is assembled on the circuit layer 50 through a transfer process and a die attach (chip attach) process.
  • the transfer process depends on the fabrication process of the wafer, which can be laser transfer or physical transfer.
  • the driving chip 20 is fixed on the wire using film or adhesive die attach, and the IO Pad 22 and P Pad 23 of the driving chip 20 face upward (taking the placement direction of the substrate 10 in FIG. 9b as the reference direction).
  • Step 003 Set sub-pixels.
  • Fig. 10a shows a top view of the component
  • Fig. 10b shows a cross-sectional view at A-A in Fig. 10a.
  • Part of the reference numerals in FIGS. 10a and 10b can refer to the same reference numerals in FIGS. 9a and 9b.
  • the sub-pixel 31 adopts a vertical structure as shown in FIG. 4.
  • the sub-pixel 31 is assembled on the surface of the driving chip 20 through a transfer process and a bonding process; wherein the P terminal (anode) of the sub-pixel 31 is connected to the P Pad 23 of the driving chip 20.
  • Step 004 Prepare an encapsulation layer.
  • Fig. 11a shows a top view of the component
  • Fig. 11b shows a cross-sectional view at A-A in Fig. 11a.
  • Part of the reference numerals in FIGS. 11a and 11b can refer to the same reference numerals in FIGS. 10a and 10b.
  • the sub-pixel 31 and the driving chip 20 are packaged through a PLN (Planarization) printing process to form a second packaging layer 80, and the negative electrode (N terminal) of the sub-pixel 31 and the IO Pad 22 of the driving chip 20 are exposed through a photolithography process.
  • PLN Planarization
  • the material of the second encapsulation layer 80 is a transparent material, specifically COF (Chip On Flex, or, Chip On Film, often referred to as a chip on film) material, or a transparent photoresist material or other transparent epoxy resin materials .
  • Step 005 Fan out and routing.
  • Figure 12a shows a top view of the components
  • Figure 12b shows a cross-sectional view at AA in Figure 12a
  • the part numbers in Figures 12a and 12b can refer to the same in Figures 11a and 11b. Label.
  • connection wiring between the driving chip 20 and the circuit layer 50 can use the ⁇ Bump (micro bump) process, which can be Cu Or Al or ITO circuit technology.
  • Step 006 Test.
  • a lighting test is performed on the stacked structure through DDIC, and if there is a defective light-emitting unit, the position of the defective light-emitting unit is located.
  • Step 007 Cutting the bad light-emitting unit.
  • the part numbers in FIG. 13 can refer to the same reference numbers in FIG. 12b.
  • the defective light-emitting unit is cut by laser.
  • the circuit layer 50 and the separation layer 40 are cut by laser, so that the defective light-emitting unit is split.
  • Step 008 Rejection of defective light-emitting units:
  • the part numbers in FIG. 14 can refer to the same reference numbers in FIG. 12b.
  • Step 009 Transfer and fix the light-emitting unit in the bad position:
  • the good light-emitting unit is transferred to a blank position by maintenance equipment, and is cured and fixed on the substrate 10 by heating or UV (ultraviolet).
  • Step 010 Repair and fill up the gaps around the light-emitting unit.
  • the part numbers in FIG. 16 can refer to the same reference numbers in FIG. 12b. Fill in the gaps around the repaired light-emitting unit through a printing device and solidify.
  • Step 011 Wiring realizes the connection between the light-emitting unit and the circuit layer of the substrate.
  • the part numbers in FIG. 17 may refer to the same reference numbers in FIG. 12b.
  • the wiring on the light-emitting unit is connected to the wiring on the circuit layer 50 through CVD (Chemical Vapor Deposition) or printing silver paste solution to achieve conduction.
  • the driving chip and the pixel unit can be located on different layers, more driving chips can be arranged on the substrate, and more driving chips can be arranged on the driving chip.
  • the entire stack structure can form a whole layer of pixel units, and the driver chip does not occupy the layout area of the pixel units, which increases the number of pixel units arranged, and further improves the display effect of the display screen.
  • the separation layer the light-emitting unit on the stacked structure can be replaced during preparation, which improves the reliability of the stacked structure in use.
  • each driving chip 20 carries two rows of sub-pixels 31, but each sub-pixel
  • the vertical projection on the first surface is located within the vertical projection of the driving chip on the first surface; wherein, the first surface is the surface of the substrate facing the circuit layer.
  • FIG. 19 illustrates another stacking structure provided by an embodiment of the present application, and some reference numerals in FIG. 19 may refer to the same reference numerals in FIG. 3.
  • the difference from the stacked structure shown in FIG. 3 is that the arrangement position of the sub-pixel 31 has been changed.
  • the stacked structure shown in FIG. 19 includes a first encapsulation layer 90.
  • Each driver chip 20 on the substrate 10 corresponds to a first encapsulation layer 90 one-to-one, and each first encapsulation layer 90 encapsulates the corresponding driver chip 20, and a plurality of sub-pixels 31 corresponding to each driver chip 20 are arranged in the first package.
  • Layer 90 is another stacking structure provided by an embodiment of the present application, and some reference numerals in FIG. 19 may refer to the same reference numerals in FIG. 3. The difference from the stacked structure shown in FIG. 3 is that the arrangement position of the sub-pixel 31 has been changed.
  • the stacked structure shown in FIG. 19 includes a first encapsulation layer 90
  • the vertical projection of the plurality of sub-pixels 31 on the first surface is located within the vertical projection of the driving chip 20 on the first surface; the first surface is the surface of the substrate 10 facing the circuit layer 50.
  • the first encapsulation layer 90 as shown in FIG. 19 adopts a rectangular parallelepiped-shaped structure.
  • the sub-pixel 31 is arranged on the first encapsulation layer 90, compared to the sub-pixel 31 shown in FIG. 3 being directly arranged on the driving chip 20, the arrangement of the sub-pixel 31 shown in FIG. The number of sub-pixels 31 carried by the chip 20.
  • FIG. 20 illustrates a top view of a driving chip carrying a plurality of pixel units 30. In FIG. 2, affected by the size of the driving chip 20, the driving chip 20 can only be provided with pixel units 30 arranged in a single row. In the structure shown in FIG.
  • the driving chip 20 may correspond to a plurality of pixel units 30, and the plurality of pixel units 30 are arranged in two.
  • the row arrangement increases the number of pixel units 30 corresponding to the driving chip 20.
  • four pixel units 30 are distributed at the four corners of a driving chip 20, and they are connected to the driving chip 20 through wiring, which can ensure that one driving chip 20 controls 4 pixel units 30. Therefore, the number of driver chips 20 can be reduced, and the number of pixel units 30 in the display screen can be increased, and the display effect of the display screen can be improved.
  • each driver chip 20 is provided with three rows of connection ports 24, 25, and 26.
  • the middle row of connection ports 25 is used to connect to the terminal, and the two rows of connection ports 24, 26 on both sides are used to connect to the pixel unit 30, respectively.
  • the middle terminal is connected to the IO Pad 54 of the circuit layer 50, and each sub-pixel 31 is connected to the GND Pad 53 of the circuit layer 50.
  • the sub-pixels 31 of each driving chip 20 are connected in parallel to the circuit layer 50.
  • FIG. 20 is only a specific example, and other connection methods may also be adopted.
  • the sub-pixels 31 of each driving chip 20 are connected to the circuit layer 50 respectively, and the sub-pixels 31 of different colors can be individually controlled to emit light.
  • the foregoing only exemplifies the specific connection mode of the sub-pixel 31 and the circuit layer 50, and the stack structure provided by the embodiment of the present application can also adopt other connection modes to realize the control of the sub-pixel 31 by the circuit layer 50. There is no specific limitation in this application.
  • the manufacturing method of the stacked structure shown in FIG. 19 can refer to the manufacturing method of the stacked structure shown in FIG. 3. The only difference is that the manufacturing process of the first encapsulation layer 90 is added.
  • the driver chip 20 can be packaged through a PLN printing process, and the IO Pad and the P Pad of the driver chip 20 are exposed through a photolithography process.
  • the PLN material can be a transparent material or a non-transparent material.
  • the material of the first encapsulation layer 90 can be the same material as that of the second encapsulation layer, such as a COF material, a transparent photoresist material or other transparent epoxy resin materials.
  • the sub-pixel 31 is prepared on the first packaging layer 90, and the sub-pixel 31 is connected to the driving chip 20 through wiring.
  • the sub-pixels of the light-emitting unit are stacked above the driving chip 20 and placed in two layers.
  • the RGB three-color pixel points The size of the light-emitting unit is as small as 30*30um. Compared with the traditional non-stacked placement, the RGB three-color pixel size is as small as 50*50um.
  • the separation layer can be reacted by laser or chemical etching to peel off the damaged pixel module.
  • the GND, IO Pad circuit can be easily repaired, and it is convenient to replace the damaged pixel module with a good pixel module.
  • vertical sub-pixels are used in the embodiments of the present application, which ensure the same light-emitting area (the light-emitting area of Flipchip-type sub-pixels only occupies ⁇ 50% of its total area; vertical-type sub-pixels have a light-emitting area of ⁇ 100%. %), reduced device area.
  • the result is that under the same ppi and brightness, the area occupied by the sub-pixels is smaller, and the limit ppi can be increased as much as possible by using this feature; transparent display can be realized or other micro components can be integrated under the scenario of not reaching the limit ppi.
  • An embodiment of the present application also provides a display screen, which includes a housing and any one of the above-mentioned stacking structures arranged in the housing. It can be seen from the above description that when the pixel unit and the driving chip are stacked, the driving chip and the pixel unit can be located on different layers, more driving chips can be arranged on the substrate, and more driving chips can be arranged on the driving chip.
  • the pixel unit, the entire stacked structure can form a whole layer of pixel unit, the driver chip does not occupy the layout area of the pixel unit, which increases the number of pixel units arranged, thereby improving the display effect of the display screen.
  • An embodiment of the present application also provides a display device, which includes a main body and any of the above-mentioned stacked structures arranged in the main body. It can be seen from the above description that when the pixel unit and the driving chip are stacked, the driving chip and the pixel unit can be located on different layers, more driving chips can be arranged on the substrate, and more driving chips can be arranged on the driving chip.
  • the pixel unit, the entire stacked structure can form a whole layer of pixel unit, the driver chip does not occupy the layout area of the pixel unit, which increases the number of pixel units arranged, thereby improving the display effect of the display screen.

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Abstract

本申请提供了一种堆叠结构、显示屏及显示装置，堆叠结构包括层叠设置的基板、驱动芯片及像素单元，基板具有第一表面，第一表面设置有线路层，驱动芯片设置在线路层背离第一表面的表面，像素单元与对应的驱动芯片层叠设置。位于每个像素单元的子像素分别与所述线路层及对应的驱动芯片电连接并形成发光回路。由上述描述可以看出，在采用像素单元与驱动芯片层叠设置的方式时，驱动芯片和像素单元可位于不同的层，基板上可布置更多的驱动芯片，并且驱动芯片上也可布置更多的像素单元，整个堆叠结构，可形成一整层的像素单元，驱动芯片不会占用像素单元的布置区域，提高了像素单元布置的个数，进而提高了显示屏的显示效果。

Description

一种堆叠结构、显示屏及显示装置
相关申请的交叉引用
本申请要求在2020年04月30日提交中国专利局、申请号为202010362184.1、申请名称为“一种堆叠结构、显示屏及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及到显示装置技术领域，尤其涉及到一种堆叠结构、显示屏及显示装置。
背景技术
Micro LED(微型LED)是一种新兴的显示技术，Micro LED其实就是将LED的发光颗粒(发光颗粒)进行薄膜化、微小化和阵列化，从而让每个单元小于100微米，能够实现每个图元单独定址和单独驱动发光，也就是我们常说的自发光。Micro LED与OLED(OrganicElectroluminesence Display，有机发光半导体)比较类似，但它比OLED屏幕寿命更长，同时响应速度可以达到奈秒级别，比OLED更快。不仅如此，Micro LED还具有高亮度、低耗电、超高分辨率等诸多优势，综合来看比OLED更具优势。
目前现有的Micro LED显示面板Panel的通用结构如下：
显示Panel由若干个显示像素pixel组成，每个像素包含R、G、B三个色发光颗粒(发光颗粒)，或者会包含微驱动单元(μIC)。目前对μIC，发光颗粒的物理组装结构和与显示驱动器IC连接方式均有设计上的差异，直接导致整个显示Panel的显示效果及性能比较差。
发明内容
本申请提供了一种堆叠结构、显示屏及显示装置，用以提高显示屏的显示效果。
第一方面，提供了一种堆叠结构，该堆叠结构应用于显示屏中，作为显示屏中的显示结构。其结构主要包括：基板、驱动芯片及像素单元，基板、驱动芯片及像素单元层叠设置，且每个驱动芯片对应至少一个像素单元。基板具有第一表面，第一表面设置有线路层，驱动芯片设置在线路层背离第一表面的表面，像素单元与对应的驱动芯片层叠设置。位于每个像素单元的子像素分别与所述线路层及对应的驱动芯片电连接并形成发光回路。由上述描述可以看出，在采用像素单元与驱动芯片层叠设置的方式时，驱动芯片和像素单元可位于不同的层，基板上可布置更多的驱动芯片，并且驱动芯片上也可布置更多的像素单元，整个堆叠结构，可形成一整层的像素单元，驱动芯片不会占用像素单元的布置区域，提高了像素单元布置的个数，进而提高了显示屏的显示效果。
在一个具体的可实施方案中，所述线路层设置有所述驱动芯片的区域与所述驱动芯片未电连接，或者是绝缘的。在驱动芯片对应的区域与驱动芯片未电连接或者是绝缘的情况下，可以方便维修。
在一个具体的可实施方案中，所述线路层设置有驱动芯片的区域未设置内层布线。方便维修。
在一个具体的可实施方案中，所述每个驱动芯片背离所述线路层的一面设置有与接线柱，所述接线柱与所述驱动芯片和线路层电连接。通过接线柱实现与线路层连接。
在一个具体的可实施方案中，每个驱动芯片对应的子像素设置在对应的驱动芯片背离所述线路层的表面。通过驱动芯片直接承载对应的像素单元中的子像素。
在一个具体的可实施方案中，还包括与每个驱动芯片一一对应的第一封装层，每个第一封装层将对应的驱动芯片封装；
每个驱动芯片对应的子像素设置在所述第一封装层。通过第一封装层增大设置像素单元的面积，提高了驱动芯片连接的像素单元的个数。
在一个具体的可实施方案中，每个驱动芯片对应有多个像素单元；且所述多个像素单元排列成两排设置。增大了像素单元的设置面积。
在一个具体的可实施方案中，还包括与每个驱动芯片一一对应的第二封装层，每个第二封装层将对应的所述驱动芯片及所述多个子像素封装。通过第二封装层提高了对子像素及驱动芯片保护。
在一个具体的可实施方案中，还包括分离层，所述分离层设置在所述线路层与所述基板之间。方便更换或者维修线路层。
在一个具体的可实施方案中，每个像素单元包括三个子像素，三个子像素分别为可发射红、蓝、绿三色的子像素。
在一个具体的可实施方案中，每个子像素包括发光层以及与所述发光层分别连接的P端及N端；其中，所述P端与对应的驱动芯片连接，所述N端与所述线路层连接；或，所述P端与所述线路层连接，所述N端与对应的驱动芯片连接。通过采用子像素实现显示。
在一个具体的可实施方案中，所述P端、所述发光层及所述N端层叠设置，且所述发光层位于所述P端及所述N端之间。采用层叠结构，减少子像素的体积。
在一个具体的可实施方案中，所述P端、所述发光层及所述N端层叠设置，且所述P端及所述N端同层设置。采用水平方向的方式供电。
第二方面，提供了一种显示屏，该显示屏包括：壳体，以及设置在所述壳体内上述任一项所述的堆叠结构。由上述描述可以看出，在采用像素单元与驱动芯片层叠设置的方式时，驱动芯片和像素单元可位于不同的层，基板上可布置更多的驱动芯片，并且驱动芯片上也可布置更多的像素单元，整个堆叠结构，可形成一整层的像素单元，驱动芯片不会占用像素单元的布置区域，提高了像素单元布置的个数，进而提高了显示屏的显示效果。
第三方面，提供了一种显示装置，该显示装置包括本体以及设置在所述本体内的上述任一项所述的堆叠结构。由上述描述可以看出，在采用像素单元与驱动芯片层叠设置的方式时，驱动芯片和像素单元可位于不同的层，基板上可布置更多的驱动芯片，并且驱动芯片上也可布置更多的像素单元，整个堆叠结构，可形成一整层的像素单元，驱动芯片不会占用像素单元的布置区域，提高了像素单元布置的个数，进而提高了显示屏的显示效果。
附图说明
图1为本申请实施例的提供的显示屏的结构示意图；
图2为本申请实施例的提供的堆叠结构的俯视图；
图3为本申请实施例的提供的堆叠结构的侧视图；
图4为本申请实施例的提供的发光颗粒的结构示意图；
图5为本申请实施例的提供的发光颗粒的另一结构示意图；
图6为本申请实施例的提供的堆叠结构的侧视图；
图7为现有技术中的堆叠结构的侧视图；
图8a为本申请实施例提供的堆叠结构制备时基板的俯视图；
图8b为图8a中A-A处的剖视图；
图9a为本申请实施例提供的堆叠结构制备时的部件的俯视图；
图9b为图9a中A-A处的剖视图；
图10a为本申请实施例提供的堆叠结构制备时的部件的俯视图；
图10b为图10a中A-A处的剖视图；
图11a为本申请实施例提供的堆叠结构制备时的部件的俯视图；
图11b为图11a中A-A处的剖视图；
图12a为本申请实施例提供的堆叠结构制备时的部件的俯视图；
图12b为图12a中A-A处的剖视图；
图13～图17为本申请实施例的提供的堆叠结构制备流程图；
图18为本申请实施例提供的另一种堆叠结构的示意图；
图19为本申请实施例的提供的另一堆叠结构的结构示意图；
图20为本申请实施例提供的另一堆叠结构的俯视图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
本申请实施例提供的堆叠结构2应用于显示屏中，如图1所示，目前现有的显示屏panel由若干个显示像素组成，显示屏中具有多个显示像素2，多个显示像素2沿方向a成行排列，沿方向b成列排列。多个显示像素2位于显示屏的显示区域中，并通过显示像素2的发光实现显示屏的显示功能，多个显示像素2与显示屏的DDIC1(Display driving Integrated circuit，显示驱动器IC)相连，通过DDIC1的驱动信号对堆叠结构2的电压控制，从而实现整个显示屏的图像显示。
首先参考图2，图2示出了本申请实施例提供的堆叠结构的俯视图。本申请实施例提供的堆叠结构包括基板(图2中未示出)、线路层50、驱动芯片20及像素单元30，驱动芯片20及像素单元30组成堆叠结构中的发光单元。基板作为承载结构，为发光单元(驱动芯片20及像素单元30)提供了一个Base(支撑)的功能。基板可以采用具有一定支撑强度的材料制备而成，示例性的，基板的材质可以是玻璃，硅，蓝宝石，PI(聚酰亚胺，是主链含有酰亚氨基团的聚合物)等材质。线路层50与基板层叠，并与驱动芯片20及像素单元30连接，线路层50还与DDIC连接，以实现DDIC与发光单元之间的电连接。
驱动芯片20设置在基板上，如图2中所示的基板上承载一个驱动芯片20，驱动芯片20采用矩形形状，驱动芯片20的长度方向沿方向a。驱动芯片20可采用极微小驱动集成电路(Micro Integrated circuit，μIC)。
在本申请中不具体限定基板上承载的驱动芯片20的个数，如在一个可选的方案中，基板还可承载两个、三个、四个、五个等不同个数的驱动芯片20。作为一个具体的实施方案，显示屏中的所有堆叠结构可共用一个基板，显示屏中的驱动芯片20阵列排列在基板 上，驱动芯片20与基板之间电连接，并通过基板与DDIC连接。
像素单元30设置在驱动芯片20，如图2中所示的驱动芯片20承载两个像素单元30，两个像素单元30沿方向a方向排列。但是在本申请实施例中并不限定驱动芯片20上承载的像素单元30的个数，如驱动芯片20可承载一个像素单元30、三个像素单元30、四个像素单元30等不同个数的像素单元30。在驱动芯片20承载多个像素单元30时，多个像素单元30沿方向a成单排排列。
不同像素单元30的结构相同，每个像素单元30包括同层设置的三个子像素，三个子像素沿方向a单排排列。三个子像素分别为可发射红、蓝、绿三色的子像素。如图2中所示三个子像素分别为：可发射出红色光的第一子像素31a、可发射出蓝色光的第二子像素31b、可发射出绿色光的第三子像素31c。驱动芯片20通过控制三个子像素的工作状态，可控制像素单元30发射出不同颜色的光线。
在一个可选的实施方案中，像素单元30还可包括其他可实现显示屏发出不同颜色光的要求的子像素，如子像素采用单色或RGB三色的子像素。在本申请不作具体限定每个像素单元30中的子像素的个数，以及每个子像素发光的颜色，在具体设置时，可以根据需要设定子像素。
一并参考图3，图3示出了图2中所示的堆叠结构的侧视图，可直接体现本申请实施例提供的堆叠结构的具体堆叠情况。为方便描述定义了方向z：由显示屏内部指向显示屏的显示面的方向。基板10、驱动芯片20及像素单元沿方向z堆叠成三层结构，并且像素单元靠近显示屏的显示面。
基板10具有第一表面，第一表面设置有线路层50，线路层50具有连接DDIC、驱动芯片20及子像素31的电路层52。如图3中所示的线路层50包括支撑层51及电路层52，支撑层51可以采用不同的材质，示例性的，线路层50的材质可以是PI、环氧树脂等材质。电路层52可以在支撑层51内部多层布线，也可以在线路层50表面布线。作为一个可选的方案，可将电路层52直接设置在基板10上，通过基板10作为电路层52的支撑结构，从而无需额外制作支撑层51支撑电路层52，如采用印刷电路板或者带电路的基板。
驱动芯片20设置在线路层50背离第一表面的表面，具体可以通过胶卷黏接，也可以通过金属键合，也可以通过浆体类材料黏接的方式将驱动芯片20固定在线路层50的表面。驱动芯片20具有接线柱21，接线柱21设置在驱动芯片20背离线路层50的一面，且接线柱21与电路层52电连接。具体的，接线柱21通过连接线70与驱动芯片20的IO Pad22连接，如接线柱21可以通过RDL(再布线Redistribution Layer)与线路层50的IO(Input Output，电信号输入输出)Pad54进行连接，也可以用Fan out(扇出)线路与线路层50的IO Pad54进行连接，以实现驱动芯片20与电路层52的电连接。连接线70的材料可以是Cu pillar(铜柱凸块)，ITO(Information Technology Outsourcing，氧化铟锡)或Cu，Au等导电材料。
位于每个像素单元内的子像素31分别与线路层50及对应的驱动芯片20电连接并形成发光回路。具体的，子像素31通过转移工艺和bonding(邦定)工艺组装在驱动芯片20表面(背离第一表面的表面)。在具体设置上述子像素时，每个驱动芯片对应的子像素设置在对应的驱动芯片背离线路50的表面；且多个子像素在第一表面的垂直投影位于该驱动芯片在所述第一表面的垂直投影内。其中，上述对应指代的是驱动芯片与子像素形成电连接回路的对应关系。
结合图4及图5来说明一下子像素31的结构。在一个可选的实施方案中，子像素可采用极微小发光二极管(Micro Light-emitting diode，μLED)。本申请实施例提供的子像素31包括发光层312以及与发光层312分别连接的P端313及N端311。在图4中子像素31的P端313、发光层312及N端311层叠设置，且发光层312位于P端313及N端311之间。在采用上述垂直的层叠结构时，可减少子像素31的体积，子像素31的尺寸可以控制在5*5um～100*100um之间。如图5所示的另一种子像素31的结构，子像素31为倒装芯片型饥饿哦股：P端313、发光层312及N端311层叠设置，且P端313及N端311同层设置。图4及图5中所示的结构均可以应用在本申请实施例提供的堆叠结构中。在采用图4所示的子像素31应用在图3中所示的堆叠结构时，子像素31的P端313与驱动芯片的P Pad23连接。子像素31的N端311通过连接线60与线路层50的GND Pad53连接，如子像素31的N端311可通过RDL与线路层50的GND Pad53进行连接，也可以用Fan out线路与线路层50的GND Pad53进行连接，以实现子像素31与电路层52的电连接。连接线60的材料可以是Cu pillar，ITO或Cu，Au等导电材料。通过驱动芯片20与子像素31通过RDL工艺或Fan Out工艺与电路层52上与子像素31及驱动芯片20的对应电极(GND Pad53及IO Pad54)相连，实现整个堆叠结构的电路回路。在一个可选的示例中，也可采用子像素与电路层的IO Pad连接，而驱动芯片的IO Pad与电路层的GND Pad连接。同样可实现驱动芯片及子像素与电路层的电连接。
继续参考图3，堆叠结构还包括设置在基板上的分离层40，在本申请实施例中分离层40可以作为一个可选的层结构。线路层50设置在分离层40上，分离层40可与基板剥离。当发光单元(像素单元或驱动芯片20)检测到出现损坏时，可以用激光剥离的方法将分离层40进行分离，从而更换损坏的像素单元。上述的分离层40可以是激光感光材料(如氮化钾，氮化砷)或者化学腐蚀材料。应当理解的是，为保证可分离发光单元，线路层50设置有驱动芯片20的区域与驱动芯片20是绝缘的。即在驱动芯片20固定在线路层50时，驱动芯片20覆盖的区域未设置电路。作为一个可选的方案，线路层50设置有驱动芯片20的区域未设置内层布线。如图3中所示，第一区域53为驱动芯片20设置在线路层50时覆盖驱动芯片20的区域，由图3可看出，在通过分离层分离发光单元时，需要将与发光单元连接的线路层50一起分离，在第一区域53未内层布线时，可保证在切割线路层50时，与驱动芯片20一起剥离的线路层部分没有任何电路，再将修复后的驱动芯片20重新设置到基板上时，可以直接将驱动芯片20放置在原来的位置。
在一个可选的方案中，堆叠结构还包括与每个驱动芯片20一一对应的第二封装层80，每个第二封装层80将对应的驱动芯片20及多个子像素31封装，以保护驱动芯片20及子像素31。示例性的，第二封装层80为梯形结构，并包裹住驱动芯片20及子像素31。第二封装层80为透明塑封料制备而成以便透过子像素31发出的光线。示例性的，第二封装层80的材料可以是COF(Chip On Flex，or，Chip On Film，覆晶薄膜)材料，也可是透明光刻胶材料或其他透明环氧树脂材料。在堆叠结构具有第二封装层80时，驱动芯片20及子像素31与电路层连接的连接线可设置在第二封装层80内，并通过第二封装层80将其与驱动芯片20及子像素31一起封装，也可如图3中所示的连接线贴附在第二封装层80表面。在发光单元包含第二封装层80时，线路层50的电路层51在第二封装层80对应的区域未设置电路，以保证在切割线路层时，不会损坏电路层。
在一个可选的方案中，接线柱21可以采用金属过孔的方式设置在第二封装层80，或 者也可采用柱体结构的方式。具体制备时，可在第二封装层80开设过孔，可以通过镀金属层形成金属过孔作为接线柱，也可在过孔中填充金属材料形成柱体结构作为接线柱。
在一个可选的方案中，驱动芯片20上除上述的子像素31外，还可摆放显示屏的其他器件或芯片，以使得堆叠结构集成更多功能元器件，降低非显示器件占用基板上的面积。
本申请实施例提供的堆叠结构在采用驱动芯片与像素单元堆叠时，可有效的降低发光单元占用基板上的面积，为直观理解其效果，将本申请实施例提供的堆叠结构与现有技术中的堆叠结构进行对比。下面结合图6及图7对本申请的堆叠结构与现有技术中的堆叠结构进行说明。为方便理解，以长度方向上的对比来说明两种堆叠结构的区别。
图6示出了本申请实施例提供的堆叠结构的侧视图。堆叠结构的基板10的长度为H1，驱动芯片20的长度为H2，像素单元的长度(子像素31的长度)为H3。发光单元占用的基板10上的总长度为H2：发光单元中的发光部分(像素单元)占用的长度为H3，非发光部分占用的长度为H2-H3。由此可看出，在基板10的长度方向上，发光单元设置的个数可以根据H1与H2的值来确定。
图7示出了现有技术中的堆叠结构的侧视图。堆叠结构的基板3的长度为H4，驱动芯片4的长度为H2，像素单元的长度(子像素6的长度)为H3。由图7可看出，在驱动芯片4及像素单元同层设置在基板3上时，发光单元占用的基板3上的总长度为H3+H2(祛除部件之间间隙后的尺寸)，其中，发光单元的发光部分(像素单元)占用的长度为H3，非发光部分占用的尺寸为H2。由此可看出，在基板3长度方向上，发光单元设置的个数可根据H4及(H2+H3)的值来确定。
对比图6及图7可以看出，在相同尺寸的基板上，图7中的发光单元占用的尺寸大于图6中的发光单元占用的尺寸。并且在图6及图7中所示的发光单元中，图7中所示的发光单元中的发光部分占比H3/(H2+H3)小于图6中所示的发光单元中的发光部分占比H3/H2，同时，图7中的发光单元的尺寸H2+H3大于图6中所示的发光单元的尺寸H2，因此，在相同尺寸的基板，可以设置更多的图6中所示的发光单元。在应用在显示屏内时，相同显示区域中，可增大像素单元的个数，从而提高显示屏的显示精度，提高显示效果。
为方便理解本申请实施例提供的堆叠结构，下面结合附图详细说明一下其具体的制备方法。
步骤001：提供基板。
如图8a及图8b所示，图8a示出了基板10的俯视图，图8b示出了图8a中A-A处的剖视图。基板10上已经设置了线路层50及分离层40。其中，线路层50中连接DDIC控制信号的走线及pad(图中未示出)已加工完成；线路层50与基板10之间的分离层40采用激光牺牲层材料。线路层50具有IO Pad54及GND Pad53，其中，IOpad54为3um厚度的In制备而成，GND Pad53为0.05um厚度的Au制备而成，DDIC走线连接pad镀层可采用相同镀层结构。
步骤002：设置驱动芯片。
如图9a及图9b所示，图9a示出了部件的俯视图，图9b示出了图9a中A-A处的剖视图。图9a及图9b中的部分标号可参考图8a及图8b中的相同标号。驱动芯片20通过转移工艺，并使用Die Attach(芯片贴装)工艺组装到线路层50上。其中转移工艺依据晶圆的制作工艺，可以采用激光转移或物理转移方式。驱动芯片20使用film或adhesive Die Attach(粘模连接)固定在线路上，并且驱动芯片20的IO Pad22及P Pad23朝上(以图 9b中基板10的放置方向为参考方向)。
步骤003：设置子像素。
如图10a及图10b所示，图10a示出了部件的俯视图，图10b示出了图10a中A-A处的剖视图。图10a及图10b中的部分标号可参考图9a及图9b中的相同标号。子像素31采用如图4中所示的垂直结构。子像素31通过转移工艺和bonding工艺组装在驱动芯片20表面；其中子像素31的P端(正极)与驱动芯片20的P Pad23连接。
步骤004：制备封装层。
如图11a及图11b所示，图11a示出了部件的俯视图，图11b示出了图11a中A-A处的剖视图。图11a及图11b中的部分标号可参考图10a及图10b中的相同标号。通过PLN(Planarization)打印工艺将子像素31及驱动芯片20封装，形成第二封装层80，通过光刻工艺露出子像素31的负极(N端)及驱动芯片20的IO Pad22。其中，第二封装层80的材料为透明材料，具体可以采用COF(Chip On Flex，or，Chip On Film，常称覆晶薄膜)材料，也可是透明光刻胶材料或其他透明环氧树脂材料。
步骤005：Fan out(扇出)及走线。
如图12a及图12b所示，图12a示出了部件的俯视图，图12b示出了图12a中A-A处的剖视图，图12a及图12b中的部分标号可参考图11a及图11b中的相同标号。通过fan out工艺将驱动芯片20的IO pad22走线到模组表面信号pad(具体通过设置接线柱21)；并将每个子像素31的负极连接在接线层50的GND Pad54；将驱动芯片20的地与子像素31的地连接，并与显示屏上的地连接，实现所有信号pin导通；其中驱动芯片20与线路层50的连接走线可使用μBump(微凸块)工艺，可以是Cu或Al或ITO线路工艺。
步骤006：测试。
具体的，通过DDIC对堆叠结构进行点亮测试，若有不良的发光单元，则定位不良发光单元的位置。
步骤007：不良发光单元切割。
如图13所示，图13中的部分编号可参考图12b中的相同标号。通过激光将不良发光单元进行切割。激光切线路层50及分离层40，使得不良发光单元被割裂开。
步骤008：不良发光单元剔除：
如图14所示，图14中的部分编号可参考图12b中的相同标号。通过激光烧蚀基板10表面的分离层40，将不良发光单元从基板10上剔除。
步骤009：不良位置的发光单元转移及固定：
如图15所示，图15中的部分编号可参考图12b中的相同标号。通过维修设备将良好的发光单元转移到空白位置，通过加热或UV(ultraviolet，利用紫外线的)方式固化固定到基板10上。
步骤010：维修发光单元四周缝隙填平。
如图16所示，图16中的部分编号可参考图12b中的相同标号。通过打印设备将修补后的发光单元的四周空隙位置填平，固化。
步骤011：走线实现发光单元与基板的线路层连接。
如图17所示，图17中的部分编号可参考图12b中的相同标号。通过CVD(Chemical Vapor Deposition，化学气相沉积)或打印银浆方案将发光单元上走线与线路层50上走线连接实现导通。
由上述描述可以看出，在采用像素单元与驱动芯片层叠设置的方式时，驱动芯片和像素单元可位于不同的层，基板上可布置更多的驱动芯片，并且驱动芯片上也可布置更多的像素单元，整个堆叠结构可形成一整层的像素单元，驱动芯片不会占用像素单元的布置区域，提高了像素单元布置的个数，进而提高了显示屏的显示效果。同时，通过采用分离层可以在制备时对堆叠结构上的发光单元进行更换，提高了堆叠结构在使用时的可靠性。
在采用子像素直接设置在驱动芯片20时，子像素可呈单排排列，也可呈双排排列，如图18所示的每个驱动芯片20上承载两排子像素31，但是每个子像素在第一表面的垂直投影位于该驱动芯片在第一表面的垂直投影内；其中，第一表面为基板朝向线路层的表面。
图19示例出了本申请实施例提供的另一种堆叠结构，图19中的部分标号可参考图3中的相同标号。与图3中所示的堆叠结构的区别在于子像素31的设置位置发生了改变。图19所示的堆叠结构包括了第一封装层90。基板10上的每个驱动芯片20一一对应一个第一封装层90，每个第一封装层90将对应的驱动芯片20封装，每个驱动芯片20对应的多个子像素31设置在第一封装层90。
在一个可选的方案中，多个子像素31在第一表面的垂直投影位于该驱动芯片20在所述第一表面的垂直投影内；第一表面为基板10朝向线路层50的表面。
如图19中所示的第一封装层90采用长方体形的矩形结构。在子像素31设置在第一封装层90时，相比图3中所示的子像素31直接设置在驱动芯片20上，图19所示的子像素31的设置方式，增大了每个驱动芯片20承载的子像素31的个数。为方便理解两者的区别，参考图2及图20，图20示例出了驱动芯片承载多个像素单元30的俯视图。在图2中，受到驱动芯片20尺寸的影响，驱动芯片20仅能设置单排排列的像素单元30。而在图20中所示的结构中，由于通过第一封装层90增加了像素单元30的设置面积，因此，驱动芯片20可对应有多个像素单元30，且多个像素单元30排列成两排设置，增加了驱动芯片20对应的像素单元30的个数。如图20中所示的，四个像素单元30分布在一个驱动芯片20的四角，通过走线与驱动芯片20相连，可以确保一个驱动芯片20控制4个像素单元30。从而可降低驱动芯片20的设置个数，同时也可提高显示屏中像素单元30的个数，改善显示屏的显示效果。
在图20中，每个驱动芯片20设置有三排连接端口24、25、26，中间一排连接端口25用于连接接线柱，两侧的两排连接端口24、26分别用于连接像素单元30中的子像素31。在实现电连接时，中间的接线柱与线路层50的IO Pad54连接，每个子像素31与线路层50的GND Pad53连接。在图20中，每个驱动芯片20的子像素31并联后与线路层50连接。但是图20中仅仅为一个具体的示例，还可采用其他的方式连接，如每个驱动芯片20的子像素31分别与线路层50连接，此时可单独控制不同颜色的子像素31发光。另外，应当理解的是，上述仅仅示例了具体的子像素31与线路层50的连接方式，本申请实施例提供的堆叠结构还可采用其他的连接方式实现线路层50对子像素31的控制，在本申请中不做具体的限定。
图19所示的堆叠结构的制备方法可参考上述图3中所示的堆叠结构的制备方法，唯一的区别在于，增加了第一封装层90的制备过程。在制备驱动芯片20后，可通过PLN打印工艺将驱动芯片20封装，通过光刻工艺露出驱动芯片20的IO Pad及P Pad。PLN材料可以为透明材料也可以为非透明材料。在采用透明材料时，第一封装层90的材料可采用与第二封装层相同的材料，如采用COF材料，也可是透明光刻胶材料或其他透明环氧树脂 材料。制备子像素31时，将子像素31制备到第一封装层90上，并通过走线将子像素31与驱动芯片20连接。
通过上述描述可以看出，本申请实施例提供的堆叠结构中，发光单元的子像素堆叠在驱动芯片20上方，分成两层摆放，对于显示屏内有限空间，可以将RGB三色像素点(发光单元)尺寸做最小至30*30um。相比于传统的非堆叠摆放，RGB三色像素点尺寸最小至50*50um。另外，通过分离层可以用激光或化学腐蚀方式反应，将损坏的像素模组剥离，GND，IO Pad电路可方便维修，便于将损坏的像素模组用完好的像素模组替换。
在显示屏中，高ppi(Pixels Per Inch，每英寸的像素数量)排布条件下，需要选择更小尺寸的子像素，对应的，Flip chip(倒装芯片)型的子像素的两个pad(N端及P端)间距将进一步缩小。在此情景下进行bonding，易发生由于焊盘侧向溢出而导致的短路。而采用本方案采用垂直型的子像素，两个电极(N端及P端)分别bonding，避免了上述情况。另外，本申请实施例中采用垂直型的子像素，其在保证发光面积一致的情况下(Flipchip型子像素的发光面积只占其总面积～50％左右；垂直型的子像素发光面积～100％)，减小的器件面积。结果为在同样的ppi以及亮度下，子像素所占面积更小，利用此特性可尽量提高极限ppi；在未达极限ppi情景下可实现透明显示或者集成其他微型元器件。
本申请实施例还提供了一种显示屏，该显示屏包括：壳体，以及设置在所述壳体内上述任一项所述的堆叠结构。由上述描述可以看出，在采用像素单元与驱动芯片层叠设置的方式时，驱动芯片和像素单元可位于不同的层，基板上可布置更多的驱动芯片，并且驱动芯片上也可布置更多的像素单元，整个堆叠结构，可形成一整层的像素单元，驱动芯片不会占用像素单元的布置区域，提高了像素单元布置的个数，进而提高了显示屏的显示效果。
本申请实施例还提供了一种显示装置，该显示装置包括本体以及设置在所述本体内的上述任一项所述的堆叠结构。由上述描述可以看出，在采用像素单元与驱动芯片层叠设置的方式时，驱动芯片和像素单元可位于不同的层，基板上可布置更多的驱动芯片，并且驱动芯片上也可布置更多的像素单元，整个堆叠结构，可形成一整层的像素单元，驱动芯片不会占用像素单元的布置区域，提高了像素单元布置的个数，进而提高了显示屏的显示效果。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (12)

  1. 一种堆叠结构，其特征在于，包括：层叠设置的基板、至少一个驱动芯片及与每个驱动芯片对应的至少一个像素单元；其中，
    所述基板具有第一表面；所述第一表面设置有线路层；
    每个驱动芯片设置在所述线路层背离所述第一表面的表面；
    每个像素单元与对应的驱动芯片层叠设置；
    位于每个像素单元内的子像素分别与所述线路层及对应的驱动芯片电连接并形成发光回路。
  2. 根据权利要求1所述的堆叠结构，其特征在于，所述线路层设置有所述驱动芯片的区域与所述驱动芯片是绝缘的。
  3. 根据权利要求2所述的堆叠结构，其特征在于，所述每个驱动芯片背离所述线路层的一面设置有与接线柱，所述接线柱与所述驱动芯片和线路层电连接。
  4. 根据权利要求1～3任一项所述的堆叠结构，其特征在于，所述每个驱动芯片对应的子像素设置在对应的驱动芯片背离所述线路层的表面。
  5. 根据权利要求4所述的堆叠结构，其特征在于，还包括与所述每个驱动芯片一一对应的第一封装层，每个第一封装层将对应的驱动芯片封装；
    所述每个驱动芯片对应的子像素设置在所述第一封装层。
  6. 根据权利要求1～5任一项所述的堆叠结构，其特征在于，还包括与每个驱动芯片一一对应的第二封装层，每个第二封装层将对应的所述驱动芯片及所述多个子像素封装。
  7. 根据权利要求1～6任一项所述的堆叠结构，其特征在于，还包括分离层，所述分离层设置在所述线路层与所述基板之间。
  8. 根据权利要求1～7任一项所述的堆叠结构，其特征在于，每个子像素包括发光层以及与所述发光层分别连接的P端及N端；其中，所述P端与对应的驱动芯片连接，所述N端与所述线路层连接；或，所述P端与所述线路层连接，所述N端与对应的驱动芯片连接。
  9. 根据权利要求8所述的堆叠结构，其特征在于，所述P端、所述发光层及所述N端层叠设置，且所述发光层位于所述P端及所述N端之间。
  10. 根据权利要求8所述的堆叠结构，其特征在于，所述P端、所述发光层及所述N端层叠设置，且所述P端及所述N端同层设置。
  11. 一种显示屏，其特征在于，包括：壳体，以及设置在所述壳体内的如权利要求1～10任一项所述的堆叠结构。
  12. 一种显示装置，其特征在于，包括本体以及设置在所述本体内的如权利要求1～10任一项所述的堆叠结构。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116995072A (zh) * 2023-09-27 2023-11-03 惠科股份有限公司 显示背板及其制作方法和转移方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115206952B (zh) * 2022-07-27 2023-03-17 北京数字光芯集成电路设计有限公司 采用堆叠式封装的Micro-LED微显示芯片
CN116469971B (zh) * 2023-04-18 2023-09-15 上海聚跃检测技术有限公司 一种集成电路堆叠芯片的封装方法及装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201910207U (zh) * 2010-11-22 2011-07-27 金建电子有限公司 一种高密度全彩led显示板
CN103545304A (zh) * 2013-11-01 2014-01-29 广东威创视讯科技股份有限公司 一种发光二极管和驱动芯片的封装结构及封装方法
CN108701691A (zh) * 2016-02-18 2018-10-23 苹果公司 用于微驱动器和微led的底板结构和方法
US20190096864A1 (en) * 2015-09-24 2019-03-28 Apple Inc. Display with embedded pixel driver chips
CN109768027A (zh) * 2019-01-29 2019-05-17 福州大学 一种Micro-LED显示屏的结构和制造方法
CN110391261A (zh) * 2018-04-18 2019-10-29 英属开曼群岛商镎创科技股份有限公司 微型发光二极管显示面板
CN110600463A (zh) * 2019-10-09 2019-12-20 深圳韦侨顺光电有限公司 基于芯片堆叠的集成封装led显示面板
CN210167355U (zh) * 2019-07-10 2020-03-20 深圳市兆驰节能照明股份有限公司 透明显示屏及其led光源

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4951018B2 (ja) 2009-03-30 2012-06-13 株式会社東芝 半導体装置の製造方法
KR101711961B1 (ko) 2010-09-10 2017-03-03 삼성전자주식회사 발광 디바이스
JP5966412B2 (ja) 2011-04-08 2016-08-10 ソニー株式会社 画素チップ、表示パネル、照明パネル、表示装置および照明装置
US8996212B2 (en) * 2011-07-26 2015-03-31 Gogoro Inc. Apparatus, method and article for providing vehicle diagnostic data
US9159700B2 (en) 2012-12-10 2015-10-13 LuxVue Technology Corporation Active matrix emissive micro LED display
US9367094B2 (en) * 2013-12-17 2016-06-14 Apple Inc. Display module and system applications
US9991423B2 (en) 2014-06-18 2018-06-05 X-Celeprint Limited Micro assembled LED displays and lighting elements
GB201418810D0 (en) * 2014-10-22 2014-12-03 Infiniled Ltd Display
CN205016161U (zh) * 2015-08-06 2016-02-03 林谊 Led像素点、发光组件、发光面板和显示屏
RU2690769C1 (ru) 2015-08-06 2019-06-05 И Линь Светодиодный пиксельный элемент, светоизлучающий компонент, светоизлучающая панель и экран дисплея
US12015103B2 (en) * 2017-01-10 2024-06-18 PlayNitride Display Co., Ltd. Micro light emitting diode display panel with option of choosing to emit light both or respectively of light-emitting regions
TWI646680B (zh) * 2017-01-10 2019-01-01 英屬開曼群島商錼創科技股份有限公司 微型發光二極體晶片以及顯示面板
CN106816502B (zh) * 2017-04-12 2019-04-02 京东方科技集团股份有限公司 一种led芯片、led发光基板、显示装置及彩色显示控制方法
US10319266B1 (en) * 2017-04-24 2019-06-11 Facebook Technologies, Llc Display panel with non-visible light detection
KR102078643B1 (ko) * 2018-04-04 2020-04-07 (주)라이타이저 원칩 타입의 발광 다이오드를 이용한 디스플레이 장치 및 그 제조 방법
CN108987382A (zh) 2018-07-27 2018-12-11 京东方科技集团股份有限公司 一种电致发光器件及其制作方法
TWI676851B (zh) * 2018-08-22 2019-11-11 隆達電子股份有限公司 畫素陣列封裝結構及顯示面板
CN109360838B (zh) * 2018-09-26 2022-04-26 京东方科技集团股份有限公司 一种感控显示面板及感控显示装置
CN110277059B (zh) * 2019-07-01 2021-04-23 武汉天马微电子有限公司 驱动芯片及其控制方法、显示装置
CN110416171A (zh) * 2019-09-05 2019-11-05 东莞市欧思科光电科技有限公司 一体化光电显示单元及其制作工艺、光电显示装置
CN112700749B (zh) * 2021-01-04 2022-04-26 武汉天马微电子有限公司 显示面板的驱动方法及其驱动装置、显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201910207U (zh) * 2010-11-22 2011-07-27 金建电子有限公司 一种高密度全彩led显示板
CN103545304A (zh) * 2013-11-01 2014-01-29 广东威创视讯科技股份有限公司 一种发光二极管和驱动芯片的封装结构及封装方法
US20190096864A1 (en) * 2015-09-24 2019-03-28 Apple Inc. Display with embedded pixel driver chips
CN108701691A (zh) * 2016-02-18 2018-10-23 苹果公司 用于微驱动器和微led的底板结构和方法
CN110391261A (zh) * 2018-04-18 2019-10-29 英属开曼群岛商镎创科技股份有限公司 微型发光二极管显示面板
CN109768027A (zh) * 2019-01-29 2019-05-17 福州大学 一种Micro-LED显示屏的结构和制造方法
CN210167355U (zh) * 2019-07-10 2020-03-20 深圳市兆驰节能照明股份有限公司 透明显示屏及其led光源
CN110600463A (zh) * 2019-10-09 2019-12-20 深圳韦侨顺光电有限公司 基于芯片堆叠的集成封装led显示面板

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4131385A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116995072A (zh) * 2023-09-27 2023-11-03 惠科股份有限公司 显示背板及其制作方法和转移方法
CN116995072B (zh) * 2023-09-27 2023-12-08 惠科股份有限公司 显示背板及其制作方法和转移方法

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