CN108231555B - 蚀刻方法和基板处理系统 - Google Patents
蚀刻方法和基板处理系统 Download PDFInfo
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Abstract
本发明提供一种蚀刻方法和基板处理系统。该蚀刻方法能够防止从基板制造的器件受到损伤。对在表层形成有氧化硅膜(32)的晶圆(W)实施去除该氧化硅膜(32)的第1突破处理,在第1突破处理之后实施对多晶硅层(31)进行蚀刻的第1主蚀刻处理,在第1主蚀刻处理之后实施将暴露的氧化硅膜(32)去除的第2突破处理,在第2突破处理之后实施对剩余的多晶硅层(31)进行蚀刻的第2主蚀刻处理。
Description
技术领域
本发明涉及蚀刻方法和执行该方法的基板处理系统。
背景技术
在用于制造电子器件的具有预定的图案的晶圆(以下称为“图案晶圆”。)中,有时在多晶硅层的表面存在通过CMP(化学机械抛光,Chemical Mechanical Polishing)处理等而产生的氧化硅膜。氧化硅膜在对多晶硅层进行蚀刻之际作为掩模发挥功能,阻碍多晶硅层的蚀刻,因此,在多晶硅层的蚀刻之前对图案晶圆实施用于去除氧化硅膜的蚀刻处理。将这样的用于去除氧化硅膜的蚀刻处理称为突破处理。
在实施了突破处理的图案晶圆中,接着突破处理实施用于去除多晶硅层的蚀刻处理(以下称为“主蚀刻处理”。),但存在在主蚀刻处理中多晶硅层未完全去除的情况,在图案晶圆残留有由硅构成的残渣。
为了去除这样的残渣,在多晶硅层被大致去除之后,也进行继续主蚀刻处理的过蚀刻处理。另外,也提出了如下方案:在主蚀刻处理后,为了去除残渣,进行等离子体清洁气体的导入(参照例如专利文献1。);为了使残渣变质成水溶性而去除,对图案晶圆实施气体等离子体处理(参照例如专利文献2。)。
现有技术文献
专利文献
专利文献1:日本特表平7-508313号公报
专利文献2:日本特开平11-260785号公报
发明内容
发明要解决的问题
然而,若进行过蚀刻处理、或主蚀刻处理后的等离子体清洁气体的导入、气体等离子体处理,则电子器件有可能受到损伤。
本发明的目的在于提供一种能够防止从基板制造的器件受到损伤的蚀刻方法和基板处理系统。
用于解决问题的方案
为了达成上述目的,本发明的蚀刻方法是将在用于制造电子器件的基板形成的被处理层去除的蚀刻方法,其特征在于,该蚀刻方法具有:第1突破处理,其将在所述被处理层的表面形成的氧化膜去除;第1主蚀刻处理,其在所述第1突破处理之后对所述被处理层进行蚀刻;第2突破处理,其在所述第1主蚀刻处理之后将暴露的氧化膜去除;第2主蚀刻处理,其在所述第2突破处理之后对所述被处理层进行蚀刻。
为了达成上述目的,本发明的基板处理系统是对用于制造电子器件的基板实施蚀刻处理的基板处理系统,其特征在于,具备:第1突破单元,其将在所述基板的被处理层的表面形成的氧化膜去除;第1主蚀刻单元,其在所述第1突破单元中的去除后对所述被处理层进行蚀刻;第2突破单元,其在所述第1主蚀刻单元中的蚀刻后将暴露的氧化膜去除;第2主蚀刻单元,其在所述第2突破单元中的去除后对所述被处理层进行蚀刻。
发明的效果
根据本发明,对被处理层进行了蚀刻后暴露的氧化膜被去除,因此,进入了被处理层的氧化膜能够防止在接下来的被处理层的蚀刻中作为掩模发挥功能,因而,能够防止产生未被去除的被处理物。即能够防止残渣的产生,因此,能够无需进行过蚀刻处理、被处理层的蚀刻后的等离子体清洁气体的导入等,因而,能够防止从基板制造的器件受到损伤。
附图说明
图1是概略地表示本发明的实施方式的基板处理系统的结构的俯视图。
图2是表示在执行以往的蚀刻方法之后残存的残渣的形态的剖视图。
图3是用于说明以往的蚀刻方法中的残渣的产生的机理的工序图。
图4是表示作为本实施方式的蚀刻方法的多晶硅层的去除方法的工序图。
图5是示意性地表示在执行了以往的多晶硅层的去除方法和图4的多晶硅层的去除方法之后观察到的沟槽的底部处的残渣的残存形态的图。
附图标记说明
W、晶圆;10、基板处理系统;13、工艺模块;28、沟槽;29、残渣;31、多晶硅层;32、氧化硅膜。
具体实施方式
以下,参照附图详细地说明本发明的实施方式。
图1是概略地表示本发明的实施方式的基板处理系统的结构的俯视图。此外,在图1中,为了容易理解,透视地表示内部的结构的一部分。
在图1中,基板处理系统10具备:晶圆保管部11,其保管多个晶圆W;作为输送室的传递模块12,其同时输送两张晶圆W;多个工艺模块13(第1突破单元、第1主蚀刻单元、第2突破单元、第2主蚀刻单元),其对从传递模块12输入来的晶圆W实施突破处理、主蚀刻处理。各工艺模块13和传递模块12的内部维持成真空气氛。
在基板处理系统10中,保管到晶圆保管部11的晶圆W由传递模块12所内置的输送臂14输送,将晶圆W逐张载置于配置到工艺模块13的内部的两个载置台15中的每一个。接下来,在基板处理系统10中,于在工艺模块13中对载置到载置台15的各晶圆W实施了突破处理、蚀刻处理之后,处理完毕的晶圆W由输送臂14向晶圆保管部11输出。
晶圆保管部11具有:多个加载部17,其作为前开式晶圆传送盒16的载置台,该前开式晶圆传送盒16是保管多个晶圆W的容器;装载模块18,其从载置到各加载部17的前开式晶圆传送盒16接收所保管的晶圆W,或者将在工艺模块13中实施了预定的处理的晶圆W交给前开式晶圆传送盒16;两个加载互锁模块19,其暂时保持晶圆W,以便在装载模块18与传递模块12之间交接晶圆W;冷藏室20,其对实施了PHT处理的晶圆W进行冷却。
装载模块18由内部是大气压气氛的矩形的壳体构成,在构成该矩形的长边的一侧面并列设置有多个加载部17。而且,装载模块18在内部中具有可沿着该矩形的长度方向移动的输送臂(未图示)。该输送臂将晶圆W从载置到各加载部17的前开式晶圆传送盒16向加载互锁模块19输入,或者将晶圆W从加载互锁模块19向各前开式晶圆传送盒16输出。
各加载互锁模块19将收容到被载置于大气压气氛的各加载部17的前开式晶圆传送盒16的晶圆W交给内部处于真空气氛的工艺模块13,因此,暂时保持晶圆W。各加载互锁模块19具有保持两张晶圆W的缓冲板21。另外,各加载互锁模块19具有用于相对于装载模块18确保气密性的闸阀22a和用于相对于传递模块12确保气密性的闸阀22b。而且,未图示的气体导入系统和气体排气系统借助配管与加载互锁模块19连接,加载互锁模块19的内部被控制成大气压气氛或真空气氛。
传递模块12将未处理的晶圆W从晶圆保管部11向工艺模块13输入,将处理完毕的晶圆W从工艺模块13向晶圆保管部11输出。传递模块12由内部是真空气氛的矩形的壳体构成,包括:两个输送臂14,其保持两张晶圆W而使两张晶圆W移动;旋转台23,其将各输送臂14支承成可旋转;旋转载置台24,其搭载有旋转台23;导轨25,其将旋转载置台24引导成可沿着传递模块12的长度方向移动。另外,传递模块12经由闸阀22a、22b、进一步经由随后叙述的各闸阀26与晶圆保管部11的加载互锁模块19、以及各工艺模块13连接。在传递模块12中,输送臂14从加载互锁模块19将两张晶圆W向各工艺模块13输送,将实施了处理的两张晶圆W从各工艺模块13向其他工艺模块13、加载互锁模块19输出。
在基板处理系统10中,各工艺模块13执行突破处理、主蚀刻处理。具体而言,在突破处理中,一个工艺模块13执行COR(化学氧化去除,Chemical Oxide Removal)处理,另一工艺模块13执行PHT(后热处理,Post Heat Treatment)处理。在COR处理中,使导入到工艺模块13的内部的处理气体、例如HF气体和NH3气体吸附于晶圆W而使在多晶硅层的表面存在的氧化硅膜和处理气体反应,生成作为生成物的AFS(氟硅酸铵)。另外,在PHT处理中,对晶圆W进行加热而使在晶圆W生成的AFS气化并去除。此外,在COR处理和PHT处理中的的任一个中都不使用等离子体。而且,在主蚀刻处理中,一个工艺模块13利用从处理气体生成的等离子体中、例如从F2气体生成的等离子体中的氟自由基对晶圆W的多晶硅层进行蚀刻。此外,在主蚀刻处理中,除了F2气体之外,还将NH3气体、N2气体向一个工艺模块13的内部导入。也包括这些突破处理、主蚀刻处理中的动作在内、基板处理系统10的各构成要素的动作由控制器27按照预定的程序控制。
图2是表示在执行以往的蚀刻方法之后残存的残渣的形态的剖视图。
若对晶圆W实施以往的突破处理和主蚀刻处理,则如图2所示,确认到多晶硅层被去除而形成的构造、例如在沟槽28的底部局部地残存有硅的残渣29。此时,即使在沟槽28的底部形成有多个翅片30,残渣29也与各翅片30的位置没有关系地残存。
针对在对晶圆W实施了突破处理和主蚀刻处理之后残留硅的残渣的理由,本发明人对以下的机理进行了推测。具体而言,在多晶硅层31(被处理层)形成于晶圆W上之后,若对包括该多晶硅层31的晶圆W的表层实施CMP处理,则多晶硅层31的硅与研磨剂、大气中的氧反应而氧化硅膜32形成于晶圆W的表层。在此,在多晶硅层31的表面附近易于产生硅的晶种(块),氧化硅膜32进入各晶种的边界(图3的(A))。
之后,若对晶圆W实施突破处理,则在晶圆W的表层形成的氧化硅膜32能够与处理气体接触,因此,变质成AFS而被去除,但进入到各晶种的间隙的氧化硅膜32难以与处理气体接触,因此,不会变质成AFS而残存(图3的(B))。
接下来,若对晶圆W实施主蚀刻处理,则随着多晶硅层31的蚀刻的进展,进入到各晶种的间隙的氧化硅膜32暴露,但该暴露的氧化硅膜32作为氧化膜掩模33发挥功能,局部地阻碍以后的多晶硅层31的蚀刻。即、在多晶硅层31中,在被氧化膜掩模33覆盖的部分的蚀刻速度与没有被氧化膜掩模33覆盖的部分的蚀刻速度之间产生无法忽视的差异,多晶硅层31没有被同样地蚀刻(图3的(C))。其结果,即使多晶硅层31被大致去除,与被氧化膜掩模33覆盖的部分相对应地产生硅的残渣29(图3的(D))。
尤其是,各晶种的间隙与各翅片30的位置没有关系地产生,各氧化膜掩模33以与各晶种的间隙相对应的方式产生,因此,各残渣29以与各翅片30的位置没有关系地残存而与各晶种的间隙相对应的方式产生。在本发明的实施方式中,基于该机理,对晶圆W实施突破处理和主蚀刻处理,以便去除各氧化膜掩模33。
图4是表示作为本实施方式的蚀刻方法的多晶硅层的去除方法的工序图。
首先,对在表层形成有氧化硅膜32的晶圆W实施第1突破处理(图4的(A))。此时,将执行COR处理的工艺模块13的内部的压力设定成例如300mTorr,将HF气体向工艺模块13的内部的导入量设定成例如140sccm~160sccm,将NH3气体向工艺模块13的内部的导入量设定成例如140sccm~160sccm,将第1突破处理设定成例如40秒~90秒。在第1突破处理中,在晶圆W的表层形成的氧化硅膜32与处理气体接触,因此,变质成AFS而被去除,但进入到各晶种的间隙的氧化硅膜32难以与处理气体接触,因此,不变质成AFS而残存(图4的(B))。
接下来,对晶圆W实施第1主蚀刻处理。此时,将执行第1主蚀刻处理的工艺模块13的内部的压力设定成例如1Torr~1.6Torr,将F2气体向工艺模块13的内部的导入量设定成例如300sccm~1050sccm,将NH3气体向工艺模块13的内部的导入量设定成例如10sccm~35sccm,将N2气体向工艺模块13的内部的导入量设定成例如180sccm~210sccm,将晶圆W的温度设定成例如80℃~120℃。第1主蚀刻处理的执行时间设定得比较短,因此,仅多晶硅层31的表面附近被蚀刻,作为结果,进入各晶种的间隙的氧化硅膜32暴露,在多晶硅层31的表面形成各氧化膜掩模33(图3的(C))。
接下来,对晶圆W实施第2突破处理(图4的(C))。此时的COR处理的执行条件设定成与第1突破处理的执行条件相同,但多晶硅层31的表面的各氧化膜掩模33与处理气体接触,因此,变质成AFS而被去除(图4的(D))。
接下来,对晶圆W实施第2主蚀刻处理。此时的执行条件设定成与第1主蚀刻处理的执行条件相同,但执行时间设定得比第1主蚀刻处理的执行时间长。因而,第2主蚀刻处理中的多晶硅层31的蚀刻量比第1主蚀刻处理中的多晶硅层31的蚀刻量多。此时,也与第1主蚀刻处理同样地多晶硅层31被蚀刻,但在第2突破处理中各氧化膜掩模33被去除,因此,多晶硅层31的蚀刻不会被局部地阻碍,多晶硅层31被同样地蚀刻。其结果,在多晶硅层31被去除之后残渣29不会局部地残存于沟槽28的底部(图4的(E))。此外,在第2主蚀刻处理中,多晶硅层31的蚀刻和来自工艺模块13的内部的排气被交替地进行,对被蚀刻而在工艺模块13的内部浮游的硅化合物等阻碍以后的多晶硅层31的蚀刻进行抑制。
根据上述的多晶硅层的去除方法,在仅对多晶硅层31的表面附近进行了蚀刻之后暴露的氧化硅膜32被去除,因此,能够防止进入到多晶硅层31的各晶种的间隙的氧化硅膜32在多晶硅层31的表面附近的蚀刻后暴露而作为氧化膜掩模33发挥功能,因而,能够防止在第2主蚀刻处理中残渣29局部地残存于沟槽28的底部。因而,能够无需进行过蚀刻处理、多晶硅层31的蚀刻后的等离子体清洁气体的导入等,因而,能够防止从晶圆W制造的器件受到损伤。
另外,在上述的多晶硅层的去除方法中,第2主蚀刻处理中的多晶硅层31的蚀刻量比第1主蚀刻处理中的多晶硅层31的蚀刻量多。即、第1主蚀刻处理中的多晶硅层31的蚀刻量比第2主蚀刻处理中的多晶硅层31的蚀刻量少。若第1主蚀刻处理中的多晶硅层31的蚀刻量较多,则暴露的氧化硅膜32在第1主蚀刻处理中作为掩模发挥功能,多晶硅层31的形状有可能紊乱,通过减少第1主蚀刻处理中的多晶硅层31的蚀刻量,能够使进入到多晶硅层31的各晶种的间隙的氧化硅膜32暴露,也同时使该氧化硅膜32在第1主蚀刻处理中作为掩模发挥功能的机会消失,能够防止在第1主蚀刻处理中多晶硅层31的形状紊乱。
以上,使用上述实施方式来对本发明进行了说明,但本发明并不限定于上述实施方式。
例如,在上述的多晶硅层的去除方法中,突破处理和主蚀刻处理分别执行了两次,但突破处理、主蚀刻处理的执行次数并不限于这些,但也可以是,例如突破处理和主蚀刻处理也可以交替地执行3次以上。尤其是,多晶硅层31的表面附近的晶种的分布被多晶硅层31的成膜条件左右,若例如多晶硅层31被快速地生成,则产生大量晶种,各晶种的边界有时到达多晶硅层31的深部。在这样的情况下,通过将突破处理和主蚀刻处理交替地执行3次以上,能够使进入已到达了多晶硅层31的深部的各晶种的边界的氧化硅膜32暴露而去除,因而,能够可靠地防止在沟槽28的底部局部地残存有残渣29。
另外,不仅在氧化硅膜32进入多晶硅层31的各晶种的边界的情况、而且在例如氮化硅膜、碳进入各晶种的边界的情况也能够适用本发明,在该情况下,用于去除氮化硅膜、碳的蚀刻处理和主蚀刻处理被交替执行地两次以上。而且,在主蚀刻处理中被蚀刻的膜也不限于多晶硅层31,只要是存在使晶种在表层产生的可能性的氮化硅层、金属层、例如钴膜,就通过适用本发明,能够防止残渣的产生。
另外,也通过将记录有实现上述的实施方式的功能的软件的程序代码的存储介质向基板处理系统10所具备的控制器27供给,控制器27的CPU将储存到存储介质的程序代码读出并执行来达成本发明的目的。
在该情况下,从存储介质读出来的程序代码自身实现上述的实施方式的功能,程序代码和存储有该程序代码的存储介质构成本发明。
另外,作为用于供给程序代码的存储介质,只要是例如RAM、NV-RAM、FLOPPY(注册商标)软盘、硬盘、光磁盘、CD-ROM、CD-R、CD-RW、DVD(DVD-ROM、DVD-RAM、DVD-RW、DVD+RW)等光盘、磁带、非易失性的存储卡、其他ROM等能够存储上述程序代码的介质即可。或者,上述程序代码也可以通过从与互联网、商用网络、或者局域网等连接的未图示的其他计算机、数据库等下载来向控制器27供给。
另外,也包括如下情况:通过控制器27执行读出来的程序代码,不仅实现上述实施方式的功能,而且基于该程序代码的指示,在CPU上运转的OS(操作系统)等执行实际的处理的一部分或全部,利用该处理实现上述的实施方式的功能。
而且,也包括如下情况:从存储介质读出来的程序代码写入到在被插入到控制器27的功能扩张板、连接到控制器27的功能扩张单元所具备的存储器之后,基于该程序代码的指示,在该功能扩张板、功能扩张单元设置的CPU等执行实际的处理的一部分或全部,利用该处理实现上述的实施方式的功能。
上述程序代码的形态也可以由目标代码、由解释程序执行的程序代码、向OS供给的脚本数据等形态构成。
【实施例】
接着,说明本发明的实施例。
首先,进行了3种对形成有多晶硅层31的晶圆W各实施1次突破处理和主蚀刻处理的以往的多晶硅层的去除方法。在各多晶硅层的去除方法中,对主蚀刻处理的执行条件进行调整而将该主蚀刻处理中的多晶硅层31的蚀刻量设定成(第1比较例)、(第2比较例)以及(第3比较例)。在执行了各多晶硅层的去除方法之后,从上方观察晶圆W,观察沟槽28的底部处的残渣29的残存形态,示意性地表示到图5。
另外,进行了6种对形成有多晶硅层31的晶圆W实施各两次突破处理和主蚀刻处理的图4的多晶硅层的去除方法。在各多晶硅层的去除方法中,对第1主蚀刻处理的执行条件进行调整而将该主蚀刻处理中的多晶硅层31的蚀刻量设定成(第1实施例)、(第2实施例)、(第3实施例)、(第4实施例)、(第5实施例)以及(第6实施例)。而且,与各比较例同样地,在执行了各多晶硅层的去除方法之后,从上方观察晶圆W,观察沟槽28的底部处的残渣29的残存形态,示意性地表示到图5。此外,在图5中,将以往的多晶硅层的去除方法表示为“无反复”,将图4的多晶硅层的去除方法表示为“有反复”。
如图5所示,在第1比较例~第3比较例中的任一个,都在沟槽28的底部局部地残存有残渣29。认为其原因在于,如上述的机理所示,在1次突破处理中,无法将进入到多晶硅层31的各晶种的间隙的氧化硅膜32去除,该氧化硅膜32作为氧化膜掩模33发挥功能,阻碍了多晶硅层31的蚀刻。
Claims (7)
1.一种蚀刻方法,将在用于制造电子器件的基板形成的被处理层去除,其特征在于,
该蚀刻方法包括:
第1突破处理,在该第1突破处理中,将在所述被处理层的表面形成的氧化膜去除;
第1主蚀刻处理,其在所述第1突破处理之后对所述被处理层进行蚀刻;
第2突破处理,其在所述第1主蚀刻处理之后将暴露的氧化膜去除;
第2主蚀刻处理,其在所述第2突破处理之后对所述被处理层进行蚀刻,
其中,在所述第2突破处理中所去除的所述暴露的氧化膜是在所述第1突破处理之前进入所述被处理层的表面附近的各晶种的边界的氧化膜,并且是在所述第1主蚀刻处理中通过蚀刻所述被处理层而暴露的氧化膜。
2.根据权利要求1所述的蚀刻方法,其特征在于,
所述第1主蚀刻处理中的所述被处理层的蚀刻量比所述第2主蚀刻处理中的所述被处理层的蚀刻量少。
4.根据权利要求1或2所述的蚀刻方法,其特征在于,
该蚀刻方法还具有:
第3突破处理,其在所述第2主蚀刻处理之后将暴露的氧化膜去除;
第3主蚀刻处理,其在所述第3突破处理之后对所述被处理层进行蚀刻。
5.根据权利要求1或2所述的蚀刻方法,其特征在于,
在所述第1突破处理和所述第2突破处理中,使用HF气体和NH3气体作为处理气体,
在所述第1主蚀刻处理和所述第2主蚀刻处理中,至少使用F2气体作为处理气体。
6.根据权利要求1或2所述的蚀刻方法,其特征在于,
所述被处理层是硅层、氮化硅层和金属层中的任一个。
7.一种基板处理系统,其对用于制造电子器件的基板实施蚀刻处理,其特征在于,该基板处理系统具备:
第1突破单元,其将在所述基板的被处理层的表面形成的氧化膜去除;
第1主蚀刻单元,其在所述第1突破单元的去除后对所述被处理层进行蚀刻;
第2突破单元,其在所述第1主蚀刻单元的蚀刻后将暴露的氧化膜去除;
第2主蚀刻单元,其在所述第2突破单元的去除后对所述被处理层进行蚀刻,
其中,所述第2突破单元所去除的所述暴露的氧化膜是在所述第1突破单元的去除处理之前进入所述被处理层的表面附近的各晶种的边界的氧化膜,并且是通过所述第1主蚀刻单元蚀刻所述被处理层而暴露的氧化膜。
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CN1777980A (zh) * | 2003-04-22 | 2006-05-24 | 东京毅力科创株式会社 | 硅氧化膜的去除方法及处理装置 |
CN102124551A (zh) * | 2008-08-18 | 2011-07-13 | 诺发系统有限公司 | 穿硅通孔填充工艺 |
JP2012164875A (ja) * | 2011-02-08 | 2012-08-30 | Tokyo Electron Ltd | プラズマエッチング方法 |
JP2012174850A (ja) * | 2011-02-21 | 2012-09-10 | Tokyo Electron Ltd | 基板処理方法及び記憶媒体 |
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EP0647163B1 (en) | 1992-06-22 | 1998-09-09 | Lam Research Corporation | A plasma cleaning method for removing residues in a plasma treatment chamber |
US5849639A (en) | 1997-11-26 | 1998-12-15 | Lucent Technologies Inc. | Method for removing etching residues and contaminants |
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JP4039385B2 (ja) * | 2003-04-22 | 2008-01-30 | 東京エレクトロン株式会社 | ケミカル酸化膜の除去方法 |
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US8664012B2 (en) * | 2011-09-30 | 2014-03-04 | Tokyo Electron Limited | Combined silicon oxide etch and contamination removal process |
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