CN108109970B - 电子封装件及其制法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 238000012856 packing Methods 0.000 claims description 50
- 238000002360 preparation method Methods 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 20
- 238000012545 processing Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 230000008859 change Effects 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 238000007772 electroless plating Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 125000004122 cyclic group Chemical group 0.000 claims description 2
- 239000011247 coating layer Substances 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 21
- 238000010276 construction Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- XLTRGZZLGXNXGD-UHFFFAOYSA-N benzene;1h-pyrazole Chemical compound C=1C=NNC=1.C1=CC=CC=C1 XLTRGZZLGXNXGD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明涉及电子封装件及其制法。一种电子封装件,包括:埋设有屏蔽部的承载结构、设于该承载结构上的电子元件、形成于该承载结构上以包覆该电子元件的包覆层、设于该包覆层中并电性连接该屏蔽部的屏蔽构件、以及形成于该包覆层上且电性连接该屏蔽构件的导电部,使该导电部、屏蔽构件与屏蔽部构成屏蔽结构。
Description
技术领域
本发明关于一种电子封装件,尤指一种防止电磁干扰的电子封装件及其制法。
背景技术
随着半导体技术的演进,半导体产品已开发出不同封装产品型态,而为提升电性品质,多种半导体产品具有屏蔽的功能,以防止电磁干扰(ElectromagneticInterference,简称EMI)产生。
请参阅图1A至图1C,其为现有的避免EMI的射频(Radio frequency,RF)模组的制法示意图,该射频模组1将多个如射频及非射频式晶片的电子元件11电性连接在一基板10上,再以如环氧树脂的封装层13包覆各该电子元件11,之后进行切单制程(如图1B所示的切割路径,其以虚线表示),再于该封装层13的顶面13a与侧面13c及该基板10的侧面10c上形成一金属薄膜15,以通过该金属薄膜15保护该些电子元件11免受外界EMI影响。
然而,现有射频模组1中,于切单制程后,再分别于单一射频模组1上形成该金属薄膜15,故需一一于各该射频模组1上形成该金属薄膜15,因而无法一次形成该金属薄膜15于所有的射频模组1上,导致该射频模组1的整体制作较为费时且生产成本较高。
因此,如何克服上述现有技术的问题,实已成目前亟欲解决的课题。
发明内容
为解决上述现有技术的种种问题,本发明遂揭示一种电子封装件及其制法,可有效缩短该电子封装件的整体制作时间。
本发明的电子封装件,包括:承载结构,其埋设有屏蔽部;电子元件,其设于该承载结构上;包覆层,其形成于该承载结构上以包覆该电子元件;屏蔽构件,其设于该包覆层中并电性连接该屏蔽部;以及导电部,其设于该包覆层上且电性连接该屏蔽构件。
本发明还提供一种电子封装件的制法,其包括:设置电子元件于一埋设有屏蔽部的承载结构上;形成包覆层于该承载结构上,以令该包覆层包覆该电子元件,并于该包覆层中设有电性连接该屏蔽部的屏蔽构件;以及设置导电部于该包覆层上,且令该导电部电性连接该屏蔽构件。
前述的制法中,该屏蔽部的制程包括:于该承载结构中形成凹部;以及于该凹部中形成导电材,以令该导电材作为该屏蔽部。
前述的制法中,还包括于形成该导电部后,进行切单制程。
前述的电子封装件及其制法中,该承载结构还埋设有接地层,以电性连接该屏蔽部。
前述的电子封装件及其制法中,该屏蔽部为板体或柱体。
前述的电子封装件及其制法中,该屏蔽部为环状。
前述的电子封装件及其制法中,该屏蔽部未凸出该承载结构的侧面,例如,该屏蔽部位于该承载结构的侧面内。
前述的电子封装件及其制法中,该屏蔽构件的部分表面外露于该包覆层以接触该导电部。
前述的电子封装件及其制法中,该承载结构定义有置晶区以供接置该电子元件,且该屏蔽部对应位于该置晶区的周围。
前述的电子封装件及其制法中,该屏蔽构件位于该电子元件周围。
前述的电子封装件及其制法中,该承载结构上设有多个该电子元件,且该屏蔽构件位于任二该电子元件之间。
另外,前述的电子封装件及其制法中,该导电部为盖体,以置放于该包覆层上。或者,该导电部为金属层,其以电镀、涂布、溅镀、化镀、无电镀或蒸镀方式形成者。
由上可知,本发明的电子封装件及其制法,主要通过先于该承载结构中形成屏蔽部,使该导电部只需形成于该包覆层的顶面上,而无需延伸至该承载结构的侧面,故相较于现有技术,只需进行一次形成导电部制程,即可于多个个电子封装件上形成屏蔽结构,而无需于多个电子封装件上一一进行形成导电部的制程,因而能有效缩短该电子封装件的整体制作时间,且利于量产化而降低成本。
附图说明
图1A至图1C为现有射频模组的制法的剖面示意图;
图2A至图2E为本发明的电子封装件的制法的剖面示意图;
图3A至图3C为对应图2B的不同实施例的上视示意图;以及
图4为对应图2C的上视示意图。
符号说明:
1 射频模组
10 基板
10c,13c,20c,23c 侧面
11 电子元件
13 封装层
13a,23a 顶面
15 金属薄膜
2 电子封装件
20 承载结构
20a 第一侧
20b 第二侧
200 绝缘层
201 线路层
202 接地层
21 电子元件
22 屏蔽部
22a 连接垫
220 凹部
23 包覆层
24 屏蔽构件
25 导电部
26 导电元件
A 置晶区
S 切割路径。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“内”、“顶”、“侧面”及“一”等用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2E为本发明的电子封装件2的制法的剖面示意图。
如图2A所示,提供一承载结构20,其具有相对的第一侧20a与第二侧20b,且于该承载结构20的第一侧20a形成至少一凹部220。
于本实施例中,该承载结构20的第一侧20a定义有至少一置晶区A,且令该凹部220位于该置晶区A的外围。该承载结构20为具有核心层的线路结构或无核心层(coreless)的线路结构,该线路结构具有绝缘层200与设于该绝缘层200上的线路层201,该线路层201对应设于该置晶区A的范围,例如为扇出(fan out)型重布线路层(redistribution layer,简称RDL),且形成该线路层201的材质为铜,而形成该绝缘层200的材质为如聚对二唑苯(Polybenzoxazole,简称PBO)、聚酰亚胺(Polyimide,简称PI)、预浸材(Prepreg,简称PP)等的介电材。应可理解地,该承载结构20也可为其它承载晶片的承载件,如有机板材、晶圆(wafer)、或其他具有金属布线(routing)的载板,并不限于上述。
此外,该线路层201具有多个外露于该第一侧20a的电性接触垫(图略),且该线路结构中设有邻近该第二侧20b的接地层202,例如,该接地层202位于该线路结构的最下层,以令该凹部220位于该线路层201与该接地层202的外围。
又,该凹部220以激光或切割刀具形成者,其可依需求连通或未连通至该第二侧20b。如图3A所示,该凹部220例如为一连续环状沟槽,以围绕置晶区A;或如图3B所示,该凹部220例如为多个的长形沟槽,且构成不连续环状沟槽,以围绕置晶区A;抑或如图3C所示,该凹部220例如为多个的柱状沟槽,且围绕置晶区A。
如图2B所示,形成导电材(如铜材)于该凹部220中,以作为屏蔽部22,使该屏蔽部22埋设于该承载结构20中并电性连接该接地层202。
于本实施例中,该屏蔽部22大致垂直该承载结构20的第一侧20a,且该屏蔽部22于该承载结构20的第一侧20a设有外露的连接垫22a。
此外,该屏蔽部22为板体,且如图3A所示,其为连续环状;该屏蔽部22也可如图3B或图3C所示的不连续环状,其中,图3B所示的屏蔽部22为板体,而图3C所示的屏蔽部22为柱体。
如图2C所示,设置多个电子元件21于该承载结构20的第一侧20a的置晶区A上,且该些电子元件21电性连接该承载结构20。接着,形成一包覆层23于该承载结构20的第一侧20a上,以令该包覆层23包覆该些电子元件21,并于该包覆层23中形成有至少一屏蔽构件24。
于本实施例中,该电子元件21为主动元件、被动元件或其二者组合等,其中,该主动元件例如为半导体晶片,且该被动元件例如为电阻、电容及电感。例如,该电子元件21为射频晶片(例如:蓝芽晶片或Wi-Fi晶片),但也可为其它不受电磁波干扰的电子元件。具体地,该电子元件21以覆晶方式或打线方式电性连接该线路层201的电性接触垫(图略)。然而,有关该电子元件电性连接该承载结构的方式不限于上述。
此外,该包覆层23为绝缘材,如聚酰亚胺(polyimide,简称PI)、干膜(dry film)、环氧树脂(epoxy)或封装材(molding compound),其可用压合(lamination)或模压(molding)的方式形成于该承载结构20的第一侧20a上。
又,该屏蔽构件24为导电材质(如铜、金、镍或铝等的金属)的板体或柱体,其立设于该承载结构20上且位于各该电子元件21周围(如图4所示,且该屏蔽构件24位于任二该电子元件21之间)并对应该屏蔽部22的连接垫22a的位置以电性连接该屏蔽部22。有关该屏蔽构件24的制作方式繁多,并无特别限制。例如,该屏蔽构件24的制程可先设置该屏蔽构件24于该承载结构20的第一侧20a上,再形成该包覆层23于该承载结构20的第一侧20a上,以令该包覆层23包覆该屏蔽构件24;或者,先形成该包覆层23于该承载结构20的第一侧20a上,再于该包覆层23中形成穿孔,之后形成该屏蔽构件24于该穿孔中。
另外,该屏蔽构件24的部分表面(顶面)外露于该包覆层23的顶面23a。例如,形成孔洞于该包覆层23上,以令该屏蔽构件24的顶面外露于该孔洞;或者,如图2C所示,进行整平制程,使该屏蔽构件24的顶面齐平该包覆层23的顶面23a。
据此,通过该屏蔽构件24作为电磁波屏障以遮蔽该些电子元件21的侧壁,而防止各该电子元件21之间相互电磁波(或信号)干扰,使该些电子元件21得以保持应有的功效。
如图2D所示,形成一导电部25于该包覆层23的顶面23a上,且该导电部25接触该屏蔽构件24以电性连接该屏蔽构件24,俾供作为电磁屏蔽隔间(EMI partition)。
于本实施例中,形成该导电部25的材质如金属或导电胶,如金、银、铜(Cu)、镍(Ni)、铁(Fe)、铝(Al)、不锈钢(Sus)等,但不以此为限。
此外,该导电部25可为盖体,以置放于该包覆层23的顶面23a上;或者,该导电部25可为金属层,通过电镀、涂布(coating)、溅镀(sputtering)、化镀、无电镀或蒸镀等方式形成该导电部25。
如图2E所示,形成多个如焊球的导电元件26于该承载结构20的第二侧20b上,再沿如图2D所示的切割路径S进行切单制程,以得到多个个本发明的电子封装件2。
于本实施例中,该导电元件26电性连接该线路层201及接地层202。
此外,该屏蔽部22未凸出该承载结构20的侧面20c,其可外露或不外露于该承载结构20的侧面20c。具体地,如图2E所示,该屏蔽部22位于该承载结构20的侧面20c内;或者,该屏蔽部22齐平该承载结构20的侧面20c,以令该屏蔽部22外露于该承载结构20的侧面20c。
本发明的电子封装件2的制法,先于该承载结构20中形成围绕置晶区A的凹部220,再于该凹部220中形成该屏蔽部22,并使该屏蔽部22电性连接该接地层202,故于后续制程中,该导电部25通过该屏蔽构件24电性连接该屏蔽部22,即可构成屏蔽结构,使该电子封装件2于运作时,该些电子元件21不会遭受外界的电磁干扰(EMI),且该屏蔽部22也可避免该线路层201受外界的电磁干扰。
因此,该导电部25只需形成于该包覆层23的顶面23a上,而无需延伸至该承载结构20的侧面20c,故于切单制程前,只需进行一次形成该导电部25的制程(如图2D所示),而无需于切单制程后,一一于各该电子封装件2上形成导电部25,因而能有效缩短该电子封装件2的整体制作时间,且利于量产化而降低成本。
本发明还提供一种电子封装件2,包括:一承载结构20、多个电子元件21、一包覆层23、一屏蔽构件24以及导电部25。
所述的承载结构20埋设有一屏蔽部22。
所述的电子元件21设于该承载结构20上。
所述的包覆层23形成于该承载结构20上并包覆该些电子元件21。
所述的屏蔽构件24设于该包覆层23中并电性连接该屏蔽部22。
所述的导电部25形成于该包覆层23上且电性连接该屏蔽构件24。
于一实施例中,该承载结构20还埋设有接地层202,以电性连接该屏蔽部22。
于一实施例中,该屏蔽部22为板体或柱体。
于一实施例中,该屏蔽部22为环状。
于一实施例中,该屏蔽部22未凸出该承载结构20的侧面20c,例如,该屏蔽部22埋设于该承载结构20的侧面20c内。
于一实施例中,该屏蔽构件24的部分表面外露于该包覆层23以接触该导电部25。
于一实施例中,该承载结构20定义有置晶区A以供接置该电子元件21,且该屏蔽部22对应位于该置晶区A的周围。
于一实施例中,该屏蔽构件24位于该电子元件21周围。
于一实施例中,该屏蔽构件24位于任二该电子元件21之间。
于一实施例中,该导电部25为金属层或盖体。
综上所述,本发明的电子封装件及其制法中,其通过先于该承载结构中形成屏蔽部,使该导电部只需形成于该包覆层的顶面上,而无需延伸至该承载结构的侧面,故只需进行一次形成导电部制程,即可于多个个电子封装件上形成屏蔽结构,而无需于多个电子封装件上一一进行形成导电部的制程,因而能有效缩短该电子封装件的整体制作时间,且利于量产化而降低成本。
上述该些实施样态仅例示性说明本发明的功效,而非用于限制本发明,任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下,对上述该些实施态样进行修饰与改变。此外,在上述该些实施态样中的元件的数量仅为例示性说明,也非用于限制本发明。因此本发明的权利保护范围,应如权利要求书所列。
Claims (19)
1.一种电子封装件,其特征为,该电子封装件包括:
承载结构,其埋设有屏蔽部,其中,该屏蔽部为连续或不连续的环状板体;
电子元件,其设于该承载结构上;
包覆层,其形成于该承载结构上以包覆该电子元件;
屏蔽构件,其设于该包覆层中并电性连接该屏蔽部;以及
导电部,其设于该包覆层上且电性连接该屏蔽构件。
2.如权利要求1所述的电子封装件,其特征为,该承载结构还埋设有接地层,以电性连接该屏蔽部。
3.如权利要求1所述的电子封装件,其特征为,该屏蔽部未凸出该承载结构的侧面。
4.如权利要求1所述的电子封装件,其特征为,该屏蔽构件的部分表面外露于该包覆层以接触该导电部。
5.如权利要求1所述的电子封装件,其特征为,该承载结构定义有置晶区以供接置该电子元件,且该屏蔽部对应位于该置晶区的周围。
6.如权利要求1所述的电子封装件,其特征为,该屏蔽构件位于该电子元件周围。
7.如权利要求1所述的电子封装件,其特征为,该承载结构上设有多个该电子元件,且该屏蔽构件位于任二该电子元件之间。
8.如权利要求1所述的电子封装件,其特征为,该导电部为金属层或盖体。
9.一种电子封装件的制法,其特征为,该制法包括:
设置电子元件于一埋设有屏蔽部的承载结构上,其中,该屏蔽部为连续或不连续的环状板体;
形成包覆层于该承载结构上,以令该包覆层包覆该电子元件,其中,该包覆层中设有电性连接该屏蔽部的屏蔽构件;以及
设置导电部于该包覆层上,且令该导电部电性连接该屏蔽构件。
10.如权利要求9所述的电子封装件的制法,其特征为,该承载结构还埋设有接地层,以电性连接该屏蔽部。
11.如权利要求9所述的电子封装件的制法,其特征为,该屏蔽部未凸出该承载结构的侧面。
12.如权利要求9所述的电子封装件的制法,其特征为,该屏蔽部的制程包括:
于该承载结构中形成凹部;以及
于该凹部中形成导电材,以令该导电材作为该屏蔽部。
13.如权利要求9所述的电子封装件的制法,其特征为,该屏蔽构件的部分表面外露于该包覆层以接触该导电部。
14.如权利要求9所述的电子封装件的制法,其特征为,该制法包括于形成该导电部后,进行切单制程。
15.如权利要求9所述的电子封装件的制法,其特征为,该承载结构定义有置晶区以供接置该电子元件,且该屏蔽部对应位于该置晶区的周围。
16.如权利要求9所述的电子封装件的制法,其特征为,该屏蔽构件位于该电子元件周围。
17.如权利要求9所述的电子封装件的制法,其特征为,该承载结构上设有多个该电子元件,且该屏蔽构件位于任二该电子元件之间。
18.如权利要求9所述的电子封装件的制法,其特征为,该导电部为盖体,以置放于该包覆层上。
19.如权利要求9所述的电子封装件的制法,其特征为,该导电部为金属层,其以电镀、涂布、溅镀、化镀、无电镀或蒸镀方式形成者。
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Publication number | Priority date | Publication date | Assignee | Title |
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CN101930969A (zh) * | 2009-06-22 | 2010-12-29 | 日月光半导体制造股份有限公司 | 具有电磁干扰防护罩的半导体封装件 |
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CN103633060A (zh) * | 2012-08-24 | 2014-03-12 | 钰桥半导体股份有限公司 | 具有内嵌元件及电磁屏障的线路板 |
CN103165563B (zh) * | 2011-12-16 | 2016-01-20 | 矽品精密工业股份有限公司 | 半导体封装件及其制法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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CN102306645A (zh) * | 2011-09-29 | 2012-01-04 | 日月光半导体制造股份有限公司 | 具有电磁干扰屏蔽膜的半导体封装件及其制造方法 |
CN103165563B (zh) * | 2011-12-16 | 2016-01-20 | 矽品精密工业股份有限公司 | 半导体封装件及其制法 |
CN103633060A (zh) * | 2012-08-24 | 2014-03-12 | 钰桥半导体股份有限公司 | 具有内嵌元件及电磁屏障的线路板 |
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