TW201820582A - 電子封裝件及其製法 - Google Patents
電子封裝件及其製法 Download PDFInfo
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Abstract
一種電子封裝件,係包括:埋設有屏蔽部之承載結構、設於該承載結構上之電子元件、形成於該承載結構上以包覆該電子元件之包覆層、設於該包覆層中並電性連接該屏蔽部之屏蔽構件、以及形成於該包覆層上且電性連接該屏蔽構件之導電部,使該導電部、屏蔽構件與屏蔽部構成屏蔽結構。本發明復提供該電子封裝件之製法。
Description
本發明係關於一種電子封裝件,更詳而言之,係有關於一種防止電磁干擾之電子封裝件及其製法。
隨著半導體技術的演進,半導體產品已開發出不同封裝產品型態,而為提升電性品質,多種半導體產品具有屏蔽之功能,以防止電磁干擾(Electromagnetic Interference,簡稱EMI)產生。
請參閱第1A至1C圖,係為習知之避免EMI之射頻(Radio frequency,RF)模組之製法示意圖,該射頻模組1係將複數如射頻及非射頻式晶片之電子元件11電性連接在一基板10上,再以如環氧樹脂之封裝層13包覆各該電子元件11,之後進行切單製程(如第1B圖所示之切割路徑,其以虛線表示),再於該封裝層13之頂面13a與側面13c及該基板10之側面10c上形成一金屬薄膜15,以藉由該金屬薄膜15保護該些電子元件11免受外界EMI影響。
惟,習知射頻模組1中,係於切單製程後,再分別於單一射頻模組1上形成該金屬薄膜15,故需一一於各該射 頻模組1上形成該金屬薄膜15,因而無法一次形成該金屬薄膜15於所有之射頻模組1上,導致該射頻模組1之整體製作較為費時且生產成本較高。
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。
為解決上述習知技術之種種問題,本發明遂揭露一種電子封裝件,係包括:承載結構,係埋設有屏蔽部;電子元件,係設於該承載結構上;包覆層,係形成於該承載結構上以包覆該電子元件;屏蔽構件,係設於該包覆層中並電性連接該屏蔽部;以及導電部,係設於該包覆層上且電性連接該屏蔽構件。
本發明復提供一種電子封裝件之製法,係包括:設置電子元件於一埋設有屏蔽部之承載結構上;形成包覆層於該承載結構上,以令該包覆層包覆該電子元件,並於該包覆層中設有電性連接該屏蔽部之屏蔽構件;以及設置導電部於該包覆層上,且令該導電部電性連接該屏蔽構件。
前述之製法中,該屏蔽部之製程係包括:於該承載結構中形成凹部;以及於該凹部中形成導電材,以令該導電材作為該屏蔽部。
前述之製法中,復包括於形成該導電部後,進行切單製程。
前述之電子封裝件及其製法中,該承載結構復埋設有接地層,以電性連接該屏蔽部。
前述之電子封裝件及其製法中,該屏蔽部係為板體或柱體。
前述之電子封裝件及其製法中,該屏蔽部係為環狀。
前述之電子封裝件及其製法中,該屏蔽部係未凸出該承載結構之側面,例如,該屏蔽部係位於該承載結構之側面內。
前述之電子封裝件及其製法中,該屏蔽構件之部分表面係外露於該包覆層以接觸該導電部。
前述之電子封裝件及其製法中,該承載結構定義有置晶區以供接置該電子元件,且該屏蔽部對應位於該置晶區之周圍。
前述之電子封裝件及其製法中,該屏蔽構件位於該電子元件周圍。
前述之電子封裝件及其製法中,該承載結構上設有複數該電子元件,且該屏蔽構件位於任二該電子元件之間。
另外,前述之電子封裝件及其製法中,該導電部係為蓋體,以置放於該包覆層上。或者,該導電部係為金屬層,其以電鍍、塗佈、濺鍍、化鍍、無電鍍或蒸鍍方式形成者。
由上可知,本發明之電子封裝件及其製法,主要藉由先於該承載結構中形成屏蔽部,使該導電部只需形成於該包覆層之頂面上,而無需延伸至該承載結構之側面,故相較於習知技術,只需進行一次形成導電部製程,即可於複數個電子封裝件上形成屏蔽結構,而無需於複數電子封裝件上一一進行形成導電部之製程,因而能有效縮短該電子 封裝件之整體製作時間,且利於量產化而降低成本。
1‧‧‧射頻模組
10‧‧‧基板
10c,13c,20c,23c‧‧‧側面
11‧‧‧電子元件
13‧‧‧封裝層
13a,23a‧‧‧頂面
15‧‧‧金屬薄膜
2‧‧‧電子封裝件
20‧‧‧承載結構
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧絕緣層
201‧‧‧線路層
202‧‧‧接地層
21‧‧‧電子元件
22‧‧‧屏蔽部
22a‧‧‧連接墊
220‧‧‧凹部
23‧‧‧包覆層
24‧‧‧屏蔽構件
25‧‧‧導電部
26‧‧‧導電元件
A‧‧‧置晶區
S‧‧‧切割路徑
第1A至1C圖係為習知射頻模組之製法之剖面示意圖;第2A至2E圖係為本發明之電子封裝件之製法之剖面示意圖;第3A至3C圖係為對應第2B圖之不同實施例之上視示意圖;以及第4圖係為對應第2C圖之上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“內”、“頂”、“側面”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示,提供一承載結構20,其具有相對之第一側20a與第二側20b,且於該承載結構20之第一側20a形成至少一凹部220。
於本實施例中,該承載結構20之第一側20a係定義有至少一置晶區A,且令該凹部220位於該置晶區A之外圍。該承載結構20係為具有核心層之線路結構或無核心層(coreless)之線路結構,該線路結構具有絕緣層200與設於該絕緣層200上之線路層201,該線路層201係對應設於該置晶區A之範圍,例如為扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL),且形成該線路層201之材質係為銅,而形成該絕緣層200之材質係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等之介電材。應可理解地,該承載結構20亦可為其它承載晶片之承載件,如有機板材、晶圓(wafer)、或其他具有金屬佈線(routing)之載板,並不限於上述。
再者,該線路層201具有複數外露於該第一側20a之電性接觸墊(圖略),且該線路結構中設有鄰近該第二側20b之接地層202,例如,該接地層202係位於該線路結構之最下層,以令該凹部220位於該線路層201與該接地層202之外圍。
又,該凹部220係以雷射或切割刀具形成者,其可依 需求連通或未連通至該第二側20b。如第3A圖所示,該凹部220例如為一連續環狀溝槽,以圍繞置晶區A;或如第3B圖所示,該凹部220例如為複數之長形溝槽,且構成不連續環狀溝槽,以圍繞置晶區A;亦或如第3C圖所示,該凹部220例如為複數之柱狀溝槽,且圍繞置晶區A。
如第2B圖所示,形成導電材(如銅材)於該凹部220中,以作為屏蔽部22,使該屏蔽部22埋設於該承載結構20中並電性連接該接地層202。
於本實施例中,該屏蔽部22大致垂直該承載結構20之第一側20a,且該屏蔽部22於該承載結構20之第一側20a設有外露之連接墊22a。
再者,該屏蔽部22係為板體,且如第3A圖所示,其為連續環狀;該屏蔽部22亦可如第3B或3C圖所示之不連續環狀,其中,第3B圖所示之屏蔽部22係為板體,而第3C圖所示之屏蔽部22係為柱體。
如第2C圖所示,設置複數電子元件21於該承載結構20之第一側20a之置晶區A上,且該些電子元件21電性連接該承載結構20。接著,形成一包覆層23於該承載結構20之第一側20a上,以令該包覆層23包覆該些電子元件21,並於該包覆層23中形成有至少一屏蔽構件24。
於本實施例中,該電子元件21係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。例如,該電子元件21係為射頻晶片(例如:藍芽晶片或Wi-Fi晶片),但 亦可為其它不受電磁波干擾之電子元件。具體地,該電子元件21係以覆晶方式或打線方式電性連接該線路層201之電性接觸墊(圖略)。然而,有關該電子元件電性連接該承載結構之方式不限於上述。
再者,該包覆層23係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound),其可用壓合(lamination)或模壓(molding)之方式形成於該承載結構20之第一側20a上。
又,該屏蔽構件24係為導電材質(如銅、金、鎳或鋁等之金屬)之板體或柱體,其立設於該承載結構20上且位於各該電子元件21周圍(如第4圖所示,且該屏蔽構件24位於任二該電子元件21之間)並對應該屏蔽部22之連接墊22a之位置以電性連接該屏蔽部22。有關該屏蔽構件24之製作方式繁多,並無特別限制。例如,該屏蔽構件24之製程可先設置該屏蔽構件24於該承載結構20之第一側20a上,再形成該包覆層23於該承載結構20之第一側20a上,以令該包覆層23包覆該屏蔽構件24;或者,先形成該包覆層23於該承載結構20之第一側20a上,再於該包覆層23中形成穿孔,之後形成該屏蔽構件24於該穿孔中。
另外,該屏蔽構件24之部分表面(頂面)係外露於該包覆層23之頂面23a。例如,形成孔洞於該包覆層23上,以令該屏蔽構件24之頂面外露於該孔洞;或者,如第2C圖所示,進行整平製程,使該屏蔽構件24之頂面齊平該包 覆層23之頂面23a。
據此,藉由該屏蔽構件24作為電磁波屏障以遮蔽該些電子元件21的側壁,而防止各該電子元件21之間相互電磁波(或訊號)干擾,使該些電子元件21得以保持應有的功效。
如第2D圖所示,形成一導電部25於該包覆層23之頂面23a上,且該導電部25接觸該屏蔽構件24以電性連接該屏蔽構件24,俾供作為電磁屏蔽隔間(EMI partition)。
於本實施例中,形成該導電部25之材質係如金屬或導電膠,如金、銀、銅(Cu)、鎳(Ni)、鐵(Fe)、鋁(Al)、不銹鋼(Sus)等,但不以此為限。
再者,該導電部25可為蓋體,以置放於該包覆層23之頂面23a上;或者,該導電部25可為金屬層,係藉由電鍍、塗佈(coating)、濺鍍(sputtering)、化鍍、無電鍍或蒸鍍等方式形成該導電部25。
如第2E圖所示,形成複數如銲球之導電元件26於該承載結構20之第二側20b上,再沿如第2D圖所示之切割路徑S進行切單製程,以得到複數個本發明之電子封裝件2。
於本實施例中,該導電元件26係電性連接該線路層201及接地層202。
再者,該屏蔽部22未凸出該承載結構20之側面20c,其可外露或不外露於該承載結構20之側面20c。具體地,如第2E圖所示,該屏蔽部22係位於該承載結構20之側面 20c內;或者,該屏蔽部22齊平該承載結構20之側面20c,以令該屏蔽部22外露於該承載結構20之側面20c。
本發明之電子封裝件2之製法,係先於該承載結構20中形成圍繞置晶區A之凹部220,再於該凹部220中形成該屏蔽部22,並使該屏蔽部22電性連接該接地層202,故於後續製程中,該導電部25藉由該屏蔽構件24電性連接該屏蔽部22,即可構成屏蔽結構,使該電子封裝件2於運作時,該些電子元件21不會遭受外界之電磁干擾(EMI),且該屏蔽部22亦可避免該線路層201受外界之電磁干擾。
因此,該導電部25只需形成於該包覆層23之頂面23a上,而無需延伸至該承載結構20之側面20c,故於切單製程前,只需進行一次形成該導電部25之製程(如第2D圖所示),而無需於切單製程後,一一於各該電子封裝件2上形成導電部25,因而能有效縮短該電子封裝件2之整體製作時間,且利於量產化而降低成本。
本發明復提供一種電子封裝件2,係包括:一承載結構20、複數電子元件21、一包覆層23、一屏蔽構件24以及導電部25。
所述之承載結構20係埋設有一屏蔽部22。
所述之電子元件21係設於該承載結構20上。
所述之包覆層23係形成於該承載結構20上並包覆該些電子元件21。
所述之屏蔽構件24係設於該包覆層23中並電性連接該屏蔽部22。
所述之導電部25係形成於該包覆層23上且電性連接該屏蔽構件24。
於一實施例中,該承載結構20復埋設有接地層202,以電性連接該屏蔽部22。
於一實施例中,該屏蔽部22係為板體或柱體。
於一實施例中,該屏蔽部22係為環狀。
於一實施例中,該屏蔽部22未凸出該承載結構20之側面20c,例如,該屏蔽部22係埋設於該承載結構20之側面20c內。
於一實施例中,該屏蔽構件24之部分表面係外露於該包覆層23以接觸該導電部25。
於一實施例中,該承載結構20定義有置晶區A以供接置該電子元件21,且該屏蔽部22對應位於該置晶區A之周圍。
於一實施例中,該屏蔽構件24係位於該電子元件21周圍。
於一實施例中,該屏蔽構件24係位於任二該電子元件21之間。
於一實施例中,該導電部25係為金屬層或蓋體。
綜上所述,本發明之電子封裝件及其製法中,係藉由先於該承載結構中形成屏蔽部,使該導電部只需形成於該包覆層之頂面上,而無需延伸至該承載結構之側面,故只需進行一次形成導電部製程,即可於複數個電子封裝件上形成屏蔽結構,而無需於複數電子封裝件上一一進行形成 導電部之製程,因而能有效縮短該電子封裝件之整體製作時間,且利於量產化而降低成本。
上述該些實施樣態僅例示性說明本發明之功效,而非用於限制本發明,任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述該些實施態樣進行修飾與改變。此外,在上述該些實施態樣中之元件的數量僅為例示性說明,亦非用於限制本發明。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
Claims (23)
- 一種電子封裝件,係包括:承載結構,係埋設有屏蔽部;電子元件,係設於該承載結構上;包覆層,係形成於該承載結構上以包覆該電子元件;屏蔽構件,係設於該包覆層中並電性連接該屏蔽部;以及導電部,係設於該包覆層上且電性連接該屏蔽構件。
- 如申請專利範圍第1項所述之電子封裝件,其中,該承載結構復埋設有接地層,以電性連接該屏蔽部。
- 如申請專利範圍第1項所述之電子封裝件,其中,該屏蔽部係為板體或柱體。
- 如申請專利範圍第1項所述之電子封裝件,其中,該屏蔽部係為環狀。
- 如申請專利範圍第1項所述之電子封裝件,其中,該屏蔽部係未凸出該承載結構之側面。
- 如申請專利範圍第1項所述之電子封裝件,其中,該屏蔽構件之部分表面係外露於該包覆層以接觸該導電部。
- 如申請專利範圍第1項所述之電子封裝件,其中,該承載結構定義有置晶區以供接置該電子元件,且該屏蔽部對應位於該置晶區之周圍。
- 如申請專利範圍第1項所述之電子封裝件,其中,該屏 蔽構件位於該電子元件周圍。
- 如申請專利範圍第1項所述之電子封裝件,其中,該承載結構上設有複數該電子元件,且該屏蔽構件位於任二該電子元件之間。
- 如申請專利範圍第1項所述之電子封裝件,其中,該導電部係為金屬層或蓋體。
- 一種電子封裝件之製法,係包括:設置電子元件於一埋設有屏蔽部之承載結構上;形成包覆層於該承載結構上,以令該包覆層包覆該電子元件,其中,該包覆層中設有電性連接該屏蔽部之屏蔽構件;以及設置導電部於該包覆層上,且令該導電部電性連接該屏蔽構件。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該承載結構復埋設有接地層,以電性連接該屏蔽部。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該屏蔽部係為板體或柱體。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該屏蔽部係為環狀。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該屏蔽部係未凸出該承載結構之側面。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該屏蔽部之製程係包括:於該承載結構中形成凹部;以及 於該凹部中形成導電材,以令該導電材作為該屏蔽部。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該屏蔽構件之部分表面係外露於該包覆層以接觸該導電部。
- 如申請專利範圍第11項所述之電子封裝件之製法,復包括於形成該導電部後,進行切單製程。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該承載結構定義有置晶區以供接置該電子元件,且該屏蔽部對應位於該置晶區之周圍。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該屏蔽構件位於該電子元件周圍。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該承載結構上設有複數該電子元件,且該屏蔽構件位於任二該電子元件之間。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該導電部係為蓋體,以置放於該包覆層上。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該導電部係為金屬層,其以電鍍、塗佈、濺鍍、化鍍、無電鍍或蒸鍍方式形成者。
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TWI511245B (zh) * | 2013-10-04 | 2015-12-01 | Azurewave Technologies Inc | 用於提升散熱效能的模組積體電路封裝結構及其製作方法 |
JP6091460B2 (ja) * | 2014-04-11 | 2017-03-08 | シマネ益田電子株式会社 | 電子部品の製造方法 |
TWI611533B (zh) * | 2014-09-30 | 2018-01-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
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2016
- 2016-11-24 TW TW105138624A patent/TWI634640B/zh active
- 2016-12-02 CN CN201611094633.9A patent/CN108109970B/zh active Active
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TWI792476B (zh) * | 2020-08-07 | 2023-02-11 | 大陸商珠海越亞半導體股份有限公司 | 一種具有遮罩腔的嵌入式封裝結構及其製造方法 |
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