CN107871733A - 半导体模块 - Google Patents

半导体模块 Download PDF

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Publication number
CN107871733A
CN107871733A CN201710891485.1A CN201710891485A CN107871733A CN 107871733 A CN107871733 A CN 107871733A CN 201710891485 A CN201710891485 A CN 201710891485A CN 107871733 A CN107871733 A CN 107871733A
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Prior art keywords
semiconductor module
circuit
circuit element
relative
metallic plate
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Granted
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CN201710891485.1A
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CN107871733B (zh
Inventor
中原贤太
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

本发明的目的在于，提供将配线的接合部分的可靠性提高且将面积缩小的半导体模块。半导体模块(100)具有：多个金属板，它们在水平方向延伸，在垂直方向层叠；至少1个开关元件；以及至少1个电路元件(71)，至少1个开关元件接合于在垂直方向相对的2个金属板之间，至少1个电路元件(71)接合于在垂直方向相对的2个金属板之间，在多个金属板之间配置有绝缘性材料，至少1个金属板与开关元件、电路元件(71)这两者接合。

Description

半导体模块
技术领域
本发明涉及半导体模块。
背景技术
就现有的半导体模块而言，使用搭载有电容器、电阻元件等电路元件、开关元件的多层配线基板。当前，电容器、电阻元件等电路元件与形成于基板之上的电路图案在水平方向接合。或者，一个电极与电路图案接合，另一个电极通过金属导线与电路图案连接。
专利文献1：日本特开平9-116091号公报
当前，在基板之上在水平方向搭载有电路元件，因此存在电路元件的搭载所需的面积增大的问题。另外，在将金属导线用于电路元件与基板的连接的情况下，伴随搭载所需的面积的增大，与导线接合相关的可靠性成为问题。
发明内容
本发明就是为了解决上述课题而提出的，其目的在于提供一种使配线的接合部分的可靠性提高，并且将电路元件的搭载所需的面积缩小的半导体模块。
本发明涉及的半导体模块具有：多个金属板，它们在水平方向延伸，在垂直方向层叠；至少1个开关元件；以及至少1个电路元件，至少1个开关元件接合于在垂直方向相对的2个金属板之间，至少1个电路元件接合于在垂直方向相对的2个金属板之间，在多个金属板之间配置有绝缘性材料，至少1个金属板与开关元件、电路元件这两者接合。
发明的效果
根据本发明涉及的半导体模块，由于将电路元件接合于在垂直方向相对的2个金属板之间，因此能够使电路元件的安装所需的面积缩小，将半导体模块小型化。另外，由于将电路元件接合于在垂直方向相对的2个金属板之间，因此与将电路元件在水平方向配置于金属板之上的情况相比，能够减少由金属板与电路元件的热膨胀率之差引起的翘曲。因此，能够提高配线的接合部分的可靠性。
附图说明
图1是实施方式1涉及的半导体模块的剖视图。
图2是表示实施方式1涉及的半导体模块的电路结构的图。
图3是实施方式1的第1变形例涉及的半导体模块的剖视图。
图4是表示实施方式1的第1变形例涉及的半导体模块的电路结构的图。
图5是实施方式1的第2变形例涉及的半导体模块的剖视图。
图6是表示实施方式1的第2变形例涉及的半导体模块的电路结构的图。
图7是实施方式2涉及的半导体模块的剖视图。
图8是实施方式3涉及的半导体模块的剖视图。
图9是实施方式4涉及的半导体模块的剖视图。
图10是表示在外部连接有缓冲电路的半导体模块的电路结构的图。
图11是表示内置有缓冲电路的半导体模块的电路结构的图。
标号的说明
8导电性接合材料，9散热器，10绝缘性树脂，21、51第1金属板，22、52第2金属板，23、53第3金属板，54第4金属板，31、32、61、62绝缘基板，41第1开关元件，42第2开关元件，71、72、73、74、75电路元件，100、100A、100B、200、300、400半导体模块。
具体实施方式
<实施方式1>
图1是本实施方式1中的半导体模块100的剖视图。如图1所示，半导体模块100具有：第1、第2、第3金属板21、22、23，它们在水平方向延伸，在垂直方向层叠；第1、第2开关元件41、42；以及电路元件71。
第1、第2开关元件41、42是例如IGBT(insulated gate bipolar transistor)、MOSFET(metal-oxide-semiconductor field-effect transistor)等。在第1、第2开关元件41、42的两面设置有主电极。另外，开关元件41、42也可以内置有续流二极管。电路元件71是电容器、电阻元件等无源元件或二极管等有源元件。在电路元件71的两端设置有电极。
第2金属板22是由第1部分221与第2部分222接合而形成的。第1金属板21的一端被引出至半导体模块100的封装件外部，成为P电极(下面也记作电极P)。另外，第2金属板22的一端被引出至半导体模块100的封装件外部，成为AC电极(下面也记作电极AC)。另外，第3金属板23的一端被引出至半导体模块100的封装件外部，成为N电极(下面也记作电极N)。
此外，在本说明书中，“在水平方向延伸的金属板”也可以不是在水平方向平坦的金属板，例如，也可以像第2金属板22这样具有存在台阶的部分。另外，就金属板而言，厚度也并非必须是均匀的，厚度也可以对应于电流容许量、所要求的强度、层叠基板的构造等而不同。第1至第3金属板21、22、23也可以形成电路图案。
第1、第2金属板21、22与绝缘基板31、32一起形成多层基板3。在第1金属板21与第2金属板22的第1部分221之间配置有第1开关元件41。第1开关元件41的两面的电极经由导电性接合材料8而分别面接合至在垂直方向相对的第1金属板21和第2金属板22的第1部分221。在这里，导电性接合材料8是焊料或含有银颗粒的烧结性接合材料等。
在第2金属板22的第2部分222与第3金属板23之间配置有第2开关元件42。第2开关元件42的两面的电极经由导电性接合材料8而分别面接合至在垂直方向相对的第2金属板22的第2部分222和第3金属板23。
在第1金属板21与第2金属板22的第2部分222之间配置有电路元件71。电路元件71的两端的电极经由导电性接合材料8而分别面接合至在垂直方向相对的第1金属板21和第2金属板22的第2部分222。电路元件71将配置于第1金属板21与第2金属板22的第2部分222之间的绝缘基板32贯穿。电路元件71与第1开关元件41并联地接合在电极P与电极AC之间。
另外，在多层基板3的背面，即与配置开关元件41的面相反侧的面配置散热器9。除电极P、N、AC的端部及散热器9之外,第1至第3金属板21、22、23、绝缘基板31、32、第1、第2开关元件41、42及电路元件71被绝缘性树脂10封装。
此外，在本实施方式1中，在第1、第2金属板21、22之间接合有电路元件71，但对电路元件进行接合的位置不限定于此。例如，也可以在第2、第3金属板22、23之间(即，电极AC与电极N之间)，或第1、第3金属板21、23之间(即，电极P与电极N之间)接合电路元件71。
另外，在本实施方式1中，将半导体模块100设为具有1个电路元件71的结构，但也可以设为具有多个电路元件71的结构。
另外，就半导体模块100而言，将第1至第3金属板21、22、23各自的厚度设为大于或等于0.25mm。在考虑到功率模块的通电和发热时，通过增加金属板的厚度，从而能够降低开关元件41、42通电时的电流密度。另外，能够抑制金属板的发热，因此能够大电流化。另外，金属板的主要材料是例如铝(Al)、铜(Cu)等。特别地，如果是铜，则电阻率低、热传导率也高，因此能够在大电流化的同时实现低热电阻化。
另外，就半导体模块100而言，绝缘基板31、32由有机树脂或陶瓷形成。在绝缘基板31、32由有机树脂形成的情况下，将绝缘基板31、32各自的厚度设为大于或等于0.1mm。通过将绝缘基板31、32的厚度设为大于或等于0.1mm，从而能够确保在例如将600V至6.5kV的范围的电压施加于半导体模块100的P电极、N电极间而使用的情况下所需的绝缘性能和可靠性。
在绝缘基板31、32由Al2O3、AlN、Si3N4等陶瓷形成的情况下，将绝缘基板31、32各自的厚度设为大于或等于0.32mm。通过将绝缘基板31、32的厚度设为大于或等于0.32mm，从而能够确保在例如将1200V的电压施加于半导体模块100的P电极、N电极间而使用的情况下所需的绝缘性能和可靠性、绝缘基板31、32的强度。
如上所述，通过将第1至第3金属板21、22、23各自的厚度设为大于或等于0.25mm，且将绝缘基板31、32各自的厚度设为大于或等于0.32mm，从而能够实现处理大电流且高电压的半导体模块。
图2是表示半导体模块100的电路结构的图。如图2所示，第1、第2开关元件41、42串联连接。另外，电路元件71与第1开关元件41并联接合。例如，通过将电路元件71设为电容器，从而构成缓冲电路SC，该缓冲电路SC抑制伴随第1开关元件41的通断而产生的浪涌电压。
<效果>
本实施方式1中的半导体模块100具有：多个金属板(第1、第2、第3金属板21、22、23)，它们在水平方向延伸，在垂直方向层叠；至少1个开关元件(第1、第2开关元件41、42)；以及至少1个电路元件71，至少1个开关元件接合于在垂直方向相对的2个金属板之间，至少1个电路元件71接合于在垂直方向相对的2个金属板之间，在多个金属板之间配置有绝缘性材料，至少1个金属板与开关元件、电路元件71这两者接合。
根据本实施方式1中的半导体模块100，与开关元件的接合同样地，将电路元件71接合于在垂直方向相对的2个金属板之间，因此能够使电路元件71的安装所需的面积缩小，将半导体模块100小型化。另外，将电路元件71接合于在垂直方向相对的2个金属板之间，因此与将电路元件71在水平方向配置于金属板之上的情况相比，能够减少由金属板与电路元件71的热膨胀率之差引起的翘曲。因此，能够提高接合部分的可靠性。
另外，就本实施方式1中的半导体模块100而言，在相对的2个金属板(第1、第2金属板21、22)之间作为绝缘性材料配置绝缘基板32，至少1个电路元件71贯穿绝缘基板32而接合于在垂直方向相对的2个金属板之间。
根据本实施方式1中的半导体模块100，以将在两面具有第1、第2金属板21、22的绝缘基板32贯穿的方式接合电路元件71。因此，能够缩小电路元件71的安装所需的面积，并且将电路元件71接合于第1、第2金属板21、22之间。
另外，就本实施方式1中的半导体模块100而言，至少1个开关元件(第1、第2开关元件41、42)在两面具有电极，至少1个开关元件的两面的电极通过导电性接合材料8分别面接合至在垂直方向相对的2个金属板，至少1个电路元件71在两端具有电极，至少1个电路元件71的两端的电极通过导电性接合材料8分别面接合至在垂直方向相对的2个金属板。
在将电路元件71在水平方向接合于金属板之上的情况下，电路元件71的两端的电极单面接合，因此伴随温度变化，电路元件受到的应力变大。另一方面，在本实施方式1中，电路元件71的两端的电极通过导电性接合材料8分别面接合至在垂直方向相对的2个金属板，因此能够减少由于温度变化而使电路元件71受到的应力。因此，能够期待半导体模块100的可靠性的提高。
另外，就本实施方式1中的半导体模块100而言，金属板(第1、第2、第3金属板21、22、23)的厚度大于或等于0.25mm。通过增加金属板的厚度，从而能够降低开关元件41、42通电时的电流密度。另外，能够抑制金属板的发热，因此能够大电流化。
另外，就本实施方式1中的半导体模块100而言，绝缘基板31、32含有陶瓷材料，绝缘基板的厚度大于或等于0.32mm。通过将绝缘基板31、32的厚度设为大于或等于0.32mm，从而能够确保在例如将1200V的电压施加于半导体模块100的P电极、N电极间而使用的情况下所需的绝缘性能和可靠性、绝缘基板31、32的强度。
<实施方式1的第1变形例>
图3是实施方式1的第1变形例的半导体模块100A的剖视图。如图3所示，就半导体模块100A而言，电路元件71接合于在垂直方向相对的第1、第3金属板21、23之间。其他结构与实施方式1(图1)相同，因此省略说明。
图4是表示半导体模块100A的电路结构的图。如图4所示，电路元件71与串联连接的第1、第2开关元件41、42并联连接。例如，通过将电路元件71设为电容器，从而构成缓冲电路SC，该缓冲电路SC抑制伴随第1、第2开关元件41、42的通断而产生的浪涌电压。
<实施方式1的第2变形例>
图5是实施方式1的第2变形例的半导体模块100B的剖视图。如图5所示，就半导体模块100B而言，串联连接的电路元件71、72接合于在垂直方向相对的第1、第2金属板21、22之间。在这里，电路元件71与电路元件72通过导电性接合材料8直接串联连接。其他结构与实施方式1(图1)相同，因此省略说明。
图6是表示半导体模块100B的电路结构的图。如图6所示，串联连接的电路元件71、72与第1开关元件41并联连接。例如，通过将电路元件71、72设为电容器和电阻元件，从而构成缓冲电路SC，该缓冲电路SC抑制伴随第1开关元件41的通断而产生的浪涌电压。
就实施方式1的第2变形例中的半导体模块100B而言，至少1个电路元件是多个，串联连接的多个电路元件71、72接合于在垂直方向相对的2个金属板(第1、第2金属板21、22)之间。
因此，通过将串联连接的多个电路元件接合于在垂直方向相对的2个金属板之间，从而即使在安装多个电路元件的情况下，也能够将安装所需的面积缩小，将半导体模块100B小型化。
<实施方式2>
图7是本实施方式2中的半导体模块200的剖视图。如图7所示，半导体模块200具有：第1、第2、第3、第4金属板51、52、53、54，它们在水平方向延伸，在垂直方向层叠；第1、第2开关元件41、42；以及电路元件73。对于第1、第2开关元件41、42而言，与实施方式1是同样的，因此省略说明。另外，电路元件73与实施方式1中的电路元件71是同样的，因此省略说明。
第1金属板51的一端被引出至半导体模块200的封装件外部，成为P电极。另外，第3金属板53的一端被引出至半导体模块200的封装件外部，成为AC电极。另外，第4金属板54的一端被引出至半导体模块200的封装件外部，成为N电极。
第1、第3金属板51、53配置于绝缘基板61的表面侧的面，在绝缘基板61的背面侧的面配置有散热器9。第1、第3金属板51、53隔开绝缘所需的距离而配置于绝缘基板61之上。在绝缘基板62的两面配置有第2、第4金属板52、54。第4金属板54的一部分通过通孔等贯穿绝缘基板62而配置于与第2金属板52相同侧的面。
在第1金属板51与第2金属板52之间配置有第1开关元件41。第1开关元件41的两面的电极经由导电性接合材料8而分别面接合至在垂直方向相对的第1金属板51和第2金属板52。
在第3金属板53与第4金属板54之间配置有第2开关元件42。第2开关元件42的两面的电极经由导电性接合材料8而分别面接合至在垂直方向相对的第3金属板53和第4金属板54。
在第2金属板52与第3金属板53之间配置有电路元件73。电路元件73的两端的电极经由导电性接合材料8而分别面接合至在垂直方向相对的第2金属板52和第3金属板53。电路元件73被绝缘性树脂10封装。电路元件73与第1、第2开关元件41、42串联地接合在第1、第2开关元件41、42之间。
除电极P、N、AC的端部及散热器9之外，第1至第4金属板51、52、53、54、绝缘基板61、62、第1、第2开关元件41、42及电路元件73被绝缘性树脂10封装。
此外，在本实施方式2中，在第2、第3金属板52、53之间接合有电路元件73，但对电路元件进行接合的位置不限定于此。例如，也可以在第1、第2金属板51、52之间(即，电极P与电极AC之间)，或第3、第4金属板53、54之间(即，电极AC与电极N之间)，或第1、第4金属板51、54之间(即，电极P与电极N之间)接合电路元件73。
另外，在本实施方式2中将半导体模块200设为具有1个电路元件73的结构，但也可以设为具有多个电路元件73的结构。
另外，就半导体模块200而言，将第1至第4金属板51、52、53、54各自的厚度设为大于或等于0.25mm。在考虑到功率模块的通电和发热时，通过增加金属板的厚度，从而能够降低开关元件41、42通电时的电流密度。另外，能够抑制金属板的发热，因此能够大电流化。另外，金属板的主要材料是例如铝(Al)、铜(Cu)等。特别地，如果是铜，则电阻率低、热传导率也高，因此能够在大电流化的同时实现低热电阻化。
另外，就半导体模块200而言，绝缘基板61、62由有机树脂或陶瓷形成。在绝缘基板61、62由有机树脂形成的情况下，将绝缘基板61、62各自的厚度设为大于或等于0.1mm。通过将绝缘基板61、62的厚度设为大于或等于0.1mm，从而能够确保在例如将600V至6.5kV的范围的电压施加于半导体模块200的P电极、N电极间而使用的情况下所需的绝缘性能和可靠性。
在绝缘基板61、62由Al2O3、AlN、Si3N4等陶瓷形成的情况下，分别将绝缘基板61、62的厚度设为大于或等于0.32mm。通过将绝缘基板61、62的厚度设为大于或等于0.32mm，从而能够确保在例如将1200V的电压施加于半导体模块200的P电极、N电极间而使用的情况下所需的绝缘性能和可靠性、绝缘基板61、62的强度。
另外，就半导体模块200而言，在垂直方向相对的金属板间将绝缘性树脂10的厚度设为大于或等于0.1mm。通过将绝缘性树脂10的厚度设为大于或等于0.1mm，从而能够确保在例如将600V至6.5kV的范围的电压施加于半导体模块200的P电极、N电极间而使用的情况下所需的绝缘性能和可靠性。
<效果>
就本实施方式2中的半导体模块200而言，在相对的2个金属板(第2、第3金属板52、53)之间作为绝缘性材料配置绝缘性树脂10，至少1个电路元件73接合于在垂直方向相对的2个金属板之间，被绝缘性树脂10封装。
根据本实施方式2中的半导体模块200，将电路元件73接合于隔着绝缘性树脂10而相对的第2、第3金属板52、53之间。因此，能够缩小电路元件73的安装所需的面积，并且将电路元件73接合于第2、第3金属板52、53之间。
<实施方式3>
图8是本实施方式3中的半导体模块300的剖视图。本实施方式3中的半导体模块300相对于半导体模块100(图1)还具有电路元件74。其他结构与半导体模块100相同，因此省略说明。
如图8所示，在第1金属板21与第2金属板22的第1部分221之间配置有电路元件74。电路元件74的两端的电极经由导电性接合材料8而分别面接合至在垂直方向相对的第1金属板21和第2金属板22的第1部分221。电路元件74被绝缘性树脂10封装。电路元件74与第1开关元件41并联地接合在电极P与电极AC之间。
此外，在本实施方式3中，设为具有2个电路元件71、74的结构，但电路元件是多个即可。另外，在本实施方式3中，在第1、第2金属板21、22之间接合有电路元件71、74，但对电路元件进行接合的位置不限定于此。例如，也可以在第2、第3金属板22、23之间(即，电极AC与电极N之间)，或第1、第3金属板21、23之间(即，电极P与电极N之间)接合电路元件71、74。
<效果>
就本实施方式3中的半导体模块300而言，至少1个电路元件是多个，在多个金属板(第1、第2、第3金属板21、22、23)中的在垂直方向相对的2个金属板(第1、第2金属板21、22)之间作为绝缘性材料配置绝缘基板32，多个电路元件71、74中的至少1个电路元件71贯穿绝缘基板32而接合于相对的2个金属板之间，在多个金属板中的在垂直方向相对的2个金属板(第1、第2金属板21、22)之间作为绝缘性材料配置绝缘性树脂10，多个电路元件71、74中的至少1个电路元件74接合于相对的2个金属板之间，被绝缘性树脂10封装。
根据本实施方式3中的半导体模块300，将电路元件71接合于夹着绝缘基板32而相对的2个金属板之间，且将电路元件74接合于夹着绝缘性树脂10而相对的2个金属板之间。这样，电路元件71、74的配置的自由度变大，因此能够将电路元件71、74配置于对功率模块的振荡现象的抑制、通断损耗的减少等有效的位置。另外，通过将电路元件71、74内置于半导体模块300，从而能够将半导体模块300的与外部连接的电路结构简化。
<实施方式4>
图9是本实施方式4中的半导体模块400的剖视图。本实施方式4中的半导体模块400相对于半导体模块200(图7)还具有电路元件75。其他结构与半导体模块200相同，因此省略说明。
如图9所示，在第2金属板52与第4金属板54之间配置有电路元件75。电路元件75的两端的电极经由导电性接合材料8而分别面接合至在垂直方向相对的第2金属板52和第4金属板54。电路元件75将配置于第2金属板52与第4金属板54之间的绝缘基板62贯穿。
此外，在本实施方式4中，设为具有2个电路元件73、75的结构，但电路元件是多个即可。另外，对电路元件73、75进行接合的位置不被图9所限定。例如，也可以在第1、第2金属板51、52之间(即，电极P与电极AC之间)，或第3、第4金属板53、54之间(即，电极AC与电极N之间)，或第1、第4金属板51、54之间(即，电极P与电极N之间)接合电路元件73、75。
<效果>
就本实施方式4中的半导体模块400而言，至少1个电路元件是多个，在多个金属板(第1、第2、第3、第4金属板51、52、53、54)中的在垂直方向相对的2个金属板(第2、第4金属板52、54)之间作为绝缘性材料配置绝缘基板62，多个电路元件73、75中的至少1个电路元件75贯穿绝缘基板62而接合于相对的2个金属板之间，在多个金属板中的在垂直方向相对的2个金属板(第2、第3金属板52、53)之间作为绝缘性材料配置绝缘性树脂10，多个电路元件73、75中的至少1个电路元件73接合于相对的2个金属板之间，被绝缘性树脂10封装。
根据本实施方式4中的半导体模块400，将电路元件75接合于夹着绝缘基板62而相对的2个金属板之间，且将电路元件73接合于夹着绝缘性树脂10而相对的2个金属板之间。这样，电路元件73、75的配置的自由度变大，因此能够将电路元件73、75配置于对功率模块的振荡现象的抑制、通断损耗的减少等有效的位置。另外，通过将电路元件73、75内置于半导体模块400，从而能够将半导体模块400的与外部连接的电路结构简化。
如图10所示，通常为了抑制在使半导体模块的开关元件接通、断开时产生的过冲量、电压及电流的振荡现象，需要在半导体模块的外部连接缓冲电路SC。然而，在半导体模块的外部连接缓冲电路SC的情况下，由于将半导体模块与缓冲电路SC连接的配线部分的噪声、电路电感的影响，缓冲电路SC的效果有时会下降。因此，需要与将半导体模块和缓冲电路SC连接的配线部分相匹配地变更缓冲电路SC的结构。
另一方面，如图11所示，在上面说明的实施方式1至4中，能够将电路元件71至75设为电容器、电阻元件等无源元件而构成缓冲电路SC，将缓冲电路SC内置于半导体模块。通过将缓冲电路SC配置于半导体模块内部，从而能够将缓冲电路配置于靠近开关元件的位置，因此能够使缓冲电路有效地起作用。另外，无需与半导体模块外部的配线相匹配地变更缓冲电路SC的结构。
特别地，就开关元件使用了SiC的半导体模块而言，期待在大于或等于20kHz的高频下的使用。通断速度越快越容易产生振荡，因此需要使用了电容器等无源元件的缓冲电路SC。通过由无源元件构成缓冲电路，从而能够抑制振荡现象。另外，优选将缓冲电路SC设置于开关元件附近。
实施方式1至4中的半导体模块还具有缓冲电路SC，该缓冲电路SC抑制伴随开关元件41、42的通断而产生的浪涌电压，缓冲电路SC包含多个金属板的一部分及至少1个电路元件。因此，通过将缓冲电路SC内置于半导体模块，从而能够将缓冲电路配置于靠近开关元件的位置，因此能够使缓冲电路有效地起作用。另外，无需与半导体模块外部的配线相匹配地变更缓冲电路SC的结构。
在实施方式1至4中，电路元件71至75包含无源元件，无源元件是电容器或电阻元件。通过将电路元件71至75设为电容器、电阻元件等无源元件，从而能够由电路元件71至75构成缓冲电路。
此外，在实施方式1至4中，开关元件41、42也可以是IGBT。另外，开关元件41、42也可以是MOSFET。另外，开关元件41、42也可以含有碳化硅。实施方式1至4中的半导体模块的接合部分的可靠性提高，因此在通过IGBT、MOSFET等开关元件来处理大电流、高电压的用途中特别有效。另外，通过由碳化硅形成开关元件41、42，从而能够在高温环境中进行例如大于或等于20kHz的高速通断，但通过将电路元件71至75设为电容器、电阻元件等而构成缓冲电路，从而能够抑制开关元件的振荡现象。
此外，本发明能够在其发明的范围内，将各实施方式自由地进行组合，或对各实施方式进行适当的变形、省略。

Claims (14)

1.一种半导体模块，其中，
具有：
多个金属板，它们在水平方向延伸，在垂直方向层叠；
至少1个开关元件；以及
至少1个电路元件，
所述至少1个开关元件接合于在垂直方向相对的2个所述金属板之间，
所述至少1个电路元件接合于在垂直方向相对的2个所述金属板之间，
在所述多个金属板之间配置有绝缘性材料，
至少1个所述金属板与所述开关元件、所述电路元件这两者接合。
2.根据权利要求1所述的半导体模块，其中，
在相对的2个所述金属板之间作为所述绝缘性材料配置绝缘基板，
所述至少1个电路元件贯穿所述绝缘基板而接合于在垂直方向相对的2个所述金属板之间。
3.根据权利要求1所述的半导体模块，其中，
在相对的2个所述金属板之间作为所述绝缘性材料配置绝缘性树脂，
所述至少1个电路元件接合于在垂直方向相对的2个所述金属板之间，被所述绝缘性树脂封装。
4.根据权利要求1所述的半导体模块，其中，
所述至少1个电路元件是多个，
在多个所述金属板中的在垂直方向相对的2个所述金属板之间，作为所述绝缘性材料配置绝缘基板，
多个所述电路元件中的所述至少1个电路元件贯穿所述绝缘基板而接合于相对的2个所述金属板之间，
在多个所述金属板中的在垂直方向相对的2个所述金属板之间，作为所述绝缘性材料配置绝缘性树脂，
多个所述电路元件中的所述至少1个电路元件接合于相对的2个所述金属板之间，被所述绝缘性树脂封装。
5.根据权利要求1至3中任一项所述的半导体模块，其中，
所述至少1个电路元件是多个，
串联连接的多个所述电路元件接合于在垂直方向相对的2个所述金属板之间。
6.根据权利要求1至5中任一项所述的半导体模块，其中，
所述至少1个开关元件在两面具有电极，
所述至少1个开关元件的两面的所述电极通过导电性接合材料而分别面接合至在垂直方向相对的2个所述金属板，
所述至少1个电路元件在两端具有电极，
所述至少1个电路元件的两端的所述电极通过导电性接合材料而分别面接合至在垂直方向相对的2个所述金属板。
7.根据权利要求1至6中任一项所述的半导体模块，其中，
还具有缓冲电路，该缓冲电路抑制伴随所述开关元件的通断而产生的浪涌电压，
所述缓冲电路包含所述多个金属板的一部分及所述至少1个电路元件。
8.根据权利要求1至7中任一项所述的半导体模块，其中，
所述至少1个电路元件包含无源元件，
所述无源元件是电容器或电阻元件。
9.根据权利要求1至8中任一项所述的半导体模块，其中，
所述金属板的厚度大于或等于0.25mm。
10.根据权利要求2或4所述的半导体模块，其中，
所述绝缘基板含有陶瓷材料，
所述绝缘基板的厚度大于或等于0.32mm。
11.根据权利要求3或4所述的半导体模块，其中，
所述绝缘性树脂的厚度大于或等于0.1mm。
12.根据权利要求1至11中任一项所述的半导体模块，其中，
所述至少1个开关元件是IGBT。
13.根据权利要求1至11中任一项所述的半导体模块，其中，
所述至少1个开关元件是MOSFET。
14.根据权利要求12或13所述的半导体模块，其中，
所述至少1个开关元件含有碳化硅。
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CN111788769B (zh) * 2018-02-20 2023-12-12 三菱电机株式会社 电力用半导体模块以及使用该电力用半导体模块的电力变换装置
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CN114762105A (zh) 2020-01-17 2022-07-15 凯米特电子公司 用于高密度电子器件的部件组件和嵌入
WO2021146284A1 (en) 2020-01-17 2021-07-22 Kemet Electronics Corporation Structural lead frame
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JP2021182575A (ja) 2020-05-18 2021-11-25 現代自動車株式会社Hyundai Motor Company 半導体装置内部スナバ回路接続構造及びこれを用いたパワーモジュール構造

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004193476A (ja) * 2002-12-13 2004-07-08 Denso Corp 半導体装置
JP2006040926A (ja) * 2004-07-22 2006-02-09 Honda Motor Co Ltd 電子回路装置
US20120106220A1 (en) * 2010-11-03 2012-05-03 Denso Corporation Switching module
JP2013162019A (ja) * 2012-02-07 2013-08-19 Toyota Motor Corp 半導体モジュール

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3578366B2 (ja) 1995-10-17 2004-10-20 株式会社ルネサステクノロジ 混成集積回路装置
JP5074089B2 (ja) * 2007-04-27 2012-11-14 株式会社Ｊｖｃケンウッド 電子部品収容基板及びその製造方法
DE102008035993B4 (de) 2008-08-01 2018-10-11 Infineon Technologies Ag Leistungshalbleitermodul
JP5273095B2 (ja) 2010-05-24 2013-08-28 株式会社デンソー 半導体装置
JP6097013B2 (ja) 2012-02-29 2017-03-15 ローム株式会社 パワーモジュール半導体装置
US8916968B2 (en) 2012-03-27 2014-12-23 Infineon Technologies Ag Multichip power semiconductor device
JP2014187145A (ja) * 2013-03-22 2014-10-02 Toyota Motor Corp 半導体モジュール及びその製造方法
JP6053668B2 (ja) * 2013-12-20 2016-12-27 三菱電機株式会社 半導体モジュールおよび電力変換装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004193476A (ja) * 2002-12-13 2004-07-08 Denso Corp 半導体装置
JP2006040926A (ja) * 2004-07-22 2006-02-09 Honda Motor Co Ltd 電子回路装置
US20120106220A1 (en) * 2010-11-03 2012-05-03 Denso Corporation Switching module
JP2013162019A (ja) * 2012-02-07 2013-08-19 Toyota Motor Corp 半導体モジュール

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