CN107845609A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN107845609A
CN107845609A CN201611018352.5A CN201611018352A CN107845609A CN 107845609 A CN107845609 A CN 107845609A CN 201611018352 A CN201611018352 A CN 201611018352A CN 107845609 A CN107845609 A CN 107845609A
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China
Prior art keywords
protective layer
disclosure
connection pad
conducting shell
protuberance
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CN201611018352.5A
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English (en)
Inventor
林柏均
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Nanya Technology Corp
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Nanya Technology Corp
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Publication of CN107845609A publication Critical patent/CN107845609A/zh
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Abstract

一种半导体结构包含一基板；位于该基板上方的一接垫；位于该基板上方、局部覆盖该接垫且包含一突出部的一保护层，其中该突出部自该第一保护层突出且远离该基板；位于该第一保护层与自该第一保护层暴露的该接垫的一部分上方的一传导层；以及位于该传导层上方的一第二保护层，其中位于该突出部上方的该传导层自该第二保护层暴露。

Description

半导体结构及其制造方法
技术领域
本公开涉及包括一种具有保护层(passivation)的半导体结构，其中该保护层包含一突出部，经配置以吸收或缓和该半导体结构上方的应力。
背景技术
半导体装置对于许多现代应用而言是重要的。随着电子技术的进展，半导体装置的尺寸越来越小，而功能越来越大且整合的电路量越来越多。由于半导体装置的规模微小化，晶圆级晶片规模封装(wafer level chip scale packaging，WLCSP)广泛用于制造。在此等小半导体装置内，实施许多制造步骤。
然而，微型化规模的半导体装置的制造变得越来越复杂。制造半导体装置的复杂度增加可造成缺陷，例如电互连不良、发生破裂、或元件脱层(delamination)。因此，修饰结构与制造半导体装置有许多挑战。
上文的「现有技术」说明仅是提供背景技术，并未承认上文的「现有技术」说明公开本公开的标的，不构成本公开的现有技术，且上文的「现有技术」的任何说明均不应作为本案的任一部分。
发明内容
本公开的实施例提供一种半导体结构，该半导体结构包括一基板；位于该基板上方的一接垫；位于该基板上方、环绕该接垫并且包含一突出部的一第一保护层，其中该突出部自该第一保护层突出且远离该基板；位于该第一保护层与自该第一保护层暴露的该接垫的一部分上方的一传导层；以及位于该传导层上方的一第二保护层，其中位于该突出部上方的该传导层自该第二保护层暴露。
在本公开的实施例中，该传导层经配置与该突出部共形。
在本公开的实施例中，该传导层电连接该接垫。
在本公开的实施例中，该第一保护层与该突出部一体成形。
在本公开的实施例中，该第一保护层包含弹性体、环氧化合物、或聚酰亚胺。
在本公开的实施例中，该第二保护层包含一开口，该开口暴露位于该接垫上方的该传导层。
在本公开的实施例中，该第一保护层包含一第一介电层与一第二介电层，该第一介电层位于该基板上方并且局部覆盖该接垫，以及该第二介电层位于该第一介电层上方、局部覆盖该接垫并且包含自该第二介电层突出且远离开第一介电层的该突出部。
在本公开的实施例中，该半导体结构还包括一传导凸块，该传导凸块覆盖自该第二保护层暴露的该传导层。
在本公开的实施例中，该传导凸块经由该传导层而电连接至该接垫。
在本公开的实施例中，该传导凸块环绕该突出部，或该突出部突出至该传导凸块中。
本公开的实施例另提供一种半导体结构的制造方法，该制造方法包含：提供包含一凹部的一载体；配置一第一保护层于该载体上方并且填充该凹部；提供一基板，其中一接垫位于基板上方；接合该第一保护层与该基板以将该接垫插至该第一保护层中；移除该载体；移除该第一保护层的一部分以暴露该接垫的一暴露部分；配置一传导层于该第一保护层与该接垫的该暴露部分上方；配置一第二保护层于该传导层上方，其中该第一保护层包含一突出部，该突出部自该第一保护层突出且远离该基板，并且位于该突出部上方的该传导层自该第二保护层暴露。
在本公开的实施例中，该制造方法另包含：在配置该第一保护层之前，配置一释放膜于该载体与该凹部上方；或在接合该基板与该第一保护层之后，硬化该第一保护层；或在移除该载体之前，翻转与该第一保护层接合的该基板；或配置一传导凸块于自该第二保护层暴露的该传导层上方。
在本公开的实施例中，该第一保护层的配置包含进行旋涂工艺。
在本公开的实施例中，配置该传导层包含进行镀工艺、电镀、或无电镀工艺。
在本公开的实施例中，该突出部位于该凹部内。
在本公开的实施例中，该第一保护层包含一第一介电层与一第二介电层，其中该第一介电层位于该基板上方并且覆盖该接垫，该第二介电层位于该载体上方并且填充该凹部，该第一介电层接合该第二介电层，该制造方法包含移除该第一介电层的一部分与该第二介电层的一部分以暴露该接垫的该暴露部分。
在本公开的实施例中，该第一保护层包含一第一介电层与一第二介电层，该第一介电层位于该基板上方、覆盖该接垫并且包含自该第一介电层突出且远离该基板的该突出部，该第二介电层经配置与该第一介电层及该突出部共形，该制造方法包含移除该第一介电层的一部分与该第二介电层的一部分以暴露该接垫的该暴露部分。
本公开的实施例另提供一种半导体结构的制造方法，该制造方法包含：提供含有一凹部的一载体；配置一第二保护层于该载体上方；配置一传导层于该第二保护层与该凹部上方；配置一第一保护层于该传导层与该第二保护层上方；提供一基板，其中一接垫位于基板上方；接合该基板与该第一保护层以将该接垫插至该第一保护层中；配置该接垫于该传导层上方；移除该载体；移除该第二保护层的一部分以暴露该传导层的一暴露部分，其中该第一保护层包含一突出部，该突出部自该第一保护层突出且远离该基板，以及自该第二保护层暴露的该传导层的该暴露部分位于该突出部上方。
在本公开的实施例中，该第二保护层经配置与该凹部的侧壁共形，或该传导层经配置与该第二保护层共形。
在本公开的实施例中，该方法另包含：在配置该第二保护层之前，配置一释放膜于该载体与该凹部上方；或在接合该基板与该第一保护层之后，硬化该第一保护层；或在移除该载体之前，翻转与该第一保护层接合的该基板；或配置一传导凸块于自该第二保护层暴露的该传导层的该暴露部分上方。
上文已相当广泛地概述本公开的技术特征及优点，俾使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本领域技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本公开相同的目的。本领域技术人员亦应了解，这类等效建构无法脱离后附的权利要求所界定的本公开的精神和范围。
附图说明
参阅详细说明与权利要求结合考虑附图时，可得以更全面了解本申请案的公开内容，附图中相同的元件符号是指相同的元件。
图1为剖面示意图，例示本公开的实施例的半导体结构。
图2至图4为剖面示意图，例示本公开的实施例中具有各种形状的突出部的半导体结构。
图5为剖面示意图，例示本公开的实施例的半导体结构，该半导体结构具有暴露的传导层的一部分。
图6为剖面示意图，例示本公开的实施例的半导体结构，该半导体结构具有球形的传导凸块。
图7为剖面示意图，例示本公开的实施例的半导体结构，该半导体结构包含两个介电层。
图8为剖面示意图，例示本公开的实施例的半导体结构，该半导体结构具有暴露的传导层的一部分。
图9为剖面示意图，例示本公开的实施例的半导体结构。
图10为剖面示意图，例示本公开的实施例的半导体结构，该半导体结构具有暴露的传导层的一部分。
图11为流程图，例示本公开的实施例的半导体结构的制造方法。
图12至图23为示意图，例示本公开的实施例通过图11的方法制造半导体结构。
图24为流程图，例示本公开的实施例的半导体结构的制造方法。
图25至图36为示意图，例示本公开的实施例通过图24的方法制造半导体结构。
图37为流程图，例示本公开的实施例半导体结构的制造方法。
图38至图49为示意图，例示本公开的实施例通过图37的方法制造半导体结构。
图50为流程图，例示本公开的实施例半导体结构的制造方法。
图51至图62为示意图，例示本公开的实施例通过图50的方法制造半导体结构。
附图标记说明：
100 半导体结构
101 基板
101a 第一表面
101b 第二表面
102 接垫
103 第一保护层
103a 第一开口
103b 突出部
103c 第一介电层
103d 第二介电层
103e 开口
104 传导层
105 第二保护层
105a 第二开口
106 传导凸块
107 载体
107a 凹部
200 半导体结构
300 半导体结构
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
「一实施例」、「实施例」、「例示实施例」、「其他实施例」、「另一实施例」等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用「在实施例中」一语并非必须指相同实施例，然而可为相同实施例。
本公开涉及一种半导体结构，该半导体结构包括位于基板上方的保护层且包含自该保护层突出且远离该基板的突出部。为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制本领域技术人员已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的较佳实施例详述如下。然而，除了详细说明之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容，而是由权利要求定义。
半导体结构经由连接器，例如凸块(bump)、柱(pillar)、杆(post)或类似物而电连接另一晶片或封装。该连接器位于该半导体结构上并且经配置以与另一晶片或封装接合。在接合连接器与另一晶片或封装之后，应力或力会作用于该连接器上并且对于该连接器与连接器下方的那些元件造成破坏。因此，连接器中可能产生破裂或甚至遍及至元件中。可能发生元件的脱层。因此，发生电连接故障。
本公开提供一种半导体结构。该半导体结构包括一保护层位于基板上方并且包含自该保护层突出且远离该基板的突出部。该突出部可提供弹性，因而在制造过程中或是热工艺过程中，可吸收或缓和半导体结构上方的应力。例如，当连接器配置于突出部上方或是当配置于突出部上方的连接器与另一半导体晶片或封装接合时，应力可作用于半导体结构上方。因此，可最小化或防止半导体结构中的破裂与元件的脱层。可改良半导体结构的可信赖度。
图1为剖面示意图，例示本公开的实施例的半导体结构100。在本公开的实施例中，半导体结构100包含基板101、接垫102、第一保护层103、传导层104、第二保护层150、以及传导凸块106。在本公开的实施例中，半导体结构100为晶粒、晶片或半导体封装的一部分。
在本公开的实施例，基板101经制造具有预定的功能性电路于其上。在本公开的实施例中，基板101包含数个传导迹线以及由该传导迹线连接的数个电子元件，例如晶体管与二极管。在本公开的实施例中，基板101为晶圆。在本公开的实施例中，基板101包含半导体材料，例如硅、锗、镓、砷、以及其组合。在本公开的实施例中，基板101为硅基板。在本公开的实施例中，基板101包含材料例如陶瓷、玻璃、或类似物。在本公开的实施例中，基板101为玻璃基板。在本公开的实施例中，基板101为四边形、矩形、正方形、多边形、或任何其他合适的形状。
在本公开的实施例中，基板101包含第一表面101a以及与第一表面101a对立的第二表面101b。在本公开的实施例中，第一表面101a为正面或主动面，其中电路或电子元件位于其上。在本公开的实施例中，第二表面101b为背面或非主动面。
在本公开的实施例中，接垫102位于基板101上方。在本公开的实施例中，接垫102位于基板101的第一表面101a上方或基板101的第一表面101a内。在本公开的实施例中，接垫102位于基板101的第二表面101b上方。在本公开的实施例中，接垫102电连接至基板101中的电路或电子元件。在本公开的实施例中，接垫102电连接至基板101外部的电路，因而基板101中的电路可经由接垫102电连接至基板101外部的电路。在本公开的实施例中，在本公开的实施例中，接垫102经配置以接收传导结构。在本公开的实施例中，接垫102为晶粒接垫或接合接垫。在本公开的实施例中，接垫102包含金、银、铜、镍、钨、铝、钯、以及/或其合金。
在本公开的实施例中，第一保护层103位于基板102上方。在本公开的实施例中，第一保护层103位于基板101的第一表面101a或第二表面101b上方。在本公开的实施例中，第一保护层103局部覆盖接垫102，因而自第一保护层103暴露接垫102的一部分。在本公开的实施例中，第一保护层103环绕接垫102。在本公开的实施例中，第一保护层103包含第一开口103a于接垫102上方。在本公开的实施例中，通过第一开口103a，自第一保护层103暴露接垫102的该暴露部分。在本公开的实施例中，自第一保护层103暴露的接垫102的该暴露部分可接收传导结构或电连接至基板101外部的电路。
在本公开的实施例中，第一保护层103经配置以提供对于基板101的电性绝缘与湿度保护，因而基板101与周围环境隔离。在本公开的实施例中，第一保护层包含彼此堆叠的一或多层的介电材料。在本公开的实施例中，第一保护层103由介电材料形成，例如弹性体、环氧化合物、聚酰亚胺、聚合物、树脂、氧化物、或类似物。在本公开的实施例中，第一保护层103包含有弹性的、可变形的、可挠的、或软的材料，因而第一保护层103可提供可挠性或弹性。在本公开的实施例中，第一保护层103为有弹性的、可变形的、或可压缩的。
在本公开的实施例中，第一保护层103包含从第一保护层103突出且远离基板101的突出部103b。在本公开的实施例中，当第一保护层103位于第一表面101a上方时，突出部103b位于第一表面101a上方且突出远离基板101a。在本公开的实施例中，当第一保护层103位于第二表面101b上方时，突出部103b位于第二表面101b上方且突出远离第二表面101b。在本公开的实施例中，突出部103b与第一保护层103一体成形或是与第一保护层103分离。在本公开的实施例中，突出部103b延伸垂直于基板101。
在本公开的实施例中，突出部103b包含弹性体、环氧化合物、聚酰亚胺、聚合物、树脂、氧化物、或类似物。在本公开的实施例中，突出部103b包含有弹性的、可变形的、可挠的、或软的材料，因而突出部103b可提供可挠性或弹性。在本公开的实施例中，突出部103b为有弹性的、可变形的、或可压缩的。
在本公开的实施例中，突出部103b为圆筒形、或突出部103b的剖面为矩形或四边形。如图2所示，在本公开的实施例中，突出部103b为圆顶形(dome shape)。如图3所示，在本公开的实施例中，突出部103b为棱柱状，或突出部103b的剖面为三角形。如图4所示，在本公开的实施例中，突出部103b为多边形或不规则形。
参阅图1，在本公开的实施例中，传导层104位于第一保护层103上方。在本公开的实施例中，传导层104沿着第一保护层103的表面配置。在本公开的实施例中，传导层104位于自第一保护层103暴露的接垫的该暴露部分上方，并且位于第一开口103a内。在本公开的实施例中，传导层104电连接接垫102。在本公开的实施例中，传导层104位于突出部103b上方并且环绕突出部103b。在本公开的实施例中，传导层104与突出部103b共形配置。在本公开的实施例中，传导层104沿着突出部103b的外表面配置。在本公开的实施例中，传导层104为重布层(redistribution layer，RDL)。在本公开的实施例中，传导层104包含铜、金、银、镍、焊料、锡、铅、钨、铝、钛、钯、以及/或其合金。
在本公开的实施例中，第二保护层105位于传导层104上方。在本公开的实施例中，第二保护层105至少局部覆盖传导层104。在本公开的实施例中，自第二保护层105暴露位于突出部103b上方的传导层104。在本公开的实施例中，自第二保护层105暴露传导层104的一部分与突出部103b的一部分。在本公开的实施例中，第二保护层105环绕突出部103b以及位于突出部103b上方的传导层104。在本公开的实施例中，突出部103b自第二保护层105突出。在本公开的实施例中，第二保护层105包含与第一保护层103相同或不同的材料。在本公开的实施例中，第二保护层105包含介电材料，例如氧化物、氮化物、聚合物、或类似物。
如图5所示，在本公开的实施例中，第二保护层105包含第二开口105a，暴露位于接垫102上方的传导层104。在本公开的实施例中，第二开口105a位于接垫102上方。在本公开的实施例中，第二开口105a位于第一开口103a上方。在本公开的实施例中，通过第二开口105a而自第二保护层105暴露的传导层104可接收传导结构，并且可电连接至传导结构或外部电路。
参阅图1，在本公开的实施例中，传导凸块106位于第二保护层105上方。在本公开的实施例中，传导凸块106位于突出部103b与自第二保护层105暴露的传导层104上方，或是环绕突出部103b与自第二保护层105暴露的传导层104。在本公开的实施例中，传导凸块106覆盖自第二保护层105暴露的传导层104。在本公开的实施例中，突出部103b至少部分突出至传导凸块106中。在本公开的实施例中，突出部103b自第一保护层103突出至传导凸块106。在本公开的实施例中，传导凸块106经由传导层104电连接至接垫102。
在本公开的实施例中，传导凸块106经配置以接合传导结构、晶片或封装。在本公开的实施例中，传导凸块106为焊料接合、焊料凸块、焊球、球栅阵列(ball grid array，BGA)球、受控的塌陷晶片连接(controlled collapse chip connection，C4)凸块、微凸块、或类似者。在本公开的实施例中，传导凸块106为传导柱或杆。在本公开的实施例中，传导凸块106包含铅、锡、铜、金、银、镍、或其组合。在本公开的实施例中，传导凸块106为圆筒形。如图6所示，在本公开的实施例中，传导凸块106为球形或半球形。
在本公开的实施例中，突出部103b经配置以吸收施加于其上方的力。在本公开的实施例中，突出部103b可吸收施加于传导凸块106或半导体结构100上方的力，因而可最小化或防止传导凸块106或半导体结构100中发生破裂。
图7为剖面图，例示本公开的实施例的半导体结构200。在本公开的实施例中，半导体结构200包含基板101、接垫102、传导层104、第二保护层105以及传导凸块106，其具有与上述或图1至图6任一者所示的类似架构。
在本公开的实施例中，半导体结构200包含第一保护层103位于该基板101上方。在本公开的实施例中，第一保护层103包含第一介电层103c与第二介电层103d。在本公开的实施例中，第一介电层103c位于基板101上方并且局部覆盖接垫102。在本公开的实施例中，第一介电层103c位于基板101的第一表面101a或第二表面101b上方。在本公开的实施例中，第二介电层103d位于第一介电层103c上方、局部覆盖接垫102，以及包含自第二介电层103d突出且远离第一介电层103c的突出部103b。在本公开的实施例中，突出部103b与第二介电层103d一体成形，或是与第二介电层103d分离。在本公开的实施例中，传导层104位于第二介电层103d上方。在本公开的实施例中，第二保护层105位于第二介电层103d上方。
在本公开的实施例中，开口103e位于接垫102上方。在本公开的实施例中，开口103e位于接垫102上方。在本公开的实施例中，开口103e延伸穿过第二介电层103d且延伸穿过第一介电层103c的至少一部分，暴露接垫102的一部分。在本公开的实施例中，传导层104的至少一部分位于接垫102上方并且位于开口103e内。在本公开的实施例中，传导层104位于第二介电层103d上方。如图8所示，在本公开的实施例中，第二保护层105包含位于开口103e上方的第二开口105a。
在本公开的实施例中，第一介电层103c包含与第二介电层103d相同或不同的材料。在本公开的实施例中，第一介电层103c包含氧化物、氮化物、聚合物、或类似者。在本公开的实施例中，第二介电层103d包含弹性体、环氧化合物、聚酰亚胺、聚合物、树脂、氧化物、或类似者。在本公开的实施例中，第二介电层103d包含有弹性的、可变形的、可挠的、或软的材料，因而第二介电层103d可提供可挠性或弹性。在本公开的实施例中，第二介电层103d为有弹性的、可变形的、或可压缩的。
如图8所示，在本公开的实施例中，第一介电层103c包含自第一介电层103c突出且远离基板101的突出部103b。在本公开的实施例中，突出部103b与第一介电层103c一体成形，或是与第一介电层103c分离。在本公开的实施例中，第二介电层103d位于第一介电层103c上方，并且与自第一介电层103c突出的突出部103b共形。
图9与图10为剖面图，例示本公开的实施例的半导体结构300。在本公开的实施例中，半导体结构300具有与上述或图1至图8任一者所示的半导体结构100或200类似的架构。
在本公开中，亦提供半导体结构100的制造方法。在本公开的实施例中，可通过图11的方法400，形成半导体结构100。方法400包含一些操作，以及描述与说明不视为操作顺序的限制。方法400包含一些步骤(401、402、403、404、405、406、407、408与409)。
在步骤401中，提供或接收载体107，如图2所示。在本公开的实施例中，载体107由半导体材料制成。在本公开的实施例中，载体107包含硅、锗、镓、砷、以及其组合物。在本公开的实施例中，载体107微半导体载体或晶圆。在本公开的实施例中，载体107为硅载体。在本公开的实施例中，载体107为一模(mold)。在本公开的实施例中，载体107为四边形、矩形、正方形、多边形、或任何其他合适的形状。
在本公开的实施例中，载体107包含凹部107a延伸至载体107中。在本公开的实施例中，移除载体107的一部分而形成凹部107a。在本公开的实施例中，可通过蚀刻工艺或其他合适的工艺，形成凹部107a。
在步骤402中，第一保护层103位于载体107上方，如图13所示。在本公开的实施例中，第一保护层103位于载体107上方并且填充凹部107a。在本公开的实施例中，突出部103b形成于凹部107a内。在本公开的实施例中，突出部103b受到载体107环绕。在本公开的实施例中，在配置第一保护层103之前，释放膜位于载体107上方，并且沿着凹部107a配置。在本公开的实施例中，释放膜经配置以便于自第一保护层103移除载体107，因此，第一保护层103而后可自载体107释放。
在本公开的实施例中，第一保护层103由介电材料形成，例如弹性体、环氧化合物、聚酰亚胺、聚合物、树脂、氧化物、或类似者。在本公开的实施例中，第一保护层103包含有弹性的、可变形的、或软的材料，因而第一保护层103可提供可挠性或弹性。在本公开的实施例中，第一保护层103为有弹性、可变形的、或可压缩的。在本公开的实施例中，通过化学气相沉积(CVD)、等离子体辅助化学气相沉积(PECVD)、旋涂、或任何其他合适的工艺，配置第一保护层103。在本公开的实施例中，第一保护层103与突出部103b具有与上述或图1至图10任一者所示的类似架构。
在步骤403中，提供或接收基板101，如图14所示。在本公开的实施例中，基板101包含第一表面101a以及与第一表面101a对立的第二表面101b。在本公开的实施例中，基板101包含数个传导线，以及由该等传导线连接的数个电子元件，例如晶体管与二极管。在本公开的实施例中，基板101为半导体基板。在本公开的实施例中，基板101包含硅、锗、镓、砷、以及其组合。在本公开的实施例中，基板101为硅基板。在本公开的实施例中，基板101为四边形、矩形、正方形、多边形、或任何其他合适的形状。在本公开的实施例中，基板101具有与上述或图1至图10任一者所示的类似架构。
在本公开的实施例中，基板101包含位于其上的接垫102。在本公开的实施例中，接垫102位于基板101的第一表面101a或第二表面101b上方。在本公开的实施例中，接垫102电连接至基板101中的电路。在本公开的实施例中，接垫102经配置以接收传导结构。在本公开的实施例中，接垫102为晶粒接垫或接合接垫。在本公开的实施例中，接垫102包含金、银、铜、镍、钨、铝、钯以及/或其合金。在本公开的实施例中，通过电镀或任何其他合适的工艺，形成接垫102。在本公开的实施例中，接垫102具有与上述或图1至图10任一者所示的类似架构。在本公开的实施例中，基板101与接垫102翻转如图15所示，用于后续工艺。
在步骤404中，第一保护层103与基板101接合，如图16所示。在本公开的实施例中，基板101的第一表面101a或第二表面101b位于第一保护层103上方并且与第一保护层接合，以及接垫102被插入第一保护层103中。在本公开的实施例中，通过将基板101压向第一保护层103、于基板101上方朝向第一保护层103施力、将载体107压向基板101、或于载体107上方朝向基板101施力，而将接垫102插入第一保护层103中。在本公开的实施例中，在接合基板101与第一保护层103以及插入接垫102于第一保护层103中之后，硬化第一保护层103。在本公开的实施例中，通过硬化工艺或其他合适的工艺，固化第一保护层，因而基板101接合第一保护层103，以及接垫102受到第一保护层103囊封。
在步骤405中，移除载体107，如图17或图18所示。在本公开的实施例中，自第一保护层103移除载体107，因而自载体107释放第一保护层103。在本公开的实施例中，在移除载体107之前或之后，翻转与第一保护层103接合的基板101。在本公开的实施例中，载体107可重复使用，因而在移除之后，可再次使用载体107。在本公开的实施例中，例如，可通过重复实施步骤301至305以制造如图17或图18所示的中间结构，而再次使用载体107。在本公开的实施例中，突出部103b与第一保护层103为一体成形。在本公开的实施例中，突出部103b自第一保护层103突出且远离基板101。
在步骤406中，移除第一保护层103的一部分以暴露接垫102的一部分，如图19所示。在本公开的实施例中，位于接垫102的该暴露部分上方的第一保护层103的该部分被移除，以形成第一开口103a。在本公开的实施例中，通过微影与蚀刻工艺或任何其他合适的工艺，移除第一保护层103的该部分。在本公开的实施例中，自第一保护层103暴露接垫102的该暴露部分。在本公开的实施例中，第一开口103a具有与上述或图1至图10任一者所示的类似架构。
在步骤407中，传导层104位于第一保护层103上方，如图20所示。在本公开的实施例中，传导层104位于自第一保护层103暴露的接垫102的该暴露部分上方。在本公开的实施例中，传导层104经配置与突出部103b的外表面及第一开口103a的侧壁共形。在本公开的实施例中，传导层104电连接接垫102。在本公开的实施例中，通过配置光致抗蚀剂(PR)于第一保护层103上方、移除该PR的一部分因而图案化该PR、配置传导材料于该RP的移除的部分内，而后移除该PR，形成传导层104。在本公开的实施例中，通过进行镀工艺、电镀或任何其他合适的工艺，配置传导材料。在本公开的实施例中，通过光微影、蚀刻或任何其他合适的工艺，图案化该PR。在本公开的实施例中，通过蚀刻、剥除或任何其他合适的工艺，完全移除该PR。在本公开的实施例中，传导层104具有与上述或图1至图8任一者所示的类似架构。
在步骤408中，第二保护层105位于传导层104上方，如图21所示。在本公开的实施例中，第二保护层105局部覆盖传导层104。在本公开的实施例中，位于突出部103b上方的传导层104自第二保护层105突出或暴露。在本公开的实施例中，通过CVD、PECVD、旋凸、或任何其他合适的工艺，配置第二保护层105。在本公开的实施例中，第二保护层105包含与第一保护层103相同或不同的材料。在本公开的实施例中，第二保护层105包含介电材料，例如氧化物、氮化物、聚合物、或类似者。在本公开的实施例中，第二保护层105具有与上述或图1至图10任一者所示的类似架构。
在步骤409中，传导凸块106位于自第二保护层105暴露的传导层104上方，如图2所示。在本公开的实施例中，传导凸块106位于突出部103b与传导层104的一部分上方，或是环绕突出部103b与传导层104的一部分上方。在本公开的实施例中，传导凸块106经由传导层104而电连接至接垫102。在本公开的实施例中，突出部103b突出至传导凸块106中。在本公开的实施例中，通过模板粘合(stencil pasting)、植球、回焊、硬化、或任何其他合适的工艺，形成传导凸块106。在本公开的实施例中，传导凸块106为焊料接合、焊料凸块、焊球、球栅阵列(BGA)球、或类似者。在本公开的实施例中，传导凸块106为传导柱或杆。在本公开的实施例中，传导凸块106包含铅、锡、铜、金、银、镍、或其组合。
在本公开的实施例中，移除第二保护层的一部分以形成第二开口105a，如图23所示。在本公开的实施例中，形成半导体结构100，其具有与上述或图1至图6任一者所示的类似架构。在本公开的实施例中，突出部103b或第一保护层103经配置以于配置或形成传导凸块106过程中吸收力。在本公开的实施例中，步骤401至405的实施可与步骤406至409平行。
在本公开的实施例中，半导体结构200可由图24的方法500形成。方法500包含一些操作，以及描述与说明不视为操作顺序的限制。方法500包含一些步骤(501、502、503、504、505、506、507、508与509)。
在步骤501中，提供或接收包含凹部107a的载体107，如图25所示。在本公开的实施例中，步骤501类似于步骤401。
在步骤502中，第二介电层103d位于载体107上方，并且填充凹部107a，如图26所示。在本公开的实施例中，突出部103b形成于凹部107中。在本公开的实施例中，突出部103b与第二介电层103d一体成形。在本公开的实施例中，第二介电层103d包含弹性体、聚酰亚胺、聚合物、树脂、环氧化合物、或类似者。在本公开的实施例中，通过CVD、旋涂、或任何其他合适的工艺，配置第二介电层103d。在本公开的实施例中，第二介电层103d具有与上述或图7或图8所示的类似架构。在本公开的实施例中，释放膜位于载体107上方并且沿着凹部107a配置。在本公开的实施例中，释放膜经配置以便于自第二介电层103d移除载体107，因此，而后可自载体107释放第二介电层103d。
在步骤503中，提供或接收基板101，如图27所示。在本公开的实施例中，基板101包含位于基板101上方的接垫102，以及位于基板101上方且覆盖接垫102的第一介电层103c。在本公开的实施例中，第一介电层103c包含氧化物、氮化物、聚合物、或类似者。在本公开的实施例中，第一介电层103c包含与第二介电层103d相同或不同的材料。在本公开的实施例中，通过CVD、旋涂、或任何其他合适的工艺，配置第一介电层103c。在本公开的实施例中，翻转包含接垫102与第一介电层103c的基板101，如图28所示。在本公开的实施例中，第一介电层103c具有与上述或图7或图8所示的类似架构。
在步骤504中，第一介电层103c与第二介电层103d接合，如图29所示。在本公开的实施例中，第一介电层103c位于第二介电层103d上方，而后通过硬化工艺或其他合适的工艺，固化第一介电层103c与第二介电层103d，因而第一介电层103c接合第二介电层103d。在本公开的实施例中，形成包含第一介电层103c与第二介电层103d的第一保护层103。在本公开的实施例中，第一保护层103具有与上述或图1至图10所示的类似架构。
在步骤505中，移除载体107，如图30或图31所示。在本公开的实施例中，自第二介电层103d移除载体107，因而自载体107释放第二介电层103d。在本公开的实施例中，在移除载体107之前或之后，与第一介电层103c接合的基板101、接垫102、第一介电层103c及第二介电层103d被翻转。在本公开的实施例中，载体107可重复使用，因而在移除之后，再次使用载体107。在本公开的实施例中，步骤505类似于步骤405。
在步骤506中，移除第一介电层103c的一部分以及第二介电层103d的一部分，以暴露接垫102的一部分，如图32所示。在本公开的实施例中，形成开口103e，以暴露该接垫102的该暴露部分。在本公开的实施例中，通过光微影与蚀刻工艺或任何其他合适的工艺，移除位于接垫102上方的第一介电层103的该部分以及第二介电层103d的该部分。在本公开的实施例中，开口103e具有与上述或图7或图8所示的类似架构。
在步骤507中，传导层104位于第二介电层103e上方，如图33所示。在本公开的实施例中，传导层104位于自第一介电层103c与第二介电层103d暴露的接垫102上方。在本公开的实施例中，传导层104经配置与突出部103b的外表面与开口103e的侧壁共形。在本公开的实施例中，传导层104电连接接垫102。在本公开的实施例中，步骤407类似于步骤307。
在步骤508中，第二保护层105位于第二介电层103d上方并且覆盖传导层104的一部分，如图34所示。在本公开的实施例中，位于突出部103b上方的传导层104自第二保护层105突出或暴露。在本公开的实施例中，步骤508类似于步骤408。
在步骤509中，传导凸块106位于突出部103b上方，并且覆盖自第二保护层105暴露的传导层104的一部分，如图35或图36所示。在本公开的实施例中，步骤509类似于步骤409。在本公开的实施例中，形成半导体结构200，其具有如上述或图7或图8所示的类似架构。
在本公开的实施例中，可通过图37的方法600形成半导体结构300。方法600包含一些操作，以及描述与说明不视为操作顺序的限制。方法600包含一些步骤(601、602、603、604、605、606、607、608与609)。
在步骤601中，提供或接收包含凹部107a的载体107，如图38所示。在本公开的实施例中，步骤601类似于步骤401或步骤501。
在步骤602中，第二保护层105位于载体107与凹部107a上方，如图39所示。在本公开的实施例中，第二保护层105经配置与载体107的表面及凹部107a的侧壁共形。在本公开的实施例中，通过CVD、旋涂或任何其他合适的工艺，配置第二保护层105。在本公开的实施例中，第二保护层105具有与上述或图1至图10任一者所示的类似架构。
在本公开的实施例中，在配置第二保护层105之前，释放膜位于载体107上方并且沿着凹部107a配置。在本公开的实施例中，释放膜经配置以便于自第二保护层105移除载体107，因此，而后可自载体107释放第二保护层105。
在步骤603中，传导层104位于第二保护层105上方，如图40所示。在本公开的实施例中，传导层104经配置与第二保护层105共形。在本公开的实施例中，传导层104的一部分位于凹部107a内。在本公开的实施例中，通过进行镀工艺、电镀、或任何其他合适的工艺，配置传导层104。在本公开的实施例中，传导层104具有与上述或图1至图10任一者所示的类似架构。
在步骤604中，第一保护层103位于传导层104与第二保护层103上方，如图41所示。在本公开的实施例中，第一保护层103覆盖传导层104。在本公开的实施例中，第一保护层103的一部分位于凹部107a内，以形成突出部103b。在本公开的实施例中，突出部103b与第一保护层103一体成形。在本公开的实施例中，通过CVD、旋涂、或任何其他合适的操作，配置第一保护层103。在本公开的实施例中，第一保护层103具有与上述或图1至图10任一者所示的类似架构。
在步骤605中，提供或接受包含接垫102的基板101，如图42所示。在本公开的实施例中，步骤605类似于步骤403。在本公开的实施例中，基板101与接垫102被翻转，如图43所示。
在步骤606中，基板101接合第一保护层103，如图44所示。在本公开的实施例中，在接合基板101与第一保护层103的过程中，接垫102被插入至第一保护层103中，以将接垫102配置于传导层104上方。在本公开的实施例中，通过硬化工艺或其他合适的工艺，固化第一保护层103，因而基板101接合第一保护层103。在本公开的实施例中，在接合之后，接垫102与传导层104接面且电性连接。在本公开的实施例中，接垫102受到第一保护层103囊封。
在步骤607中，移除载体107，如图45或图46所示。在本公开的实施例中，自载体107释放第二保护层105。在本公开的实施例中，在移除载体107之前或之后，接合第一保护层103的基板101被翻转。在本公开的实施例中，载体107可重复使用，在移除之后，可再次使用载体107。在本公开的实施例中，例如，可通过重复实施步骤601至607以制造如图45或图46所示的中间结构，再次使用载体107。在本公开的实施例中，突出部103b自第一保护层103突出且远离基板101。
在步骤608中，移除第二保护层105的一部分，以暴露传导层104的一部分，如图47所示。在本公开的实施例中，通过光微影与蚀刻工艺或任何其他合适的工艺，移除位于突出部103b上方的第二保护层105的该部分。
在步骤609中，传导凸块106位于自第二保护层105暴露的传导层的该暴露部分上方，如图48所示。在本公开的实施例中，步骤609类似于步骤409或步骤509。
在本公开的实施例中，移除第二保护层105的一部分以形成第二开口105a，如图49所示。在本公开的实施例中，形成半导体结构300，其具有与上述或图9或图10所示的类似架构。在本公开的实施例中，步骤601至607的实施可与步骤608至609平行。
在本公开的实施例中，可通过图50的方法700，形成半导体结构300。方法700包含一些操作，以及描述与说明不视为操作顺序的限制。方法700包含一些步骤(701、702、703、704、705、706、707、708与709)。
在步骤701中，提供或接收包含凹部107a的载体107，如图51所示。在本公开的实施例中，步骤701类似于步骤601。
在步骤702中，第二保护层105位于载体107上方且位于凹部107a内，如图53所示。在步骤703中，移除第二保护层105的一部分，如图52所示。
在本公开的实施例中，可省略步骤703，在步骤702过中，第二保护层105仅位于载体107的表面上方，如图52所示。在本公开的实施例中，第二保护层105位于载体107的表面上方。在本公开的实施例中，第二保护层105未位于凹部107a内。
在本公开的实施例中，通过CVD、旋涂、或任何其他合适的工艺，配置第二保护层105。在本公开的实施例中，第二保护层105具有与上述或图1至图10任一者所示的类似架构。
在本公开的实施例中，在配置第二保护层105之前，释放膜位于载体107上方并且沿着凹部107a配置。在本公开的实施例中，释放膜经配置以便于自第二保护层105移除载体107，因此，而后可自载体107释放第二保护层105。
在步骤704中，传导层104位于第二保护层105上方，如图54所示。在本公开的实施例中，传导层104经配置与第二保护层105共形。在本公开的实施例中，传导层104的一部分位于凹部107a内。在本公开的实施例中，通过进行镀工艺、电镀、或任何其他合适的工艺，配置传导层104。在本公开的实施例中，传导层104具有与上述或图1至图10所示的类似架构。
在步骤705中，第一保护层103位于传导层104与第二保护层103上方，如图55所示。在本公开的实施例中，步骤705类似于步骤604。
在步骤706中，提供或接收包含接垫102的基板101，如图56所示。在本公开的实施例中，步骤706类似于步骤605。在本公开的实施例中，基板101与接垫102被翻转，如图57所示。
在步骤707中，基板101与第一保护层103接合，如图58所示。在本公开的实施例中，步骤707类似于步骤606。
在步骤708中，移除载体107，如图59或图60所示。在本公开的实施例中，步骤708类似于步骤607。
在步骤709，传导凸块106位于自第二保护层105暴露的传导层104的该暴露部分上方，如图61所示。在本公开的实施例中，步骤709类似于步骤609。
在本公开的实施例中，移除第二保护层105的一部分以形成第二开口105a，如图62所示。在本公开的实施例中，形成半导体结构300，其具有与上述或图9或图10所示的类似架构。在本公开的实施例中，步骤701至708的实施可与步骤709平行。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的精神与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
再者，本申请案的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。本领域技术人员可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，此等工艺、机械、制造、物质组成物、手段、方法、或步骤包含于本申请案的权利要求内。

Claims (20)

1.一种半导体结构，包括：
一基板；
一接垫，位于该基板上方；
一第一保护层，位于该基板上方，环绕该接垫，并且包含一突出部，该突出部自该第一保护层突出且远离该基板；
一传导层，位于该第一保护层与自该第一保护层暴露的该接垫的一部分上方；以及
一第二保护层，位于该传导层上方；
其中位于该突出部上方的该传导层自该第二保护层暴露。
2.如权利要求1所述的半导体结构，其中该传导层经配置与该突出部共形。
3.如权利要求1所述的半导体结构，其中该传导层电连接该接垫。
4.如权利要求1所述的半导体结构，其中该第一保护层与该突出部一体成形。
5.如权利要求1所述的半导体结构，其中该第一保护层包含弹性体、环氧化合物、或聚酰亚胺。
6.如权利要求1所述的半导体结构，其中该第二保护层包含一开口，该开口暴露位于该接垫上方的该传导层。
7.如权利要求1所述的半导体结构，其中该第一保护层包含一第一介电层与一第二介电层，该第一介电层位于该基板上方并且局部覆盖该接垫，该第二介电层位于该第一介电层上方、局部覆盖该接垫并且包含自该第二介电层突出且远离该第一介电层的该突出部。
8.如权利要求1所述的半导体结构，还包括一传导凸块，该传导凸块覆盖自该第二保护层暴露的该传导层。
9.如权利要求8所述的半导体结构，其中该传导凸块经由该传导层而电连接至该接垫。
10.如权利要求8所述的半导体结构，其中该传导凸块环绕该突出部，或该突出部突出至该传导凸块中。
11.一种半导体结构的制造方法，包括：
提供一载体，该载体包含一凹部；
配置一第一保护层于该载体上方，并且填充该凹部；
提供一基板，其中一接垫位于该基板上方；
接合该第一保护层与该基板，以将该接垫插入于该第一保护层中；
移除该载体；
移除该第一保护层的一部分，以暴露该接垫的一暴露部分；
配置一传导层于该第一保护层与该接垫的该暴露部分上方；
配置一第二保护层于该传导层上方，
其中该第一保护层包含一突出部，该突出部自该第一保护层突出且远离该基板，并且位于该突出部上方的该传导层自该第二保护层暴露。
12.如权利要求11所述的制造方法，还包括：
在配置该第一保护层之前，配置一释出膜于该载体与该凹部上方；或
在接合该基板与该第一保护层之后，硬化该第一保护层；或
在移除该载体之前，翻转与该第一保护层接合的该基板；或
配置一传导凸块于自该第二保护层暴露的该传导层上方。
13.如权利要求11所述的制造方法，其中配置该第一保护层包含进行旋涂工艺。
14.如权利要求11所述的制造方法，其中配置一传导层包含进行镀工艺、电镀、或无电镀工艺。
15.如权利要求11所述的制造方法，其中该突出部位于该凹部内。
16.如权利要求11所述的制造方法，其中该第一保护层包含一第一介电层与一第二介电层，该第一介电层位于该基板上方并且覆盖该接垫，该第二介电层位于该载体上方并且填充该凹部，该第一介电层与该第二介电层接合，该制造方法包含移除该第一介电层的一部分与该第二介电层的一部分以暴露该接垫的该暴露部分。
17.如权利要求11所述的制造方法，其中该第一保护层包含一第一介电层与一第二介电层，该第一介电层位于该基板上方、覆盖该接垫并且包含自该第一介电层突出且远离该基板的该突出部，该第二介电层经配置与该第一介电层及该突出部共形，以及移除该第一介电层的一部分与该第二介电层的一部分以暴露该接垫的该暴露部分。
18.一种半导体结构的制造方法，包括：
提供一载体，该载体包含一凹部；
配置一第二保护层于该载体上方；
配置一传导层于该第二保护层与该凹部上方；
配置一第一保护层于该传导层与该第二保护层上方；
提供一基板，其中一接垫位于该基板上方；
接合该基板与该第一保护层，以将该接垫插至该第一保护层中；
配置该接垫于该传导层上方；
移除该载体；以及
移除该第二保护层的一部分，以暴露该传导层的一暴露部分；
其中该第一保护层包含自该第一保护层突出且远离该基板的一突出部，并且自该第二保护层暴露的该传导层的该暴露部分位于该突出部上方。
19.如权利要求18所述的制造方法，其中该第二保护层经配置与该凹部的一侧壁共形，或该传导层经配置与该第二保护层共形。
20.如权利要求18所述的制造方法，还包括：
在配置该第二保护层之前，配置一释放膜于该载体与该凹部上方；或
在接合该基板与该第一保护层之后，硬化该第一保护层；或
在移除该载体之前，翻转与该第一保护层接合的该基板；或
配置一传导凸块于自该第二保护层暴露的该传导层的该暴露部分上方。
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US10431559B2 (en) 2019-10-01
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