CN107731911B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN107731911B
CN107731911B CN201710519874.1A CN201710519874A CN107731911B CN 107731911 B CN107731911 B CN 107731911B CN 201710519874 A CN201710519874 A CN 201710519874A CN 107731911 B CN107731911 B CN 107731911B
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current detection
semiconductor substrate
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CN107731911A (zh
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西村武义
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

在SJ结构的半导体装置中，将本体区域和电流检测区域进行分离并抑制耐压下降。本发明提供一种半导体装置，该半导体装置具备：半导体基板；包括形成在半导体基板的内部的1个以上的工作用单元的本体区域；包括形成在半导体基板的内部的1个以上的电流检测用单元的电流检测区域；以及在半导体基板的内部设置在本体区域和电流检测区域之间，包括耐压结构部的中间区域，在本体区域、电流检测区域和中间区域中，使第1导电型的管柱和第2导电型的管柱以等间隔交替地配置。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
以往，在IGBT(Insulated Gate Bipolar Transistor)等半导体装置中，已知具有作为元件进行驱动的本体区域和用于检测电流的电流检测区域的结构(例如，参照专利文献1)。
专利文献1：日本特开2010-219258号公报
发明内容
技术问题
存在将电流检测区域由场板等耐压结构包围的情况。在具有耐压结构的装置中，若在本体区域和电流检测区域形成超结结构，则存在超结结构的p型和n型的杂质的电荷平衡被破坏而使耐压下降的情况。
技术方案
本发明的一个方面，提供具备半导体基板的半导体装置。半导体装置可以具备包括形成在半导体基板的内部的1个以上的工作用单元的本体区域。半导体装置可以具备包括形成在半导体基板的内部的1个以上的电流检测用单元的电流检测区域。半导体装置可以具备在半导体基板的内部设置在本体区域和电流检测区域之间，并且包括耐压结构部的中间区域。在本体区域、电流检测区域和中间区域中，第1导电型的管柱和第2导电型的管柱可以以等间隔交替配置。
中间区域可以具有形成在半导体基板的上方的场板。中间区域可以在与本体区域相邻的区域和与电流检测区域相邻的区域形成有二极管部。
在半导体基板的内部可以形成有第1导电型的基区和在基区的下方形成的第2导电型的漂移区。本体区域和电流检测区域可以具有多个沟槽部，所述多个沟槽部形成为从所述半导体基板的上表面起延伸到所述基区的下侧，并且以相同的间隔配置。本体区域和电流检测区域可以具有形成在各沟槽部之间的区域中的基区的上方的第2导电型的高浓度区域。在中间区域可以不形成高浓度区域。
与本体区域相邻的二极管部和与电流检测区域相邻的二极管部具有共同的基区。与本体区域相邻的二极管部和与电流检测区域相邻的二极管部可以具有分离的基区。中间区域还可以在与本体区域相邻的二极管部的基区和与电流检测区域相邻的二极管部的基区之间具有分离的基区。
半导体装置可以具备在本体区域的至少一部分区域的上方形成的上表面侧电极。半导体装置可以具备在电流检测区域的至少一部分区域的上方形成的电流检测用电极。与本体区域相邻的二极管部可以与上表面侧电极连接。与电流检测区域相邻的二极管部可以与电流检测用电极连接连接。第1导电型的管柱和第2导电型的管柱在本体区域、电流检测区域和中间区域的杂质浓度可以相同。
上述发明内容并未列举出本发明的全部特征。这些特征组的亚组合(subcombination)也可以构成本发明。
附图说明
图1是本发明的实施方式的半导体装置100的上表面的示意图。
图2是表示图1中的A-A'截面的一例的图。
图3是表示图1中的A-A'截面的其它例的图。
图4是表示图1中的A-A'截面的其它例的图。
图5是将图1中的电流检测用电极12的角部附近的B部放大的示意图。
图6是将图1中的电流检测用电极12的角部附近的B部放大的示意图。
符号说明
11：源极，12：电流检测用电极，13：栅极，14：漏极，21：本体区域，22：电流检测区域，23：耐压结构区域，24：中间区域，26：层间绝缘膜，30：半导体基板，32：漂移区，33：漏区，34：基区，36：p+区域，38：源区，40：沟槽部，42：栅极绝缘膜，44：电极部，52：工作用单元，54：电流检测用单元，58：二极管部，60：管柱，62：管柱，70：绝缘膜，72：场板，74：层间绝缘膜，100：半导体装置。
具体实施方式
以下，根据本发明的实施方式对本发明进行说明，以下实施方式并不限定本发明的保护范围。另外，在实施方式中说明的特征的全部组合对于发明的解決方案不是必须的。
在本说明书中，将与半导体基板的深度方向平行的方向的一侧称为“上”，另一侧称为“下”。在基板、层或者其它部件的2个主面中，将一面称为上表面，另一面称为下表面。“上”、“下”的方向不限于重力方向。
在本说明书中，虽然使用了“源极”、“漏极”的用语，但半导体装置不限于MOSFET。IGBT等双极晶体管中的“发射极”和“集电极”也可以包括在本说明书中的“源极”和“漏极”的用语的范围内。
在各实施例中，以将第1导电型设为p型、将第2导电型设为n型为例进行了说明，但基板、层、区域等的导电型也可以为分别相反的极性。
图1是本发明的实施方式的半导体装置100的上表面的示意图。半导体装置100具备半导体基板30。半导体基板30可以是硅基板，也可以是氮化物半导体或碳化硅等化合物半导体基板。在半导体基板30的上表面的上方形成有源极11和电流检测用电极12。源极11是上表面侧电极的一例。在半导体基板30的上表面的上方还可以形成有栅极13。
作为一例，源极11、电流检测用电极12和栅极13由铝、铝合金、铜、铜合金等金属材料形成。源极11、电流检测用电极12和栅极13彼此分离地设置。本例的半导体装置100是主电流沿半导体基板30的深度方向流动的纵型装置。在本例的半导体基板30的下表面形成有漏极。
在半导体基板30的内部形成有本体区域21、电流检测区域22和中间区域24。本体区域21是半导体装置100的主电流流动的区域。在本体区域21流动的主电流经由源极11流向外部。源极11形成在本体区域21的至少一部分区域的上方。
电流检测区域22是被检测电流流动的区域。被检测电流经由电流检测用电极12流向外部的电流检测装置。电流检测用电极12形成在电流检测区域22的至少一部分区域的上方。在半导体基板30的上表面，电流检测用电极12所覆盖的面积小于源极11所覆盖的面积。
电流检测装置检测被检测电流的电流值。电流检测装置可以基于检测到的电流值控制半导体装置100。例如，在检测到的电流值超过规定的阈值的情况下，电流检测装置将半导体装置100控制为关断状态。
中间区域24设置在本体区域21和电流检测区域22之间，使本体区域21和电流检测区域22分离。在中间区域24中设置有场板等耐压结构。
沿半导体基板30的外周可以形成有耐压结构区域23。耐压结构区域23形成在本体区域21、电流检测区域22和中间区域24的外侧。在耐压结构区域23中形成有保护环或场板等耐压结构。中间区域24可以具有与耐压结构区域23相同的结构。
图2是表示图1中的A-A'截面的一例的图。图2所示的各构成可以形成为沿与图2的纸面垂直的方向延伸。在图2中，作为一例，在半导体装置100的下表面侧形成有掺杂了n型杂质的n+型的漏区33和漏极14。
在本体区域21中形成有主电流流动的1个以上的工作用单元52。在电流检测区域22中形成有被检测电流流动的1个以上的电流检测用单元54。本例的工作用单元52和电流检测用单元54作为对是否使电流向半导体基板30的深度方向流动进行切换的晶体管而发挥功能。工作用单元52和电流检测用单元54优选为具有相同的结构和相同的杂质浓度。
在半导体基板30的上表面，电流检测区域22所占的面积小于本体区域21所占面积。电流检测区域22所占的面积可以是本体区域21所占面积的10分之1以下，也可以是100分之1以下。
中间区域24在本体区域21和电流检测区域22之间形成在半导体基板30的内部。中间区域24以包围电流检测区域22的方式具有场板72等。
在中间区域24中的半导体基板30的内部未形成沟槽部40、工作用单元52和电流检测用单元54。在本例中，在中间区域24中未形成作为晶体管工作的区域。在本例的中间区域24中，至少在与本体区域21相邻的区域和与电流检测区域22相邻的区域形成有二极管部58。
与本体区域21相邻的二极管部58与源极11电连接。与电流检测区域22相邻的二极管部58与电流检测用电极12电连接。另外，各二极管部58具有共同的基区34。
在本例的半导体基板30中，在本体区域21、电流检测区域22和中间区域24，从下表面侧起依次形成有n+型的漏区33和n-型的漂移区32。另外，在漂移区32的表面层形成有p型的基区34。另外，在本体区域21和电流检测区域22中形成有沟槽部40，该沟槽部40贯穿基区34，并且从半导体基板30的上表面起延伸到基区34的下侧为止并达到漂移区32。
被夹在各沟槽部40之间的台面区域作为工作用单元52和电流检测用单元54中的任意一个发挥功能。在本例中，将沟槽部40的短边方向的宽度的中心作为各单元的交界。在本例的工作用单元52和电流检测用单元54中，在基区34的上方形成有n+型的源区38。在源区38中掺杂有比漂移区32的杂质的浓度高的杂质。源区38是高浓度区域的一例。由此，工作用单元52和电流检测用单元54作为晶体管发挥功能。在本例中，在作为晶体管发挥功能的单元中，将形成在源极11的下方的单元作为工作用单元52，将形成在电流检测用电极12的下方的单元作为电流检测用单元54。
与此相对地，在中间区域24中，在基区34的上方不形成源区38。中间区域24中的基区34作为与漂移区32(n型的管柱62)的pn结二极管发挥作用。利用中间区域24，使本体区域21和电流检测区域22分离，能够高精度地检测被检测电流。
另外，在工作用单元52和电流检测用单元54中，可以在露出到半导体基板30的上表面的区域形成p+型的p+区域36。在p+区域36中掺杂有比基区34的杂质浓度高的杂质。由此，降低各单元和源极11等电极之间的接触电阻。另外，中间区域24中的基区34具有位于源极11的下方的区域和位于电流检测用电极12的下方的区域。在基区34的、位于各电极的下方的区域中可以形成p+区域36。由此，能够降低基区34和源极11等之间的接触电阻，并且抑制晶体管单元内的寄生双极晶体管的工作。
场板72形成在中间区域24的基区34的上方。场板72由添加有例如杂质的多晶硅形成。在场板72和半导体基板30的上表面之间形成有厚度比栅极绝缘膜42厚的绝缘膜70。另外，进一步形成有覆盖场板72的层间绝缘膜74。
场板72可以被赋予与源极11或栅极(电极部44)相同的电位。通过将场板72等耐压结构以包围电流检测区域22的方式设置在中间区域24，能够缓解中间区域24附近的电场集中。
本例的沟槽部40具有：从半导体基板30的上表面起到达漂移区32为止的沟槽；形成在沟槽的内壁上的栅极绝缘膜42；设置在沟槽内并由栅极绝缘膜42覆盖的电极部44。
作为一例，栅极绝缘膜42是将露出到沟槽的内壁的半导体基板30热氧化而成的氧化膜。作为一例，电极部44由掺杂了杂质的多晶硅等形成。本例的电极部44与图1所示的栅极13电连接。根据施加到电极部44上的栅极电压，在与电极部44对置的基区34形成沟道。由此，在工作用单元52和电流检测用单元54中的源区38与漂移区32之间有电流流动。另外，电极部44和场板72可以同时形成。
在半导体装置100包括IGBT的情况下，一部分电极部44可以与源极11(IGBT中的发射极)电连接。与源极11连接的沟槽部40作为虚设沟槽发挥作用。由此，能够产生载流子的注入促进效果(IE效果)并降低导通电压。
各沟槽部40在该截面的工作用单元52和电流检测用单元54中以相同的间隔配置。多个沟槽部40可以以沿与该截面垂直的方向呈条纹状地延伸的方式形成。
在半导体基板30的上表面形成有栅极绝缘膜42的一部分。其中，各单元中的p+区域36和源区38至少部分地未被栅极绝缘膜42覆盖。
在半导体基板30的上表面和栅极绝缘膜42的上表面形成有层间绝缘膜26。其中，以使各单元中的p+区域36和源区38露出的方式，在层间绝缘膜26形成有开口。在这些开口内填充有源极11或电流检测用电极12。
在本体区域21、电流检测区域22和中间区域24的漂移区32中以等间隔交替配置有p型的管柱60和n型的管柱62。管柱60和管柱62以能够形成超结的方式调节杂质浓度和宽度。通过这样的结构，由于耗尽层从管柱60和管柱62的交界起沿横向扩展，即使提高n型区域的杂质浓度并使导通电阻下降，也能够维持高耐压。
在本例中，管柱60形成为从各区域的基区34的下表面起向下侧突出。管柱60之间的漂移区32作为管柱62发挥功能。各管柱60的间隔与各单元的间隔相同。管柱60分别相对于各工作用单元52和各电流检测用单元54而形成。另外，在中间区域24中的基区34的下侧也以与本体区域21和电流检测区域22相同的间隔形成有管柱60。在中间区域24中，可以从1个基区34的下表面延伸出多个管柱60。
在半导体装置100中，在本体区域21、电流检测区域22和中间区域24以相同的间隔配置有管柱60和管柱62。因此，在本体区域21、电流检测区域22和中间区域24能够形成相同结构的超结。本体区域21、电流检测区域22和中间区域24中的超结的各管柱的杂质浓度相同。
利用这样的结构，设置将本体区域21和电流检测区域22分离的中间区域24并且能够以均匀的间隔配置超结的管柱60和管柱62。因此，容易保持超结中的p型和n型的杂质的电荷平衡，并能够维持耐压。
图3是表示图1中的A-A'截面的其它例的图。在本例中，在中间区域24形成有彼此分离的多个基区34。其它结构与图2所示的例子相同。
与本例的中间区域24的源极11和电流检测用电极12连接的各二极管部58具有彼此分离的基区34。在各二极管部58的基区34中形成有p+区域36。各基区34的至少一部分可以形成在场板72的下方以外的区域。
另外，在各二极管部58的基区34之间可以形成有进一步分离的基区34。各基区34也可以通过离子注入和热处理来形成。
中间区域24中的基区34以与管柱60相同的间隔配置。另外，在中间区域24中，在不与源极11和电流检测用电极12中的任意一个连接的基区34中不形成p+区域36。未形成有p+区域36的基区34可以配置在场板72的下方。
即使通过这样的结构，也能够设置将本体区域21和电流检测区域22分离的中间区域24，并且将超结的管柱60和管柱62以均等的间隔进行配置。因此，容易保持超结中的p型和n型的杂质的电荷平衡，能够维持耐压。
图4是表示图1中的A-A'截面的其它例的图。在本例中，连接有图3所示的中间区域24的各基区34。在本例的基区34的下表面通过离子注入和扩散形成有凹凸。其中，中间区域24的基区34的向下侧突出的部分以与管柱60相同的间隔进行配置。
即使通过这样的结构，也能够设置将本体区域21和电流检测区域22分离的中间区域24，并且将超结的管柱60和管柱62以均等的间隔进行配置。因此，容易保持超结中的p型和n型的杂质的电荷平衡，能够维持耐压。
图5是将图1所示的半导体装置100的上表面中的、电流检测用电极12的角部附近的B部进行放大的示意图。图5与图2所示的结构对应。图5表示沟槽部40、电极部44、基区34、源区38、p+区域36、场板72、源极11和电流检测用电极12，并省略其它结构。
多个沟槽部40在本体区域21和电流检测区域22中沿规定的排列方向以一定的间隔配置。本例的沟槽部40不形成在中间区域24。各沟槽部40设置为沿规定的延伸方向延伸。
在各沟槽部40之间的台面区域形成有基区34。其中，在本体区域21和电流检测区域22中，在半导体基板30的上表面，沿延伸方向条纹状地延伸形成有源区38和p+区域36。也可以取而代之地使源区38和p+区域36沿延伸方向交替形成。
中间区域24在延伸方向和排列方向这两个方向设置在本体区域21和电流检测区域22之间。在中间区域24中的半导体基板30的上表面附近形成有基区34，在半导体基板30的上表面的上方形成有场板72。在排列方向上的、中间区域24与其它区域的交界附近可以沿延伸方向形成有p+区域36。
另外，在中间区域24中未形成源区38。由此，在延伸方向上存在本体区域21、电流检测区域22和中间区域24的台面区域中，将本体区域21和电流检测区域22的源区38进行分离。在存在本体区域21、电流检测区域22和中间区域24的台面区域中，形成在电流检测用电极12的下侧的中间区域24的长度L1可以大于形成在源极11的下侧的中间区域24的长度L2。由此，能够减小形成在源极11的下侧的中间区域24的面积。
图6是将半导体装置100的上表面的、电流检测用电极12的角部附近的B部进行放大的示意图。在图6的例子中，将场板72与经由栅极绝缘膜42埋入到工作用单元52和电流检测用单元54的沟槽部40的电极部44同时形成。另外，场板72与经由栅极绝缘膜42埋入到工作用单元52和电流检测用单元54的沟槽部40的电极部44在与沟槽部40的长度方向(图中的延伸方向)平行的方向上连接。其它的结构与图5相同，可以获得与图5的例子相同的效果。
以上，使用实施方式对本发明进行了说明，本发明的保护范围不限于上述实施方式。本领域技术人员可以对上述实施方式进行各种变更或改良。从权利要求书的记载可知，进行了这些变更或改良的实施方式也可以包括在本发明的保护范围内。
另外，本发明的实施方式，虽然记载了具有形成在沟槽的内壁的栅极绝缘膜42和设置在沟槽部40内并被栅极绝缘膜42覆盖的电极部44的沟槽栅极结构，但是也可以是具备在半导体基板的表面层选择性地配置的基区和选择性地配置在基区内的源区，在半导体基板的表面配置栅极绝缘膜并在栅极绝缘膜上具备电极部的平面栅极结构。
另外，基区34和沟槽部40如图5、图6所示将平面形状设为条纹状，但也可以将基区34的平面形状设为岛状，将沟槽部40的平面形状设为配置在基区34的岛状之间的格子状并将电极部44设为格子状。在上述的平面栅极结构中同样地也可以将基区的平面形状设置为岛状，将电极部的平面形状设置为以跨越基区的岛状之间的方式配置的格子状。另外，在将基区形成为岛状的情况下，p型的管柱的平面形状也配置为岛状。

Claims (7)

1.一种半导体装置，其特征在于，具备：
半导体基板；
本体区域，其包括形成在所述半导体基板的内部的1个以上的工作用单元；
电流检测区域，其包括形成在所述半导体基板的内部的1个以上的电流检测用单元；以及
中间区域，其在所述半导体基板的内部设置在所述本体区域和所述电流检测区域之间，并且包括耐压结构部，
在所述半导体基板的内部形成有：
第1导电型的基区；以及
形成在所述基区的下方的第2导电型的漂移区，
在所述本体区域、所述电流检测区域和所述中间区域，第1导电型的管柱和第2导电型的管柱以等间隔交替配置，
在所述中间区域，所述第2导电型的管柱从所述基区的下表面起向下方延伸出，
所述中间区域在与所述本体区域相邻的区域和与所述电流检测区域相邻的区域通过所述基区和所述第2导电型的管柱形成二极管部。
2.根据权利要求1所述的半导体装置，其特征在于，
在所述中间区域，所述第1导电型的管柱从与所述第2导电型的管柱共同的所述基区的下表面起向下方延伸出。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述中间区域具有形成在所述半导体基板的上方的场板。
4.根据权利要求1或2所述的半导体装置，其特征在于，
所述本体区域和所述电流检测区域具有：
多个沟槽部，所述多个沟槽部形成为从所述半导体基板的上表面起延伸到所述基区的下侧，并且以相同的间隔配置；以及
第2导电型的高浓度区域，其形成在各沟槽部之间的区域中的所述基区的上方，
在所述中间区域未形成所述高浓度区域。
5.根据权利要求1或2所述的半导体装置，其特征在于，与所述本体区域相邻的所述二极管部和与所述电流检测区域相邻的所述二极管部具有共同的所述基区。
6.根据权利要求1或2所述的半导体装置，其特征在于，还具备：
上表面侧电极，其形成在所述本体区域的至少一部分的区域的上方；以及
电流检测用电极，其形成在所述电流检测区域的至少一部分的区域的上方，
与所述本体区域相邻的所述二极管部与所述上表面侧电极连接，
与所述电流检测区域相邻的所述二极管部与所述电流检测用电极连接。
7.根据权利要求1或2所述的半导体装置，其特征在于，在所述本体区域、所述电流检测区域和所述中间区域中，所述第1导电型的管柱和所述第2导电型的管柱的杂质浓度相同。
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