CN107644871B - 固态驱动器封装 - Google Patents

固态驱动器封装 Download PDF

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Publication number
CN107644871B
CN107644871B CN201710601042.4A CN201710601042A CN107644871B CN 107644871 B CN107644871 B CN 107644871B CN 201710601042 A CN201710601042 A CN 201710601042A CN 107644871 B CN107644871 B CN 107644871B
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layer
chip
substrate
connection
package
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CN107644871A (zh
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李光烈
金宝星
南泰德
李旺周
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020160129206A external-priority patent/KR102616664B1/ko
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Abstract

提供了一种固态驱动器封装。该固态驱动器封装可以包括集成电路基板和提供在集成电路基板上的多个第三芯片，集成电路基板包括：下再分布层；提供在下再分布层上的第一芯片和第二芯片；以及提供在下再分布层上的连接基板，连接基板被提供在第一芯片和第二芯片的外周上。所述多个第三芯片经由连接基板和下再分布层电连接到第一芯片和第二芯片。

Description

固态驱动器封装
技术领域
与示例实施方式一致的装置涉及半导体器件，具体地，涉及具有减小的尺寸的固态驱动器封装。
背景技术
随着以信息为导向的社会的到来，用于个人用途而被存储或发送的数据的量正指数地增加。由于对这样的信息存储介质的需求的增加，各种各样的个人外部存储设备正在被开发。外部存储设备被提供成单个存储设备的形式并被连接到主机设备。根据来自主机设备的命令，数据从外部存储设备被读取或者被写入到外部存储设备。
近来，硬盘驱动器(HDD)正以具有非易失性半导体芯片的存储设备(例如固态驱动器(SSD))被替代。固态驱动器的尺寸正在减小。此外，有必要减少开发固态驱动器所需的时间和成本。
发明内容
本发明构思的示例实施方式提供了具有减小的尺寸的固态驱动器封装。
根据本发明构思的一示例实施方式的一方面，一种固态驱动器(SSD)封装可以包括集成电路基板和提供在集成电路基板上的多个第一存储器芯片。集成电路基板可以包括下再分布层、提供在下再分布层上的控制器芯片和第二存储器芯片、以及围绕控制器芯片和第二存储器芯片被提供并连接到下再分布层的连接基板。第一存储器芯片可以经由连接基板和下再分布层电连接到控制器芯片和第二存储器芯片。
根据本发明构思的一示例实施方式的一方面，一种固态驱动器(SSD)封装可以包括集成电路基板和提供在集成电路基板上的多个第一存储器芯片。集成电路基板可以包括：具有空腔的连接基板，提供在连接基板的空腔中的控制器芯片和第二存储器芯片，覆盖连接基板、控制器芯片和第二存储器芯片的底表面的下再分布层，以及覆盖连接基板、控制器芯片和第二存储器芯片的顶表面的上再分布层。第一存储器芯片可以经由上再分布层和下再分布层以及连接基板电连接到控制器芯片和第二存储器芯片。
根据本发明构思的一示例实施方式的一方面，一种固态驱动器(SSD)封装可以包括集成电路基板和提供在集成电路基板上的多个第三芯片，集成电路基板包括：下再分布层；第一芯片和第二芯片，第一芯片和第二芯片被提供在下再分布层上；以及提供在下再分布层上的连接基板，连接基板被提供在第一芯片的外周和第二芯片的外周上。所述多个第三芯片经由连接基板和下再分布层电连接到第一芯片和第二芯片。
根据本发明构思的一示例实施方式的一方面，一种固态驱动器(SSD)封装可以包括集成电路基板和提供在集成电路基板上的多个第三芯片，集成电路基板包括：具有空腔的连接基板；第一芯片和第二芯片，第一芯片和第二芯片被提供在连接基板的空腔中；下再分布层，其覆盖连接基板的第一表面、第一芯片的第一表面和第二芯片的第一表面；以及上再分布层，其覆盖连接基板的与连接基板的第一表面相反的第二表面、第一芯片的与第一芯片的第一表面相反的第二表面以及第二芯片的与第二芯片的第一表面相反的第二表面。所述多个第三芯片经由上再分布层和下再分布层以及连接基板电连接到第一芯片和第二芯片。
根据本发明构思的一示例实施方式的一方面，一种固态驱动器(SSD)封装可以包括集成电路基板、上封装和连接层，集成电路基板包括：第一再分布层；提供在第一再分布层上的第一芯片和第二芯片；以及提供在第一再分布层上的连接基板，连接基板被提供在第一芯片的外周和第二芯片的外周上，上封装被提供在集成电路基板上并包括：封装基板；以及堆叠在封装基板上的多个第三芯片，连接层被提供在集成电路基板与上封装之间。连接层可以包括第二再分布层和连接端子层中的至少一个。所述多个第三芯片经由连接层、连接基板和第一再分布层电连接到第一芯片。
附图说明
示例实施方式将由以下结合附图的简要描述被更清楚地理解。附图展示了如在此描述的非限制性的示例实施方式。
图1是示意性地示出根据本发明构思的一示例实施方式的固态驱动器封装的框图。
图2至12是示出根据本发明构思的示例实施方式的固态驱动器封装的剖视图。
图13是根据本发明构思的一示例实施方式的固态驱动器封装的透视图。
图14A和14B以及图15至21是示出根据本发明构思的示例实施方式的制造固态驱动器封装的方法的剖视图。
应注意，以上附图旨在示出某些示例实施方式中所利用的方法、结构和/或材料的一般特征，并且旨在补充下面提供的书面描述。然而，这些附图将不按比例缩放，并且可能不精确地反映任何给出的实施方式的精确的结构特征或性能特征，并且不应被解释为限定或限制由示例实施方式所涵盖的值或特性的范围。例如，为了清楚，分子、层、区域和/或结构元件的相对厚度和布置可以被减小或夸大。相似或相同的附图标记在各种附图中的使用旨在指明相似或相同的元件或特征的存在。
具体实施方式
在下文中，将参照图1至13描述根据本发明构思的示例实施方式的固态驱动器封装。
图1是示意性地示出根据本发明构思的一示例实施方式的固态驱动器(SDD)封装的框图。
参照图1，固态驱动器(SSD)封装1000可以被配置为响应于来自主机H(例如外部电子设备)的读取/写入请求而存储或读取数据。SSD封装1000可以包括SSD控制器1、输入/输出接口2、多个非易失性存储器件(NVM)3和缓冲存储器件4。
SSD控制器1可以通过输入/输出接口2与主机H交换信号。这里，SSD控制器1与主机H之间将要交换的信号可以包括命令、地址和数据。SSD控制器1可以响应于来自主机H的命令而从非易失性存储器件3中的至少一个读取数据或将数据写入到非易失性存储器件3中的至少一个。
输入/输出接口2可以被配置为在主机H与SSD封装1000之间提供物理连接。就是说，输入/输出接口2可以被配置为允许固态驱动器封装1000对应于主机H的总线格式地与主机H相连接。主机H的总线格式可以包括通用串行总线(USB)、PCI快速、串行高级技术附件(SATA)、并行ATA(PATA)等。
非易失性存储器件3可以是具有大容量和高存储速度特性的NAND型闪速存储器件。在某些示例实施方式中，非易失性存储器件3可以是相变随机存取存储器(PRAM)、磁性RAM(MRAM)、电阻式RAM(ReRAM)、铁磁RAM(FRAM)或NOR闪速存储器件。
缓冲存储器件4可以用于临时存储将在SSD控制器1与非易失性存储器件3之间传输的数据，以及用于临时存储将在SSD控制器1与主机H之间传输的数据。此外，缓冲存储器件4可以用来操作用于有效地管理非易失性存储器件3的软件(S/W)。缓冲存储器件4可以包括随机存取存储器(例如DRAM或SRAM)。或者，缓冲存储器件4可以包括非易失性存储器(例如闪速存储器、PRAM、MRAM、ReRAM和FRAM)。
图2至12是示出根据本发明构思的示例实施方式的固态驱动器封装1000的剖视图。图13是根据本发明构思的一示例实施方式的SSD封装1000的透视图。
参照图2和13，SSD封装1000可以包括集成电路基板100和安装在集成电路基板100上的上封装200。
在示例实施方式中，集成电路基板100可以包括连接基板110、缓冲存储器芯片10、控制器芯片20、下再分布层120和下模制层130。
详细地，连接基板110可以包括多个绝缘层111、多个互连图案113、多个导电通路115、以及多个下焊盘117a和多个上焊盘117b。作为一示例，连接基板110可以是印刷电路板(PCB)。然而，示例实施方式不限于此。下焊盘117a和上焊盘117b可以分别设置在连接基板110的底表面和顶表面上，互连图案113可以插置在绝缘层111之间并且可以联接到导电通路115。下焊盘117a和上焊盘117b可以通过导电通路115和互连图案113彼此电连接。在示例实施方式中，连接基板110可以具有放置在集成电路基板100的中央区域处的空腔110c。就是说，连接基板110可以围绕缓冲存储器芯片10和控制器芯片20被提供。例如，连接基板110的导电通路115可以被提供在缓冲存储器芯片10的一侧以及控制器芯片20的一侧。
缓冲存储器芯片10和控制器芯片20可以被提供在连接基板110的空腔110c中。在一示例中，缓冲存储器芯片10和控制器芯片20可以在连接基板110的空腔110c中被提供为彼此间隔开。然而，示例实施方式不限于此。
在一些示例实施方式中，缓冲存储器芯片10和控制器芯片20可以包括分别提供在其底表面上的芯片焊盘11和21。缓冲存储器芯片10和控制器芯片20可以具有基本上等于或者小于连接基板110的厚度的厚度。作为示例，缓冲存储器芯片10和控制器芯片20可以具有放置在与连接基板110的顶表面基本上相同的水平处、或者如图3中所示地放置在比连接基板110的顶表面更低的水平处的顶表面。在某些示例实施方式中，如图4中所示，缓冲存储器芯片10和控制器芯片20的顶表面可以被放置在比连接基板110的顶表面更高的水平处。
缓冲存储器芯片10可以是或者包括易失性存储器芯片(例如动态随机存取存储器(DRAM)芯片)。在某些示例实施方式中，缓冲存储器芯片10可以是或者包括PRAM芯片、ReRAM芯片、FRAM芯片或MRAM芯片。
在一些示例实施方式中，控制器芯片20可以包括中央处理单元(CPU)、内部存储器、缓冲存储器控制单元、主机接口和FLASH接口。
控制器芯片20可以包括用于经由SATA、PATA或小型计算机系统接口(SCSI)标准与外部设备交换信号的程序。这里，SATA标准可以包括含SATA-1、SATA-2、SATA-3和外部SATA(e-SATA)的所有基于SATA的标准。PATA标准可以包括含电子集成驱动器(IDE)和增强IDE(E-IDE)的所有基于IDE的标准。
下再分布层120可以被提供在缓冲存储器芯片10、控制器芯片20和连接基板110的底表面上。下再分布层120可以电连接到缓冲存储器芯片10、控制器芯片20和连接基板110。
在一些示例实施方式中，连接基板110可以具有第一厚度T1，下再分布层120可以具有比第一厚度T1更小的第二厚度T2。在一示例中，下再分布层120的第二厚度T2可以小于缓冲存储器芯片10或控制器芯片20的厚度。
详细地，下再分布层120可以包括多个下绝缘层121、多个下再分布图案123、多个下再分布通路125和多个外连接焊盘127。
下再分布图案123可以被提供在下绝缘层121之间，下再分布通路125可以被提供为电连接不同水平处的下再分布图案123。若干下再分布通路125可以穿过下绝缘层121电连接到分别提供在缓冲存储器芯片10和控制器芯片20中的芯片焊盘11和21、以及电连接到下再分布图案123。下再分布图案123可以包括用于施加电信号的信号线以及用于施加接地电压或电源电压的电源线。
外连接焊盘127可以被提供在下绝缘层121上，下保护层129可以被提供在下绝缘层121上以暴露外连接焊盘127。下保护层129可以由不同于下绝缘层121的绝缘材料形成。例如，下保护层129可以由与下模制层130相同的材料形成。外连接端子150(例如焊料球或焊料凸块)可以被附接到外连接焊盘127。例如，外连接端子150可以是提供在下再分布层120的底表面上的球栅阵列(BGA)。外连接端子150可以经由下再分布层120电连接到连接基板110、缓冲存储器芯片10和控制器芯片20。因此，SSD封装1000可以通过BGA直接连接到外部电子设备。外连接焊盘127可以包括用于发送或接收数据信号的数据焊盘、用于发送或接收命令/地址信号的命令/地址焊盘、用于发送或接收接地电压或电源电压的电源焊盘、以及用于测试SSD封装1000的测试焊盘。
在一些示例实施方式中，如作为示例在图13中所示，若干外连接焊盘127可以不被附接到外连接端子150并且可以被暴露于空气。外连接端子150未附接于其的外连接焊盘127可以用作用于电测试SSD封装1000的测试焊盘。
在一些示例实施方式中，下再分布图案123和下再分布通路125可以被配置为将缓冲存储器芯片10电连接到控制器芯片20。此外，下再分布图案123和下再分布通路125可以用于将连接基板110电连接到缓冲存储器芯片10或控制器芯片20。缓冲存储器芯片10和控制器芯片20可以通过下再分布图案123和下再分布通路125电连接到外连接焊盘127。
下模制层130可以被提供为覆盖缓冲存储器芯片10、控制器芯片20和连接基板110的顶表面，并被提供为填充连接基板110的空腔110c。下模制层130可以包括绝缘聚合物(例如环氧模塑料)。
在一示例中，下模制层130可以以下模制层130暴露连接基板110的上焊盘117b的方式被填充到空腔113c中。例如，如图2-6中所示，连接端子250可以被附接到由下模制层130暴露的上焊盘117b。
在一些示例实施方式中，上封装200可以包括封装基板210以及安装在封装基板210上的多个非易失性存储器芯片30、多个无源器件40和上模制层230。
封装基板210可以是或者包括各种类型的基板(例如印刷电路板、柔性基板或胶带基板)。在一些示例实施方式中，封装基板210可以是其中形成内部线IC的印刷电路板。封装基板210可以包括提供在其顶表面上的接合焊盘211以及提供在其底表面上的联接焊盘213。接合焊盘211可以通过内部线IC电连接到联接焊盘213。接合焊盘211可以经由金属线W电连接到非易失性存储器芯片30的输入/输出焊盘31，并且可以通过联接焊盘213附接到连接端子250(例如焊料球或焊料凸块)。
在一些示例实施方式中，第一芯片堆叠ST1和第二芯片堆叠ST2以及无源器件40可以被安装在封装基板210上。
第一芯片堆叠ST1和第二芯片堆叠ST2的每个可以包括以阶梯式结构或阶梯结构堆叠的多个非易失性存储器芯片30。非易失性存储器芯片30可以是例如NAND闪速存储器芯片。
非易失性存储器芯片30的每个可以包括用于输入或输出信号的输入/输出焊盘31。非易失性存储器芯片30可以使用粘合层被堆叠，并且非易失性存储器芯片30的每个可以被堆叠为暴露形成在下面的非易失性存储器芯片中的输入/输出焊盘31。此外，非易失性存储器芯片30的堆叠方向可以被改变至少一次。例如，第一芯片堆叠ST1和第二芯片堆叠ST2的每个可以包括顺序地堆叠并形成在相反方向上倾斜的阶梯式结构的下堆叠30a和上堆叠30b。非易失性存储器芯片30的输入/输出焊盘31可以经由金属线W彼此电连接。
无源器件40可以是电阻器、电容器、电感器、热敏电阻器、振荡器、铁氧体磁珠、天线、变阻器和晶体中的一种。然而，本发明构思不限于此，并且任何其它无源器件可以用作无源器件40。无源器件40可以联接到封装基板210的接合焊盘211，并且可以经由内部线IC、连接基板110和下再分布层120电连接到集成电路基板100的控制器芯片20和缓冲存储器芯片10。
上模制层230可以被提供在封装基板210的顶表面上以覆盖第一芯片堆叠ST1和第二芯片堆叠ST2以及无源器件40。上模制层230可以由环氧模塑料形成或者包括环氧模塑料。
在一些示例实施方式中，上封装200可以经由连接端子250(例如焊料球和焊料凸块)电连接到集成电路基板100。例如，如图2中所示，连接端子250可以在一侧附接到封装基板210的联接焊盘213并且在另一侧附接到集成电路基板100的上焊盘117b。如图2-6中所示，上封装200可以经由连接端子250而被安装在集成电路基板100上，并且间隙G可以形成在上封装200的底表面与集成电路基板100的顶表面之间。
在一些示例实施方式中，上封装200可以经由连接端子250、连接基板110和下再分布层120电连接到缓冲存储器芯片10和控制器芯片20。例如，上封装200中的非易失性存储器芯片30可以由集成电路基板100的控制器芯片20控制，并且可以用于在集成电路基板100的缓冲存储器芯片10中临时存储数据或者从集成电路基板100的缓冲存储器芯片10临时读取数据。此外，无源器件40可以经由连接端子250、连接基板110和下再分布层120电连接到缓冲存储器芯片10和控制器芯片20。
将参照图3至6描述根据本发明构思的一些示例实施方式的固态驱动器(SSD)封装。在对图3至6的以下描述中，为了简洁，参照图2描述的元件可以由相似或相同的附图标记标识，而不重复对其的重叠描述。
参照图3和4，无源器件40可以被嵌入连接基板110中。例如，无源器件40可以电连接到提供在连接基板110中的互连图案113、导电通路115以及下焊盘117a和上焊盘117b。在连接基板110中，无源器件40的位置可以被各种各样地改变。例如，如图4中所示，无源器件40可以被提供在缓冲存储器芯片10与控制器芯片20之间。在一示例中，无源器件40可以直接连接到下再分布层120。
参照图5，提供在上封装200中的非易失性存储器芯片30的数量可以被增加以增大SSD封装1000的存储容量。在这种情况下，上封装200的第一芯片堆叠ST1和第二芯片堆叠ST2的每个可以包括交替地堆叠并形成在相反方向上倾斜的阶梯式结构的多个下堆叠30a和多个上堆叠30b。所述多个下堆叠30a和所述多个上堆叠30b的每个可以经由金属线W联接到提供在封装基板210上的接合焊盘211。
参照图6，上封装200的第一芯片堆叠ST1和第二芯片堆叠ST2的每个可以包括经由穿通通路35彼此电连接的多个非易失性存储器芯片30。例如，非易失性存储器芯片30可以被堆叠在封装基板210上并且可以具有垂直对齐的侧壁，并且非易失性存储器芯片30的每个可以包括联接到输入/输出焊盘的穿通通路35。第一芯片堆叠ST1和第二芯片堆叠ST2可以以倒装芯片安装方式被安装在封装基板210上。
将参照图7描述根据本发明构思的一示例实施方式的固态驱动器封装。在对图7的以下描述中，为了简洁，参照图2描述的元件可以由相似或相同的附图标记标识，而不重复对其的重叠描述。
参照图7和13，SSD封装1000可以包括集成电路基板100以及安装在集成电路基板100上的多个非易失性存储芯片30。
在一些示例实施方式中，集成电路基板100可以包括连接基板110、缓冲存储器芯片10、控制器芯片20、下再分布层120、上再分布层140和下模制层130。
上再分布层140可以被提供在下模制层130上以覆盖缓冲存储器芯片10、控制器芯片20和连接基板110的顶表面。上再分布层140可以电连接到缓冲存储器芯片10、控制器芯片20和连接基板110。
在一些示例实施方式中，上再分布层140可以具有比连接基板110的第一厚度T1更小的第三厚度T3。此外，上再分布层140的第三厚度T3可以小于缓冲存储器芯片10或控制器芯片20的厚度。
例如，上再分布层140可以包括多个上绝缘层141、多个上再分布图案143和多个上再分布通路145。
上绝缘层141可以被提供为覆盖下模制层130，上再分布图案143可以被提供在上绝缘层141之间以及上绝缘层141与下模制层130之间。上再分布通路145可以用于将放置在不同水平处的上再分布图案143彼此电连接。上绝缘层141中的最上一个可以被提供为暴露上再分布图案143中的一些，并且由上绝缘层141暴露的上再分布图案143可以用作输入/输出焊盘。
在一些示例实施方式中，所述多个非易失性存储器芯片30可以被直接安装在上再分布层140上。此外，无源器件40可以被直接安装在上再分布层140上。
例如，第一芯片堆叠ST1和第二芯片堆叠ST2以及无源器件40可以被提供在上绝缘层141中的最上一个上。在第一芯片堆叠ST1和第二芯片堆叠ST2中，非易失性存储器芯片30可以使用粘合层被堆叠在上再分布层140上。
非易失性存储器芯片30的每个可以包括输入/输出焊盘31，并且非易失性存储器芯片30的输入/输出焊盘31可以经由金属线W电连接到上再分布层140的上再分布图案143。换言之，非易失性存储器芯片30可以经由上再分布层140、连接基板110和下再分布层120电连接到缓冲存储器芯片10和/或控制器芯片20。
无源器件40可以经由导电凸块连接到上再分布层140的上再分布图案143。换言之，无源器件40可以经由上再分布层140、连接基板110和下再分布层120电连接到缓冲存储器芯片10和/或控制器芯片20。
上模制层230可以被提供在上再分布层140上以覆盖第一芯片堆叠ST1和第二芯片堆叠ST2以及无源器件40。上模制层230可以由环氧模塑料形成或者包括环氧模塑料，并且可以与上再分布层140的上绝缘层141直接接触。
在一些示例实施方式中，非易失性存储器芯片30可以被直接安装在上再分布层140上，并且可以由上模制层230包封，因而，上模制层230与上再分布层140之间可以不形成间隙。因此，可以减小SSD封装1000的厚度。
在对图8至12的以下描述中，为了简洁，参照图7描述的元件可以由相似或相同的附图标记标识，而不重复对其的重叠描述。
根据图8中所示的一示例实施方式，SSD封装1000可以包括集成电路基板110和其上的多个非易失性存储器芯片30。集成电路基板100可以包括连接基板110、缓冲存储器芯片10、控制器芯片20、下再分布层120、下模制层130和上再分布层140，并且缓冲存储器芯片10和控制器芯片20的每个可以具有比连接基板110的厚度更小的厚度。换言之，缓冲存储器芯片10和控制器芯片20可以具有比连接基板110的顶表面更低的顶表面。
根据图9中所示的一示例实施方式，第一芯片堆叠ST1和第二芯片堆叠ST2可以被提供在集成电路基板100的上再分布层140上，并且第一芯片堆叠ST1和第二芯片堆叠ST2的每个可以包括通过穿通通路35彼此电连接的多个非易失性存储器芯片30。第一芯片堆叠ST1和第二芯片堆叠ST2可以以倒装芯片接合方式被安装在上再分布层140的上再分布图案143上。
根据图10中所示的一示例实施方式，SSD封装1000可以包括集成电路基板100、集成电路基板100上的多个非易失性存储器芯片30和屏蔽层500。
屏蔽层500可以防止外部电子部件遭受可能由SSD封装1000中产生的电磁波引起的电磁干扰(EMI)问题。屏蔽层500可以由其中含有金属和环氧树脂的金属性环氧材料形成或者包括其中含有金属和环氧树脂的金属性环氧材料。屏蔽层500可以由金属材料(例如铜(Cu)、银(Ag)、金(Au)、镍(Ni)、锡(Sn)、锌(Zn)、铬(Cr)、锰(Mn)、铟(In)、钯(Pd)、钛(Ti)、钼(Mo)或铂(Pt))形成或者包括金属材料(例如铜(Cu)、银(Ag)、金(Au)、镍(Ni)、锡(Sn)、锌(Zn)、铬(Cr)、锰(Mn)、铟(In)、钯(Pd)、钛(Ti)、钼(Mo)或铂(Pt))。
在一些示例实施方式中，因为集成电路基板100与上模制层230之间没有间隙，所以屏蔽层500可以从集成电路基板100的侧表面连续地延伸到上模制层230的侧表面。例如，屏蔽层500可以被提供为与上模制层230的顶表面和侧表面以及集成电路基板100的侧表面直接接触。
屏蔽层500可以与提供在集成电路基板100的下再分布层120和上再分布层140中的接地焊盘(未示出)接触。因此，接地电压可以被施加到屏蔽层500。
在一些示例实施方式中，屏蔽层500可以通过使用喷射装置将金属性环氧材料涂覆到上模制层230的顶表面和侧表面以及集成电路基板100的侧表面上而形成。因此，屏蔽层500可以形成为在上模制层230的顶表面和侧表面以及集成电路基板110的侧表面上具有基本上均匀的厚度。在某些示例实施方式中，屏蔽层500可以通过诸如电镀法、无电镀法、溅射法的膜沉积法而形成。在某些示例实施方式中，屏蔽层500可以通过丝网印刷法而形成。
根据图11中所示的一示例实施方式，集成电路基板100的连接基板110可以具有多个空腔110c，并且缓冲存储器芯片10和控制器芯片20可以被提供在空腔110c的每个中。例如，连接基板110可以包括放置在缓冲存储器芯片10与控制器芯片20之间的至少一个部分。
根据图12中所示的一示例实施方式，集成电路基板100可以包括连接基板110、缓冲存储器芯片10、控制器芯片20、无源器件40、下再分布层120、上再分布层140和下模制层130。
在一示例中，无源器件40可以设置在缓冲存储器芯片10与控制器芯片20之间，并且可以通过下再分布层120电连接到缓冲存储器芯片10和/或控制器芯片20。
根据本发明构思的一些示例实施方式，固态驱动器(SSD)封装可以以单个封装的形式被制造，并且可以用于代替个人计算机或笔记本电脑的硬盘驱动器。此外，SSD封装可以被提供成便携式电子设备(例如智能电话、平板个人计算机、数字照相机、MP3播放器或个人数字助理)的一部分。SSD封装可以占据电子设备中小的空间，因而，可以增大电子设备的存储容量。
在下文中，将参照图14A、14B以及15至21描述根据本发明构思的示例实施方式的制造固态驱动器封装的方法。
图14A、14B以及15至21是示出根据本发明构思的示例实施方式的制造固态驱动器(SSD)封装的方法的剖视图。
参照图14A和14B，可以准备具有多个单位区域UR的连接基板面板110P。连接基板面板110P可以被提供为在单位区域UR的每个上具有至少一个空腔110c。在一些示例实施方式中，如图14A中所示，连接基板面板110P可以被提供为在单位区域UR的每个上具有两个空腔110c。在某些示例实施方式中，如图14B中所示，连接基板面板110P可以被提供为在单位区域UR的每个上具有单个空腔110c。
在一示例中，连接基板面板110P可以是具有电路图案的印刷电路板面板。然而，本发明构思的示例实施方式不限于此。连接基板面板110P可以包括多个绝缘层111、绝缘层111之间的互连图案113、以及连接互连图案113的导电通路115，但是可以被构造为具有无芯结构。连接基板面板110P可以包括提供在其底表面和顶表面上的下焊盘117a和上焊盘117b。
具有空腔110c的连接基板面板110P可以被附接到支撑基板300。支撑基板300可以包括粘合层，并且可以由其粘合强度能通过UV光或热而被改变的粘合材料形成。
参照图15，缓冲存储器芯片10和控制器芯片20可以被附接到支撑基板300。缓冲存储器芯片10和控制器芯片20的每个可以被提供在连接基板面板110P的空腔110c中的相应一个中。在其中空腔110c仅形成在单位区域UR的每个中的情况下，缓冲存储器芯片10和控制器芯片20可以被提供在空腔110c中的一个中。缓冲存储器芯片10和控制器芯片20可以具有提供在其底表面上的芯片焊盘11和21，并且可以被附接到支撑基板300。缓冲存储器芯片10和控制器芯片20的芯片焊盘11和21可以面对支撑基板300。
在一些示例实施方式中，缓冲存储器芯片10和控制器芯片20可以具有放置在比连接基板面板110P的顶表面更高或更低的水平处的各自的顶表面。
参照图16，下模制层130可以在支撑基板300上形成。下模制层130可以形成为覆盖连接基板面板110P、缓冲存储器芯片10和控制器芯片20的顶表面。下模制层130可以填充其中提供缓冲存储器芯片10和控制器芯片20的空腔110c。下模制层130可以由绝缘聚合物(例如环氧基聚合物)形成或者包括绝缘聚合物(例如环氧基聚合物)。
在下模制层130的形成之后，支撑基板300可以被去除。例如，支撑基板300可以被加热以去除粘合层的粘合特性，因而，支撑基板300可以与连接基板面板110P、缓冲存储器芯片10和控制器芯片20分离。
参照图17，在支撑基板300的去除之后，下再分布层120可以在连接基板面板110P、缓冲存储器芯片10和控制器芯片20的底表面上形成。
在一些示例实施方式中，下再分布层120的形成可以包括：形成第一下绝缘层1211，其具有暴露连接基板面板110P以及缓冲存储器芯片10和控制器芯片20的通路孔；在第一下绝缘层1211上形成下再分布图案123和下再分布通路125；形成第二下绝缘层1212以覆盖下再分布图案123；在第二下绝缘层1212上形成外连接焊盘127；以及在第二下绝缘层1212上形成下保护层129以暴露外连接焊盘127。
作为一示例，第一下绝缘层1211可以覆盖连接基板面板110P、缓冲存储器芯片10和控制器芯片20的底表面。第一下绝缘层1211可以被图案化以形成暴露芯片焊盘11和21以及下焊盘117a的通路孔。
在通路孔的形成之后，金属籽晶层(未示出)可以在第一下绝缘层1211的表面上形成。金属籽晶层可以通过诸如电镀法、无电镀法、溅射法的膜沉积法而形成。金属籽晶层可以由铬(Cr)、钛(Ti)、铜(Cu)、镍(Ni)、锡(Sn)或其合金中的至少一种形成或者包括铬(Cr)、钛(Ti)、铜(Cu)、镍(Ni)、锡(Sn)或其合金中的至少一种。
此后，光致抗蚀剂图案(未示出)可以在金属籽晶层上形成，然后，金属图案可以使用电镀法在由光致抗蚀剂图案暴露的金属籽晶层上形成。接着，光致抗蚀剂图案可以被去除，然后下再分布图案123和下再分布通路125可以通过使用金属图案作为蚀刻掩模选择性地蚀刻金属籽晶层而形成。
第二下绝缘层1212和外连接焊盘127可以在第一下绝缘层1211上形成以覆盖下再分布图案123。外连接焊盘127可以通过与用于形成下再分布图案123和下再分布通路125的方法基本上相同的方法而形成。外连接焊盘127可以通过通路联接到下再分布图案123。
在其中下保护层129由聚酰亚胺基材料(例如光敏聚酰亚胺(PSPI))形成的情况下，下保护层129可以通过旋涂工艺而形成，并且可以通过曝光工艺而非通过形成光致抗蚀剂层的额外工艺而被图案化。曝光工艺可以被执行以形成暴露外连接焊盘127的开口。
此外，在下保护层129的形成之后，粘合导电图案(未示出)可以在通过下保护层129的开口而暴露的外连接焊盘127上形成。粘合导电图案可以是用作粘合层、扩散防止层和润湿层的凸块下金属(under-bump metallurgy)(UBM)。粘合导电图案可以包括金属(例如铬(Cr)、钛(Ti)、铜(Cu)、镍(Ni)、钛-钨(TiW)或镍-钒(NiV))中的至少一种，并且可以形成为具有多层结构。作为一示例，粘合导电图案可以形成为具有Ti/Cu、Cr/Cr-Cu/Cu、TiW/Cu、Al/NiV/Cu和Ti/Cu/Ni结构中的一种。
参照图18，上再分布层140可以在连接基板面板110P、缓冲存储器芯片10和控制器芯片20的顶表面上形成。
在一些示例实施方式中，上再分布层140的形成可以包括：在下模制层130上形成上绝缘层141，形成穿透上绝缘层141和下模制层130的通路孔，以及在具有通路孔的上绝缘层141上形成上再分布图案143和上再分布图案通路145。
详细地，上绝缘层141可以形成为覆盖下模制层130。上绝缘层141可以由不同于下模制层130的绝缘材料形成。例如，上绝缘层141可以由硅氧化物层、硅氮化物层或硅氮氧化物层形成。
通路孔可以通过使用激光打孔工艺选择性地去除上绝缘层141和下模制层130而形成。
上再分布图案143和上再分布通路145可以通过诸如电镀法、无电镀法、溅射法的膜沉积法而形成，并且可以包括籽晶层和金属图案，类似于下再分布图案123和下再分布通路125。上绝缘层141可以形成为暴露上再分布层140的上再分布图案143中的最上面的上再分布图案的部分。
在某些示例实施方式中，形成上再分布层140的工艺可以被省略。
参照图19，外连接端子150可以被附接到下再分布层120的外连接焊盘127。外连接端子150可以是焊料球或焊料凸块。外连接端子150可以经由下再分布层120电连接到连接基板面板110P、缓冲存储器芯片10和控制器芯片20。
在一些示例实施方式中，如图13中所示，外连接端子150可以是球栅阵列(BGA)，并且可以不附接到外连接焊盘127中的一些。
参照图20，可以对连接基板面板110P执行锯切工艺，因而，连接基板面板110P可以被分成其每个包括缓冲存储器芯片10和控制器芯片20的多个单位区域UR。
例如，激光或锯切刀片可以用于切割单位区域UR之间的下再分布层120和上再分布层140、下模制层130以及连接基板面板110P。结果，连接基板面板110P可以被分成彼此分离的多个集成电路基板100。如上所述，集成电路基板100的每个可以包括连接基板110、下再分布层120和上再分布层140、缓冲存储器芯片10和控制器芯片20。
参照图21，非易失性存储器芯片30和无源器件40可以被安装在集成电路基板100的每个上。
例如，多个非易失性存储器芯片30可以使用粘合层被堆叠在集成电路基板100的上再分布层140上。这里，如上所述，非易失性存储器芯片30可以被堆叠成各种各样的形状。
在一些示例实施方式中，在非易失性存储器芯片30的堆叠之后，金属线W可以被接合到上再分布层140的上再分布图案以及接合到非易失性存储器芯片30的输入/输出焊盘31。在某些示例实施方式中，非易失性存储器芯片30可以以倒装芯片接合方式被安装在上再分布层140上。
无源器件40可以使用焊料凸块被附接到上再分布层140的上再分布图案143。在某些示例实施方式中，如上所述，无源器件40可以被提供在集成电路基板100中或连接基板110中。
此后，如上所述，上模制层230可以被形成以覆盖上再分布层140。
在某些示例实施方式中，如图2中所示，包括安装在封装基板210上的非易失性存储器芯片30的上封装200可以以倒装芯片接合方式被安装在集成电路基板100上。
根据本发明构思的一些示例实施方式，固态驱动器可以由单个半导体封装构成，因而可以被容易地安装到便携式电子设备。此外，多个非易失性存储器芯片可以被提供在具有控制器芯片的集成电路基板上，这使得可以减小固态驱动器封装的厚度。
因此，可以减小固态驱动器封装在便携式电子设备中的占用空间从而减小便携式电子设备的尺寸。此外，这使得可以增大便携式电子设备中提供的其它电子部件(例如电池等)的尺寸。
虽然已经具体显示和描述了本发明构思的示例实施方式，但是本领域普通技术人员将理解，可以在其中作出形式和细节上的变化而不背离所附权利要求的精神和范围。
本申请要求享有2016年7月21日提交的美国临时专利申请第62/364,933号以及2016年10月6日提交的韩国专利申请第10-2016-0129206号的优先权，其内容通过引用其全文合并于此。

Claims (19)

1.一种固态驱动器封装，包括：
集成电路基板，其包括：
下再分布层；
易失性存储器和存储控制器，所述易失性存储器和所述存储控制器被提供在所述下再分布层上；
提供在所述下再分布层上的连接基板，所述连接基板被提供在所述易失性存储器的外周和所述存储控制器的外周上；以及
下模制层，其覆盖所述易失性存储器、所述存储控制器和所述连接基板的顶表面，且被配置为支撑所述易失性存储器、所述存储控制器和所述连接基板；
提供在所述集成电路基板上的多个非易失性存储器件；
上模制层，其被提供在所述集成电路基板的顶表面上以覆盖所述多个非易失性存储器件；以及
屏蔽层，其从所述集成电路基板的侧表面延伸到所述上模制层的侧表面和所述上模制层的顶表面，
其中所述多个非易失性存储器件经由所述连接基板和所述下再分布层电连接到所述易失性存储器和所述存储控制器，以及
其中所述连接基板包括绝缘层、所述绝缘层的底表面上的下焊盘、所述绝缘层的顶表面上的上焊盘、以及设置在所述绝缘层中且连接所述下焊盘和所述上焊盘的导电通路。
2.根据权利要求1所述的固态驱动器封装，其中所述下再分布层包括：
覆盖所述连接基板的底表面、所述易失性存储器的底表面和所述存储控制器的底表面的至少两个下绝缘层；
提供在所述至少两个下绝缘层之间并联接到所述连接基板、所述易失性存储器和所述存储控制器的至少一个下再分布图案层；以及
连接到所述至少一个下再分布图案层的外连接焊盘。
3.根据权利要求2所述的固态驱动器封装，其中所述易失性存储器经由所述至少一个下再分布图案层连接到所述存储控制器。
4.根据权利要求2所述的固态驱动器封装，其中所述连接基板经由所述至少一个下再分布图案层连接到所述易失性存储器和所述存储控制器。
5.根据权利要求1所述的固态驱动器封装，其中所述下再分布层的厚度小于所述连接基板的厚度，或者所述下再分布层的厚度小于所述易失性存储器或所述存储控制器的厚度。
6.根据权利要求1所述的固态驱动器封装，还包括提供在所述集成电路基板上的无源器件，所述无源器件经由所述连接基板和所述下再分布层连接到所述存储控制器。
7.根据权利要求1所述的固态驱动器封装，还包括提供在所述下再分布层上的无源器件，所述无源器件经由所述下再分布层连接到所述存储控制器。
8.根据权利要求1所述的固态驱动器封装，其中所述集成电路基板还包括上再分布层，所述上再分布层被提供在所述下模制层上以覆盖所述连接基板的顶表面、所述易失性存储器的顶表面和所述存储控制器的顶表面，以及
其中所述上再分布层电连接到所述连接基板。
9.根据权利要求8所述的固态驱动器封装，其中所述上再分布层的厚度小于所述连接基板的厚度，或者所述上再分布层的厚度小于所述易失性存储器或所述存储控制器的厚度。
10.根据权利要求8所述的固态驱动器封装，其中所述多个非易失性存储器件经由金属线电连接到所述上再分布层。
11.根据权利要求8所述的固态驱动器封装，其中所述上再分布层包括：
覆盖所述下模制层且提供在所述连接基板的顶表面、所述易失性存储器的顶表面和所述存储控制器的顶表面上的至少两个上绝缘层；以及
提供在所述至少两个上绝缘层之间的至少一个上再分布图案层，所述至少一个上再分布图案层联接到所述连接基板，
其中所述多个非易失性存储器件被堆叠在所述至少两个上绝缘层中的最上一个上。
12.根据权利要求1所述的固态驱动器封装，还包括：
封装基板，其被提供在所述集成电路基板与所述多个非易失性存储器件之间；以及
连接端子，其被提供在所述封装基板的底表面上以将所述封装基板连接到所述连接基板，
其中所述多个非易失性存储器件经由金属线电连接到所述封装基板。
13.根据权利要求12所述的固态驱动器封装，还包括上模制层，所述上模制层被提供在所述封装基板的顶表面上以覆盖所述多个非易失性存储器件。
14.一种固态驱动器封装，包括：
集成电路基板，其包括：
下再分布层；
第一芯片和第二芯片，所述第一芯片和所述第二芯片被提供在所述下再分布层上；
提供在所述下再分布层上的连接基板，所述连接基板被提供在所述第一芯片的外周和所述第二芯片的外周上；以及
下模制层，其覆盖所述第一芯片、所述第二芯片和所述连接基板的顶表面，且被配置为支撑所述第一芯片、所述第二芯片和所述连接基板；提供在所述集成电路基板上的多个第三芯片；
上模制层，其被提供在所述集成电路基板的顶表面上以覆盖所述多个第三芯片；以及
屏蔽层，其从所述集成电路基板的侧表面延伸到所述上模制层的侧表面和所述上模制层的顶表面，
其中所述多个第三芯片经由所述连接基板和所述下再分布层电连接到所述第一芯片和所述第二芯片，以及
其中所述连接基板包括绝缘层、所述绝缘层的底表面上的下焊盘、所述绝缘层的顶表面上的上焊盘、以及设置在所述绝缘层中且连接所述下焊盘和所述上焊盘的导电通路。
15.一种固态驱动器封装，包括：
集成电路基板，其包括：
第一再分布层；
第一芯片和第二芯片，所述第一芯片和所述第二芯片被提供在所述第一再分布层上；
提供在所述第一再分布层上的连接基板，所述连接基板被提供在所述第一芯片的外周和所述第二芯片的外周上；以及
下模制层，其覆盖所述第一芯片、所述第二芯片和所述连接基板的顶表面，且被配置为支撑所述第一芯片、所述第二芯片和所述连接基板；上封装，其被提供在所述集成电路基板上并包括：
封装基板；以及
堆叠在所述封装基板上的多个第三芯片；
提供在所述集成电路基板与所述上封装之间的连接层；以及
屏蔽层，其从所述集成电路基板的侧表面延伸到所述上封装的侧表面、所述连接层的侧表面和所述上封装的顶表面，
其中所述连接层包括第二再分布层和连接端子层中的至少一个，
其中所述多个第三芯片经由所述连接层、所述连接基板和所述第一再分布层电连接到所述第一芯片，以及
其中所述连接基板包括绝缘层、所述绝缘层的底表面上的下焊盘、所述绝缘层的顶表面上的上焊盘、以及设置在所述绝缘层中且连接所述下焊盘和所述上焊盘的导电通路。
16.根据权利要求15所述的固态驱动器封装，其中所述连接端子层包括多个焊料球或多个焊料凸块。
17.根据权利要求15所述的固态驱动器封装，其中所述第二再分布层包括：
覆盖所述下模制层且提供在所述连接基板的顶表面、所述第一芯片的顶表面和所述第二芯片的顶表面上的至少两个第二绝缘层；以及
提供在所述至少两个第二绝缘层之间的至少一个第二再分布图案层，所述至少一个第二再分布图案层联接到所述连接基板，
其中所述多个第三芯片被堆叠在所述至少两个第二绝缘层中的最上一个上。
18.根据权利要求15所述的固态驱动器封装，其中所述第一再分布层包括：
覆盖所述连接基板的底表面、所述第一芯片的底表面和所述第二芯片的底表面的至少两个第一绝缘层；
提供在所述至少两个第一绝缘层之间并联接到所述连接基板、所述第一芯片和所述第二芯片的至少一个第一再分布图案层；以及
连接到所述至少一个第一再分布图案层的外连接焊盘。
19.根据权利要求15所述的固态驱动器封装，其中所述第一芯片包括控制器芯片，所述第二芯片包括第二存储器芯片，以及所述多个第三芯片包括多个第三存储器芯片。
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Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107424974A (zh) * 2016-05-24 2017-12-01 胡迪群 具有埋入式噪声屏蔽墙的封装基板
KR102605617B1 (ko) 2016-11-10 2023-11-23 삼성전자주식회사 적층 반도체 패키지
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
TWI765944B (zh) 2016-12-14 2022-06-01 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列（ｆｐｇａ）積體電路晶片組成之邏輯驅動器
WO2018125254A1 (en) * 2016-12-31 2018-07-05 Intel Corporation Electronic device package
TWI643305B (zh) * 2017-01-16 2018-12-01 力成科技股份有限公司 封裝結構及其製造方法
CN109075146A (zh) * 2017-02-20 2018-12-21 新电元工业株式会社 电子装置、连接体以及电子装置的制造方法
US20190013214A1 (en) * 2017-07-10 2019-01-10 Powertech Technology Inc. Package structure and manufacturing method thereof
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10886263B2 (en) * 2017-09-29 2021-01-05 Advanced Semiconductor Engineering, Inc. Stacked semiconductor package assemblies including double sided redistribution layers
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
KR20190121560A (ko) * 2018-04-18 2019-10-28 삼성전기주식회사 팬-아웃 반도체 패키지
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
TWI700798B (zh) * 2018-07-12 2020-08-01 南韓商三星電子股份有限公司 半導體封裝
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
JP2020047652A (ja) 2018-09-14 2020-03-26 キオクシア株式会社 半導体記憶装置及び電子機器
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11075260B2 (en) * 2018-10-31 2021-07-27 Qualcomm Incorporated Substrate comprising recessed interconnects and a surface mounted passive component
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
KR102524812B1 (ko) * 2018-11-06 2023-04-24 삼성전자주식회사 반도체 패키지
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
KR102632367B1 (ko) * 2018-12-04 2024-02-02 삼성전기주식회사 반도체 패키지
KR20200076778A (ko) 2018-12-19 2020-06-30 삼성전자주식회사 반도체 패키지의 제조방법
US11990449B2 (en) * 2019-01-14 2024-05-21 Intel Corporation Dual RDL stacked die package using vertical wire
JP7242366B2 (ja) 2019-03-22 2023-03-20 キオクシア株式会社 半導体装置
CN110731012B (zh) * 2019-04-15 2021-01-29 长江存储科技有限责任公司 具有处理器和异构存储器的一体化半导体器件及其形成方法
US10964616B2 (en) * 2019-06-17 2021-03-30 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
WO2021002387A1 (ja) * 2019-07-04 2021-01-07 パナソニックＩｐマネジメント株式会社 記憶装置ユニット
US11424212B2 (en) * 2019-07-17 2022-08-23 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
JP7392308B2 (ja) * 2019-07-19 2023-12-06 富士電機株式会社 半導体装置
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
KR20210044934A (ko) * 2019-10-15 2021-04-26 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR20210077290A (ko) * 2019-12-17 2021-06-25 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
KR20210097406A (ko) * 2020-01-30 2021-08-09 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR20210109179A (ko) 2020-02-27 2021-09-06 삼성전자주식회사 반도체 패키지
KR20220054086A (ko) * 2020-10-23 2022-05-02 삼성전자주식회사 반도체 패키지
CN112420529B (zh) * 2020-11-27 2022-04-01 上海易卜半导体有限公司 封装件及形成封装件的方法
US20220173074A1 (en) 2020-11-27 2022-06-02 Yibu Semiconductor Co., Ltd. Chip Package and Method of Forming Chip Packages
KR20220092690A (ko) * 2020-12-24 2022-07-04 삼성전자주식회사 반도체 패키지
US11876085B2 (en) 2021-06-25 2024-01-16 Qualcomm Incorporated Package with a substrate comprising an embedded capacitor with side wall coupling
US20230011439A1 (en) * 2021-07-07 2023-01-12 Western Digital Technologies, Inc. Semiconductor Device Package Die Stacking System and Method
US20230137512A1 (en) * 2021-11-03 2023-05-04 Western Digital Technologies, Inc. Stacked ssd semiconductor device
CN115036301A (zh) * 2022-05-17 2022-09-09 佛山市国星光电股份有限公司 基板模组和基板模组的制作方法、显示模组

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6618267B1 (en) 1998-09-22 2003-09-09 International Business Machines Corporation Multi-level electronic package and method for making same
JP4055717B2 (ja) * 2004-01-27 2008-03-05 カシオ計算機株式会社 半導体装置およびその製造方法
KR100618892B1 (ko) * 2005-04-13 2006-09-01 삼성전자주식회사 와이어 본딩을 통해 팬 아웃 구조를 달성하는 반도체패키지
JP2009206429A (ja) * 2008-02-29 2009-09-10 Toshiba Corp 記憶媒体
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
US8653654B2 (en) 2009-12-16 2014-02-18 Stats Chippac Ltd. Integrated circuit packaging system with a stackable package and method of manufacture thereof
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
WO2012122388A2 (en) * 2011-03-08 2012-09-13 Georgia Tech Research Corporation Chip-last embedded interconnect structures and methods of making the same
US20140057394A1 (en) 2012-08-24 2014-02-27 Stmicroelectronics Pte Ltd. Method for making a double-sided fanout semiconductor package with embedded surface mount devices, and product made
JP6152254B2 (ja) * 2012-09-12 2017-06-21 新光電気工業株式会社 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
JP2014082245A (ja) * 2012-10-15 2014-05-08 J Devices:Kk 半導体記憶装置及びその製造方法
KR101537390B1 (ko) 2013-01-03 2015-07-16 하나마이크론(주) 인터포저를 이용한 적층형 반도체 패키지
KR20140088764A (ko) 2013-01-03 2014-07-11 하나 마이크론(주) 인터포저를 이용한 적층형 반도체 패키지
US9035461B2 (en) 2013-01-30 2015-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging methods
KR20140109134A (ko) * 2013-03-05 2014-09-15 삼성전자주식회사 멀티-채널을 갖는 반도체 패키지 및 관련된 전자 장치
KR102192356B1 (ko) * 2013-07-29 2020-12-18 삼성전자주식회사 반도체 패키지
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
KR101601388B1 (ko) 2014-01-13 2016-03-08 하나 마이크론(주) 반도체 패키지 및 그 제조 방법
US9236355B2 (en) 2014-04-17 2016-01-12 Apple Inc. EMI shielded wafer level fan-out pop package
KR102245134B1 (ko) * 2014-04-18 2021-04-28 삼성전자 주식회사 반도체 칩을 구비하는 반도체 패키지
US9425178B2 (en) 2014-07-08 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. RDL-first packaging process
KR20160025945A (ko) * 2014-08-28 2016-03-09 삼성전자주식회사 전자부품이 내장된 반도체 패키지
KR20160040363A (ko) * 2014-10-02 2016-04-14 삼성전자주식회사 반도체 패키지

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