CN107623017B - 显示设备及其制造方法 - Google Patents

显示设备及其制造方法 Download PDF

Info

Publication number
CN107623017B
CN107623017B CN201710568790.7A CN201710568790A CN107623017B CN 107623017 B CN107623017 B CN 107623017B CN 201710568790 A CN201710568790 A CN 201710568790A CN 107623017 B CN107623017 B CN 107623017B
Authority
CN
China
Prior art keywords
pad electrode
bump
electrode
driver
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710568790.7A
Other languages
English (en)
Other versions
CN107623017A (zh
Inventor
柳承洙
梁正道
赵正然
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Publication of CN107623017A publication Critical patent/CN107623017A/zh
Application granted granted Critical
Publication of CN107623017B publication Critical patent/CN107623017B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13028—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10242—Metallic cylinders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Ceramic Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

公开了显示设备及制造显示设备的方法，显示设备包括：柔性衬底，具有用于显示图像的显示区域和在显示区域外部的外围区域；第一焊盘电极，位于柔性衬底的外围区域中；以及驱动器，连接至第一焊盘电极。驱动器包括：电路板，包括驱动电路；第二焊盘电极，位于电路板的一侧上并且面向第一焊盘电极；凸起结构，位于第二焊盘电极的一侧上并且具有椭圆形横截面；以及凸块电极，位于凸起结构的一侧上并且连接至第一焊盘电极。凸块电极包括覆盖凸起结构的柱以及从柱的一侧延伸并且向第一焊盘电极突出的凸起部分。

Description

显示设备及其制造方法
相关申请的交叉引用
本申请要求于2016年7月15日提交韩国知识产权局的第10-2016-0089859号韩国专利申请的优先权和权益，所述专利申请的全部内容通过引用的方式并入本文。
技术领域
本发明实施方式的方面涉及显示设备及其制造方法。
背景技术
显示设备通常包括衬底和设置在衬底上的多个信号线和薄膜晶体管。此外，包括用于生成驱动显示设备的各种信号的集成电路(IC)的驱动器可以设置在衬底的区域中。
驱动器通过非导电膜(NCF)安装在衬底上。驱动器设置在衬底上，并且驱动器的凸块电极连接至衬底的焊盘电极以将信号传输至设置在衬底上的多个信号线。
当驱动器通过非导电膜安装时，可能由于例如驱动器的凸块电极上的凹坑而在驱动器与衬底的焊盘电极之间发生接触故障。
在本背景部分中公开的以上信息是为了加强对本发明背景的理解，并且因此其可含有并不构成现有技术的信息。
发明内容
本发明的实施方式的方面已致力于使驱动器与衬底之间的接触稳定。
本发明的示例性实施方式提供了显示设备，所述显示设备包括：柔性衬底，具有用于显示图像的显示区域和设置在显示区域外部的外围区域；第一焊盘电极，位于柔性衬底的外围区域中；以及驱动器，连接至第一焊盘电极。驱动器包括：电路板，包括驱动电路；第二焊盘电极，位于电路板的一侧上并且面向第一焊盘电极；凸起结构，位于第二焊盘电极的一侧上并且具有椭圆形横截面；以及凸块电极，位于凸起结构的一侧上并且连接至第一焊盘电极。凸块电极包括覆盖凸起结构的柱以及从柱的一侧延伸并且向第一焊盘电极突出的凸起部分。
凸起结构可以向第一焊盘电极突出。
显示设备还可以包括在第一焊盘电极上的接触辅助电极，并且凸起部分可以接触接触辅助电极。
凸起结构可以包含焊料或聚合物材料。
在凸起部分和柱彼此汇合处，柱的横截面可以大于凸起部分的横截面。
显示设备还可以包括在凸起结构与第二焊盘电极之间的辅助金属层。
柱的边缘可以接触辅助金属层。
本发明的另一个实施方式提供了用于制造显示设备的方法。所述方法包括：形成包括第一焊盘电极的第一柔性衬底；形成驱动器；以及将驱动器安装在第一柔性衬底上。驱动器的形成包括：在包括驱动电路的电路板的一侧上形成第二焊盘电极；在第二焊盘电极的一侧上形成具有开口的感光膜图案，所述开口与第二焊盘电极重叠；在开口中形成凸起结构材料层，使凸起结构材料层软熔以形成具有椭圆形横截面的凸起结构；在开口中形成凸块电极，所述凸块电极包括覆盖凸起结构的柱和从柱的一侧突出的凸起部分；去除感光膜图案。
将驱动器安装在第一柔性衬底上可以包括使凸块电极与第一焊盘电极彼此连接。
根据本发明的示例性实施方式，驱动器的凸块电极具有凸起部分，所以可以使驱动器与衬底之间的接触稳定。
附图说明
图1示出了根据本发明的示例性实施方式的显示设备；
图2示出了沿图1中的线II-II取得的横截面；
图3至图7示出了用于制造根据本发明的示例性实施方式的驱动器的方法；以及
图8示出了根据本发明的另一示例性实施方式的显示设备的横截面。
具体实施方式
将参考附图在下文中更全面地描述本发明，在附图中示出了本发明的示例性实施方式。如本领域的技术人员将认识到的，可以以多种不同的方式修改所描述的实施方式，而所有修改不脱离本发明的精神和范围。
为了更清楚地描述本发明的特征和方面，本发明的所描述实施方式的与说明无关的部分可以省去，并且在整个说明书中，相同的附图标号表示相同的元件。
附图中示出的每个部件的尺寸和厚度可以随意地示出以更好地理解和便于描述，并且本发明不限于此。例如，在附图中，为清楚起见，层、膜、面板、区域等的厚度可能被夸大。
应当理解，当元件或层被称为在另一元件或层“上”、“连接至”或“联接至”另一元件或层时，其可直接在该另一元件或层上，直接连接至或直接联接至该另一元件或层，或也可以存在一个或多个中间元件或层。当元件或层被称为“直接”在另一元件或层“上”、“直接连接至”或“直接联接至”另一元件或层时，不存在中间元件或层。例如，当第一元件被描述为“联接”或“连接”至第二元件时，第一元件可直接联接或直接连接至第二元件或者第一元件可通过一个或多个中间元件间接地联接或间接地连接至第二元件。当描述本发明的实施方式时，“可”的使用涉及“本发明的一个或多个实施方式”。当诸如“…中的至少一个”的措辞位于一系列元件之后时，修饰整个元件列表并且不修饰列表中的单个元件。另外，术语“示例性的”旨在是指示示例或图例。如本文所用的，可以认为术语“使用”、“通过使用”和“所使用的”分别与术语“利用”、“通过利用”和“所利用的”同义。
为了方便描述，可在本文使用诸如“之下”、“下方”、“下部”、“上方”、“上部”等的空间相对术语来描述如附图中所示出的一个元件或特征与另一元件(多个元件)或特征(多个特征)的关系。应当理解，除附图中所描绘的定向之外，空间相对术语旨在涵盖在使用中或操作中的设备的不同定向。例如，如果附图中的设备翻转，那么描述为在其他元件或特征“下方”或“之下”的元件将被定向为在其他元件或特征“上方”或“之上”。因此，术语“下方”可以包含上方和下方的定向两者。设备可以以其他方式定向(旋转90度或处于其他定向)并且本文所使用的空间相对描述语应当被相应地解释。
本文所用的术语仅是为了描述本发明的具体示例性实施方式的目的，并非旨在限制本发明的所描述的示例性实施方式。如本文所用的，除非上下文另外明确说明，否则单数形式“一(a)”和“一(an)”旨在也包括复数形式。此外，除非明确描述相反情况，否则术语“包括(include)”和“包含(comprise)”以及诸如“包括(includes)”、“包括有(including)”、“包含(comprises)”和“包含有(comprising)”的变型应理解为意指包括所陈述的元件但不排除任何其他元件。
应当理解，虽然本文可使用术语第一、第二、第三等来描述各种元件、部件、区域、层和/或区段，但是这些元件、部件、区域、层和/或区段不应受这些术语限制。这些术语用来区别一个元件、部件、区域、层或区段与另一元件、部件、区域、层或区段。因此，在不脱离示例性实施方式的教导的情况下，以下所论述的第一元件、第一部件、第一区域、第一层或第一区段可被称为第二元件、第二部件、第二区域、第二层或第二区段。
短语“在平面上”意指从其顶部观察对象部分，并且短语“在横截面上”意指从侧面观察对象部分的垂直切割的横截面。
本文所述的根据本发明实施方式的驱动器和/或任何其他相关设备或部件可以利用任何合适的硬件、固件(例如，专用集成电路)、软件和/或软件、固件和硬件的合适组合来实施。例如，驱动器的各种部件可以形成在一个集成电路(IC)芯片上或形成在分离的IC芯片上。此外，驱动器的各种部件可以实施在柔性印刷电路膜、带载封装(TCP)、印刷电路板(PCB)上或形成在与驱动器相同的衬底上。此外，驱动器的各种部件可以是进程或线程，在一个或多个处理器上运行、在一个或多个计算设备中、执行计算机程序指令以及与用于执行如本文所述的各种功能的其他系统部件交互。计算机程序指令存储在存储器中，所述存储器可以使用诸如例如随机存取存储器(RAM)的标准存储器设备实现在计算设备中。计算机程序指令也可以存储在诸如例如CD-ROM、闪存驱动器等的其他非暂时性计算机可读介质中。另外，本领域的技术人员应当认识到，在不背离本发明的示例性实施方式的范围的情况下，各种计算设备的功能可以被组合或集成到单个计算设备中，或者特定计算设备的功能可以跨一个或多个其他计算设备分布。
现将参考图1和图2详细描述根据本发明的示例性实施方式的显示设备。
图1示出了根据本发明的示例性实施方式的显示设备。图2示出了沿图1中的线II-II取得的横截面。
参考图1，显示设备1000包括第一衬底100、面向第一衬底100的第二衬底200、以及驱动器300。
第一衬底100和第二衬底200可以是包含具有优异耐热性和耐久性的材料的柔性衬底，所述材料诸如聚萘二甲酸乙二醇酯(PEN)、聚碳酸酯(PC)、聚芳酯(PAR)、聚醚酰亚胺(PEI)、聚醚砜(PES)和/或聚酰亚胺(PI)。此外，在一些实施方式中，第一衬底100和第二衬底200可以包括(或可以是)由各种合适的柔性材料制成的柔性衬底。
多个薄膜晶体管、栅极线、数据线和有机发光二极管可以设置在第一衬底100上。第二衬底200通过密封剂组合至(或联接至)第一衬底100以用作封装衬底。
此外，在其他实施方式中，多个薄膜晶体管、栅极线、数据线和像素电极可以设置在第一衬底100上，多个滤色器和一个或多个公共电极可以设置在第二衬底200上，并且液晶层可以设置在第一衬底100与第二衬底200之间。然而，在一些实施方式中，滤色器和公共电极可以设置在第一衬底100上。
第一衬底100包括用于显示图像的显示区域(D)和设置在显示区域(D)的一个边缘上的外围区域(P)。然而，显示区域(D)和外围区域(P)的位置可以以许多不同方式变化。图1示出了外围区域(P)设置在显示区域(D)的下边缘上的示例性实施方式。然而，在其他实施方式中，外围区域(P)可以设置在显示区域(D)的下边缘和左边缘上。在此类实施方式中，外围区域(P)可以具有L形状。在其他实施方式中，外围区域(P)可以设置成围绕显示区域(D)(例如，设置成围绕显示区域(D)的周边)。
第二衬底200设置在显示区域(D)中并且不与驱动器300重叠(例如，驱动器300暴露在第二衬底200的外部)。驱动器300设置在外围区域(P)中并且通过非导电膜(NCF)结合至第一衬底100。驱动器300接收来自外部的驱动信号并且将与所接收的驱动信号对应的驱动信号传输至显示区域(D)。
现将参考图2进一步描述安装在第一衬底100上的驱动器300。
参考图2，第一焊盘电极110、第一绝缘层120和接触辅助电极130设置在第一衬底100上。接触辅助电极130通过第一绝缘层120中的第一接触开口125(例如，第一接触孔)连接至第一焊盘电极110。第一焊盘电极110和接触辅助电极130设置在外围区域(P)中。
驱动器300包括电路板310、第二焊盘电极320、第二绝缘层330、辅助金属层340、凸起结构350和凸块电极360，其中，电路板310包括驱动电路。
第二焊盘电极320设置在电路板310的一侧上并且面向第一焊盘电极110。第二绝缘层330设置在电路板310上并且在第二焊盘电极320的一侧上。
辅助金属层340设置在第二绝缘层330的一侧上并且通过第二绝缘层330中的第二接触开口335(例如，第二接触孔)连接至第二焊盘电极320。
凸起结构350设置在辅助金属层340的一侧上并且与第二焊盘电极320重叠。凸起结构350具有从辅助金属层340朝向第一焊盘电极110突出的凸起形状并且具有椭圆形横截面。凸起结构350可以包含导电材料，例如，焊料或聚合物材料。
凸块电极360设置在辅助金属层340上并且在凸起结构350的一侧上。凸块电极360包含金属，例如，金(Au)、铜(Cu)、银(Ag)、铂(Pt)、钯(Pd)、镍(Ni)或铝(Al)。
凸块电极360包括柱361和凸起部分362。柱361覆盖凸起结构350，并且柱361的边缘接触辅助金属层340。凸起部分362从柱361的另一边缘延伸并且朝向第一焊盘电极110突出。在柱361和凸起部分362彼此汇合处(例如，在柱361和凸起部分362的虚拟边界上)，柱361的横截面大于(例如宽于)凸起部分362的横截面。
凸起部分362接触接触辅助电极130。凸起部分362的接触接触辅助电极130的表面可以具有平坦的侧部。例如，驱动器300的第二焊盘电极320通过辅助金属层340、凸块电极360和接触辅助电极130连接至设置在第一衬底100上的第一焊盘电极110。从外部施加至驱动器300的驱动信号通过第一焊盘电极110传输至显示区域(D)。
凸起结构350是具有椭圆形横截面的突出部并且被设置成使得设置在凸起结构350的一侧上的凸块电极360包括突出的凸起部分362。
目前描述的示例性实施方式已被描述为包括从柱361延伸的一个凸起部分362，但是在其他实施方式中，多个凸起部分362可以从柱361延伸。在这些实施方式中，设置了多个凸起结构350(例如设置在辅助金属层340上)，并且凸起结构350中的每个可以被设置成与凸起部分362中的一个对应。
如所描述的，凸块电极360包括接触接触辅助电极130的凸起部分362，从而防止在凸块电极360中产生凹坑，并且增大与接触辅助电极130的接触面积。因此，驱动器300可以稳定地接触第一衬底100。
现将参考图1至图7描述用于制造根据本发明的示例性实施方式的显示设备的方法。
图3至图7示出了用于制造根据本发明的示例性实施方式的驱动器的方法。
根据目前描述的示例性实施方式的制造显示设备1000的方法包括提供第一衬底100(例如，第一柔性衬底)和第二衬底200(例如，第二柔性衬底)、形成驱动器300、以及将驱动器300安装在第一衬底100上(例如，参见图1)。在此类实施方式中，驱动器300连接至设置在第一衬底100上的第一焊盘电极110。
现将进一步详细描述用于形成驱动器300和将驱动器300安装在第一衬底100上的过程。
参考图3，将第二焊盘电极320形成在电路板310的一侧上，并且将第二绝缘层330形成在电路板310和第二焊盘电极320上。将驱动电路设置在电路板310的与其上形成有第二焊盘电极320的一侧相反的一侧上。
通过蚀刻第二绝缘层330的部分(例如，一部分)来形成与第二焊盘电极320重叠的第二接触开口335。
参考图4，将辅助金属层340形成在第二绝缘层330上。辅助金属层340通过第二接触开口335连接至第二焊盘电极320。
将感光膜图案50形成在第二绝缘层330和辅助金属层340上。感光膜图案50包括用于暴露辅助金属层340的部分(例如，一部分)的开口。感光膜图案50中的开口与第二焊盘电极320重叠。
凸起结构材料层350a(例如，凸起结构形成材料层)形成在感光膜图案50中的开口中。凸起结构材料层350a可以包含焊料或聚合物材料。
参考图5，凸起结构350通过使凸起结构材料层350a软熔(reflow)形成。凸起结构350从辅助金属层340向上突出，并且具有椭圆形横截面。凸起结构350的边缘不接触感光膜图案50中的开口。例如，凸起结构350的边缘通过间隙(例如，预定间隙)与感光膜图案50中的开口的侧边分开(例如，间隔开)。
参考图6，将凸块电极360形成在感光膜图案50中的开口中。
凸块电极360包括柱361和凸起部分362。柱361覆盖凸起结构350，并且柱361的部分(例如，一部分)接触辅助金属层340。由于设置在柱361的下侧上的凸起结构350，所以凸起部分362从柱361的顶侧突出至感光膜图案50中的开口的外部。凸起部分362的顶侧的形状与凸起结构350的顶侧的形状对应。
凸起部分362的边缘设置在柱361的边缘内侧。例如，凸起部分362的底侧的面积小于柱361的顶侧的面积。
参考图2和图7，去除感光膜图案50以制造驱动器300，并且将驱动器300安装在第一衬底100的外围区域(P)上。
当将驱动器300安装在第一衬底100上时，凸块电极360连接至接触辅助电极130。例如，凸块电极360的凸起部分362接触接触辅助电极130，并且由于在驱动器300安装在第一衬底100上时形成的压力，凸起部分362的接触接触辅助电极130的部分(例如，一部分)可以制成为平坦的(例如，可以是平坦化的)。
现将参考图8描述根据本发明的另一示例性实施方式的显示设备。
图8示出了根据本发明的另一示例性实施方式的显示设备的横截面。
参考图8，通过与先前所述的元件相同的附图标记指示的根据目前所述的示例性实施方式的显示设备的元件与先前所述的元件相同或基本上相同，并且此类元件可以不再进行描述。图8中示出的示例性实施方式的以下描述将主要集中于与先前所述的实施方式不同的元件和/或配置。
凸块电极360包括柱361和凸起部分362。柱361覆盖凸起结构350。凸起部分362从柱361的一侧延伸并且向第一焊盘电极110突出(例如，突出以接触第一焊盘电极110)。在柱361和凸起部分362彼此汇合处(例如，在柱361和凸起部分362的虚拟边界处)，柱361的横截面对应于凸起部分362的横截面(例如，具有与凸起部分362的横截面相同或基本上相同的尺寸)。
凸起结构350设置在辅助金属层340的一侧上并且与第二焊盘电极320重叠。凸起结构350从辅助金属层340朝向第一焊盘电极110突出并且具有椭圆形横截面。凸起结构350可以包含导电材料，例如，焊料。
因此，驱动器300的第二焊盘电极320通过辅助金属层340、凸块电极360和接触辅助电极130连接至设置在第一衬底100上的第一焊盘电极110。因此，从外部施加至驱动器300的驱动信号通过第一焊盘电极110传输至显示区域(D)。
虽然已经结合目前认为是实际示例性实施方式的示例对本发明进行了描述，但应当理解，本发明不限于所公开的实施方式并且旨在覆盖包括在随附权利要求和其等同的精神和范围内的各种修改和等同布置。

Claims (15)

1.一种显示设备，包括：
柔性衬底，具有用于显示图像的显示区域和在所述显示区域外部的外围区域；
第一焊盘电极，位于所述柔性衬底的所述外围区域中；以及
驱动器，连接至所述第一焊盘电极，所述驱动器包括：
电路板，包括驱动电路；
第二焊盘电极，位于所述电路板的一侧上并且面向所述第一焊盘电极；
凸起结构，位于所述第二焊盘电极的一侧上，包括导电材料，并且具有椭圆形横截面；以及
凸块电极，位于所述凸起结构的一侧上并且连接至所述第一焊盘电极，所述凸块电极包括覆盖所述凸起结构的柱和从所述柱的一侧延伸并且向所述第一焊盘电极突出的凸起部分。
2.如权利要求1所述的显示设备，其中，所述凸起结构向所述第一焊盘电极突出。
3.如权利要求2所述的显示设备，还包括位于所述第一焊盘电极上的接触辅助电极，
其中，所述凸起部分接触所述接触辅助电极。
4.如权利要求3所述的显示设备，其中，所述凸起结构包含焊料或聚合物材料。
5.如权利要求4所述的显示设备，其中，在所述凸起部分和所述柱彼此汇合处，所述柱的横截面大于所述凸起部分的横截面。
6.如权利要求5所述的显示设备，还包括位于所述凸起结构与所述第二焊盘电极之间的辅助金属层。
7.如权利要求6所述的显示设备，其中，所述柱的边缘接触所述辅助金属层。
8.一种用于制造显示设备的方法，所述方法包括：
形成包括第一焊盘电极的第一柔性衬底；
形成驱动器；以及
将所述驱动器安装在所述第一柔性衬底上，
其中，所述形成所述驱动器包括：
在包括驱动电路的电路板的一侧上形成第二焊盘电极；
在所述第二焊盘电极的一侧上形成具有开口的感光膜图案，所述开口与所述第二焊盘电极重叠；
在所述开口中形成凸起结构材料层，使所述凸起结构材料层软熔以形成具有椭圆形横截面的凸起结构，其中，所述凸起结构包括导电材料；
在所述开口中形成凸块电极，所述凸块电极包括覆盖所述凸起结构的柱和从所述柱的一侧突出的凸起部分；以及
去除所述感光膜图案。
9.如权利要求8所述的方法，其中，所述将所述驱动器安装在所述第一柔性衬底上包括：
使所述凸块电极与所述第一焊盘电极彼此连接。
10.如权利要求9所述的方法，其中，所述凸起部分向所述第一焊盘电极突出。
11.如权利要求10所述的方法，其中，所述凸起结构向所述第一焊盘电极突出。
12.如权利要求11所述的方法，其中，所述凸起结构包含焊料或聚合物材料。
13.如权利要求12所述的方法，其中，在所述凸起部分和所述柱彼此汇合处，所述柱的横截面大于所述凸起部分的横截面。
14.如权利要求13所述的方法，其中，所述形成所述驱动器还包括：
在所述凸起结构与所述第二焊盘电极之间形成辅助金属层。
15.如权利要求14所述的方法，其中，所述柱的边缘接触所述辅助金属层。
CN201710568790.7A 2016-07-15 2017-07-13 显示设备及其制造方法 Active CN107623017B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020160089859A KR102666884B1 (ko) 2016-07-15 2016-07-15 표시 장치 및 그의 제조 방법
KR10-2016-0089859 2016-07-15

Publications (2)

Publication Number Publication Date
CN107623017A CN107623017A (zh) 2018-01-23
CN107623017B true CN107623017B (zh) 2023-06-20

Family

ID=60942211

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710568790.7A Active CN107623017B (zh) 2016-07-15 2017-07-13 显示设备及其制造方法

Country Status (3)

Country Link
US (1) US10262965B2 (zh)
KR (1) KR102666884B1 (zh)
CN (1) CN107623017B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109156080B (zh) 2016-05-16 2021-10-08 株式会社村田制作所 陶瓷电子部件
KR102521582B1 (ko) * 2018-04-03 2023-04-12 삼성전자주식회사 발광 다이오드 디스플레이 장치
KR102533660B1 (ko) * 2018-07-04 2023-05-17 삼성디스플레이 주식회사 표시 장치
KR102580325B1 (ko) * 2019-03-07 2023-09-20 주식회사 경동나비엔 액체 품질 측정기용 전극단자 어셈블리 및 그를 포함하는 액체 품질 측정기
CN110444562B (zh) * 2019-08-16 2021-12-21 成都辰显光电有限公司 一种显示面板及显示装置
CN111755463A (zh) * 2020-06-24 2020-10-09 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
USD1026947S1 (en) 2021-07-23 2024-05-14 Samsung Electronics Co., Ltd. Display screen or portion thereof with transitional graphical user interface
CN113725251B (zh) * 2021-08-30 2024-04-09 上海天马微电子有限公司 驱动基板和显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1065555A1 (en) * 1999-01-20 2001-01-03 Citizen Watch Co., Ltd. Structure for mounting semiconductor device on liquid crystal display, and semiconductor device
TWM243783U (en) * 2003-06-30 2004-09-11 Innolux Display Corp Structure of chip on glass
WO2007039960A1 (ja) * 2005-10-05 2007-04-12 Sharp Kabushiki Kaisha 配線基板及びそれを備えた表示装置
KR20080035905A (ko) * 2006-10-20 2008-04-24 삼성전자주식회사 유기 발광 표시 장치 및 그 제조 방법
US8035226B1 (en) * 2008-06-05 2011-10-11 Maxim Integrated Products, Inc. Wafer level package integrated circuit incorporating solder balls containing an organic plastic-core
CN102544055A (zh) * 2010-12-07 2012-07-04 三星移动显示器株式会社 有机发光显示装置及其制造方法
CN103823314A (zh) * 2012-11-19 2014-05-28 乐金显示有限公司 显示装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3763607B2 (ja) * 1996-04-10 2006-04-05 セイコーエプソン株式会社 液晶表示装置の製造方法及び液晶表示装置
JP2002076055A (ja) 2000-08-22 2002-03-15 Hitachi Ltd 半導体装置の実装方法および実装構造
JP3868766B2 (ja) 2001-07-02 2007-01-17 株式会社東芝 半導体装置
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
TW521361B (en) * 2002-02-27 2003-02-21 Advanced Semiconductor Eng Bump process
JP2005301056A (ja) * 2004-04-14 2005-10-27 Hitachi Displays Ltd 表示装置とその製造方法
KR101134168B1 (ko) * 2005-08-24 2012-04-09 삼성전자주식회사 반도체 칩 및 그 제조 방법과, 그를 이용한 표시 패널 및그 제조 방법
JP4355960B2 (ja) 2006-11-30 2009-11-04 セイコーエプソン株式会社 バンプ構造体、ｉｃチップ、ならびにｉｃチップと配線基板との実装構造
JP5395407B2 (ja) * 2008-11-12 2014-01-22 ルネサスエレクトロニクス株式会社 表示装置駆動用半導体集積回路装置および表示装置駆動用半導体集積回路装置の製造方法
KR101048829B1 (ko) 2009-05-27 2011-07-13 명지대학교 산학협력단 볼록 단부를 가지는 금속 기둥 범프 형성 방법
JP2012028708A (ja) 2010-07-27 2012-02-09 Renesas Electronics Corp 半導体装置
JP2012079956A (ja) 2010-10-04 2012-04-19 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
US8823180B2 (en) * 2011-12-28 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
KR20130123720A (ko) 2012-05-03 2013-11-13 에스케이하이닉스 주식회사 반도체 칩과 이를 갖는 반도체 패키지 및 이를 이용한 적층 반도체 패키지
KR20130126171A (ko) * 2012-05-11 2013-11-20 삼성전자주식회사 범프 구조물 및 이의 형성 방법
JP6326723B2 (ja) 2012-08-24 2018-05-23 Tdk株式会社 端子構造及び半導体素子
US20170323863A1 (en) * 2016-05-09 2017-11-09 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1065555A1 (en) * 1999-01-20 2001-01-03 Citizen Watch Co., Ltd. Structure for mounting semiconductor device on liquid crystal display, and semiconductor device
TWM243783U (en) * 2003-06-30 2004-09-11 Innolux Display Corp Structure of chip on glass
WO2007039960A1 (ja) * 2005-10-05 2007-04-12 Sharp Kabushiki Kaisha 配線基板及びそれを備えた表示装置
KR20080035905A (ko) * 2006-10-20 2008-04-24 삼성전자주식회사 유기 발광 표시 장치 및 그 제조 방법
US8035226B1 (en) * 2008-06-05 2011-10-11 Maxim Integrated Products, Inc. Wafer level package integrated circuit incorporating solder balls containing an organic plastic-core
CN102544055A (zh) * 2010-12-07 2012-07-04 三星移动显示器株式会社 有机发光显示装置及其制造方法
CN103823314A (zh) * 2012-11-19 2014-05-28 乐金显示有限公司 显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
平板显示器用的薄膜开关矩阵;G.Kramer等;《发光学报》;19760315(第01期);全文 *

Also Published As

Publication number Publication date
KR102666884B1 (ko) 2024-05-17
KR20180008985A (ko) 2018-01-25
US10262965B2 (en) 2019-04-16
CN107623017A (zh) 2018-01-23
US20180019220A1 (en) 2018-01-18

Similar Documents

Publication Publication Date Title
CN107623017B (zh) 显示设备及其制造方法
JP4024773B2 (ja) 配線基板、半導体装置およびその製造方法並びに半導体モジュール装置
US9349683B2 (en) Chip-on-film package having bending part
TWI384303B (zh) Liquid crystal display device
CN105826298B (zh) 半导体封装件和使用所述半导体封装件的封装模块
CN101587900A (zh) 柔性显示装置及其制造方法
US8344486B2 (en) Semiconductor device and display apparatus
JP2007048812A (ja) 半導体装置
KR20140059548A (ko) 회로 기판의 접속 구조
US10747038B2 (en) Display device
US9601445B2 (en) Semiconductor packages
US11036263B2 (en) Display device having an anisotropic conductive film
US20180114768A1 (en) Semiconductor chip, electronic device having the same and method of connecting semiconductor chip to electronic device
US11696474B2 (en) Display device
US10032708B2 (en) Circuit board and smart card module and smart card utilizing the same
JP2008090147A (ja) 接続端子基板及びこれを用いた電子装置
JP4656311B2 (ja) 電子モジュール
JP5220692B2 (ja) 表示装置
US9972567B2 (en) Multilayer substrate, component mounted board, and method for producing component mounted board
JP2020056951A (ja) 表示装置
JP4273347B2 (ja) 半導体装置
US20180033755A1 (en) Integrated circuit chip and display device including the same
JP2007019410A (ja) 半導体装置、及び、電子モジュールの製造方法
US11978743B2 (en) TFT array substrate and display panel including the same
CN115762329A (zh) 绑定结构、显示模组及显示装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant