CN1073745C - 隔离半导体器件的元件的方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
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- 238000000137 annealing Methods 0.000 claims 2
- 239000007789 gas Substances 0.000 claims 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 125000004433 nitrogen atom Chemical group N* 0.000 abstract description 4
- 241000293849 Cordylanthus Species 0.000 abstract 1
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- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
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Abstract
一种隔离半导体器件的元件的方法,通过在衬垫氧化膜和硅衬底之间积累氮原子可以限制鸟嘴图形的产生,并且,利用湿腐蚀,在形成氮化物隔离层以后除掉在硅衬底上低温生长的氧化物,可控制硅衬底的腐蚀深度,由此,可重复生产具有优良外形的场氧化膜。
Description
本发明一般涉及隔离半导体器件中元件的方法,特别涉及限制LOCOS工艺产生的鸟嘴和控制凹进LOCOS工艺的腐蚀深度,并且提供上述限制和控制的方法。
现在利用的大多数元件隔离方法,取决于LOCOS工艺。特别是,广泛地利用凹进的LOCOS工艺,以便获得优良的场氧化膜的外形。
下面结合图1A到图1D,详细地叙述常规凹进LOCOS工艺。
首先,参看图1A剖视图,在硅衬底11上面形成衬垫氧化膜(pad oxidefilm)12后,接着,在缓冲氧化膜12上面形成厚的氮化硅膜13。
然后,例如,以光致抗蚀剂图形作为掩模(未表示),通过选择腐蚀,在预定区域顺序地对氮化膜13和缓冲氧化膜12开孔,以便形成露出硅衬底11预定区域的场区14。
接着,在获得的结构整个表面上,淀积薄的氧化氮膜,然后对其整个表面进行干腐蚀,以便在已形成图形的氮化硅膜13和衬垫氧化膜12的侧壁上形成氮化物隔离层15,如图1C所示。把露出的硅衬底11的场区14干腐蚀到预定深度,例如,大约300到800。这由标号16来表示。
图1D是剖面图,表示通过高温氧化形成场氧化膜17后,除了场氧化膜以外,除掉叠在硅衬底11上面的全部薄膜。在图1D中,标号18表示“鸟嘴”。
虽然在常规方法中采用了氮化物隔离层,但是不能充分防止沿着衬垫氧化膜产生“鸟嘴”状氧化物。而且当按照常规方法腐蚀硅衬底时,难以控制腐蚀深度,特别是小于500的腐蚀深度。可重复性很差。干腐蚀产生很大损伤。按常规方法,发现使场氧化膜和鸟嘴的形状造成很大的变化。此外,用来保证有源区的厚氮化物隔离层,在制造薄场的氧化膜时发生问题。
因此,本发明的目的是克服现有技术中遇到的上述问题,提供一种关于隔离半导体器件的元件的方法,其能够相当大程度地限制鸟嘴的产生,以便保证有源区,控制半导体衬底的腐蚀深度,重复产生场氧化膜的良好形状。
按照本发明,通过提供关于半导体器件隔离元件的方法,可实现上述目的,该方法包括下列步骤:在硅衬底上,形成应力缓冲层;在含氮气的气氛中进行退火,在硅衬底和缓冲层之间的界面处形成氮积累层;在整个获得结构的上面,淀积防氧化层;在场区选择腐蚀防氧化层和缓冲层,给出第一凹进区;在第一凹进区的侧壁上面形成限制鸟嘴产生的隔离层;在第一氧化工艺形成牺牲氧化膜;用湿腐蚀工艺去除牺牲氧化膜,在硅衬底中形成第二凹进区;以及在第二氧化工艺中形成场氧化膜。
下面按照本发明对此进行较详细的叙述,利用在衬垫氧化膜和硅衬底之间积累氮原子,可限制鸟嘴,利用湿腐蚀去除在形成氮化物隔离层后用低温在硅衬底上面生长的氧化物,可以控制硅衬底的腐蚀深度,由此,重复生长优良外形的场氧化膜。
从下面结合附图对实施例的叙述,本发明的其它目的和方案将变得显而易见。附图中:
图1A到图1D是表示常规凹进LOCOS工艺的剖视图;
图2A到图2F是表示按照本发明关于隔离半导体器件的元件的方法的示意剖视图。
结合各附图会更好地理解本发明的优选实施例,附图中分别利用相同的标号表示相同的和相应的部分。
图2A到图2F表示按照本发明的关于隔离半导体器件的元件的方法。
首先,如图2A所示,在硅衬底21上面,形成厚度大约为50到200衬垫氧化膜22,然后,把它在800到1000℃、在NH3气氛中、在10到100torr气压下退火约0.5到2小时,在硅衬底21和衬垫氧化膜22之间界面处,形成积累氮原子的氮氧化物层100。接着,淀积防止氧化的氮化物膜23,厚度为约1000到3000。
接着,利用掩模,通过腐蚀在预定区域顺序地把氮化膜23和衬垫氧化膜22开孔,形成场区。同时,选择地腐蚀氮氧化物层100,如图2B所示。
图2C是剖面图,表示在已开孔的氮化物膜23、衬垫氧化膜22和氮氧化物膜100的侧壁上形成的隔离氮化物膜25。因此,沿所得结构的整个表面,淀积如100-700厚的薄氮化膜,然后进行腐蚀,形成隔离氮化物膜25。
接着,在场区24的硅衬底21上面生长厚度为1000的氧化层200,如图2D所示。在如大约700到900℃的较低温下进行氧化。应当理解,氧化物200不是场氧化物,而是一种用于腐蚀硅衬底21的牺牲层。在这样低的温度下对硅衬底氧化是因为由于氧化在隔离氮化物膜25和硅衬底21之间产生的应力变大,实际上避免了鸟嘴图形的产生。而且,因为氧化层200有一个垂直的侧壁,当除掉氧化物200时,可以获得各向异性的硅凹进外形。
图2E是一个剖面图,表示利用HF溶液除掉场区的薄氧化物200后形成的凹进图形300。此时,腐蚀硅衬底21的深度大约为100到500。必须注意,该深度是由前述工艺生长的氧化物200确定的氧化物可以保留少许,其腐蚀可以控制在大约80到100%。
最后,在大约1000到1200℃的高温下形成场氧化膜27,厚度大约为2000到5000。然后,除掉在硅衬底21上面形成的所有其它膜。
由上述可见,按照本发明,当对硅衬底氧化形成氧化膜时,隔离氮化膜的应力增加,这减慢了氧扩散进入衬垫的速度。为了使氧扩散到衬垫达到某一程度,在硅衬底和衬垫氧化膜之间界面处积累的氮原子起到防止氧进一步扩散的作用,这样减少了鸟嘴形状的形成。
另外,利用牺牲氧化膜,实际上形成了与硅衬底垂直的外形,并且能适当地控制凹进深度。这样能重复形成优良的场氧化膜的外形。而且,因为本发明用湿法除掉了牺牲氧化膜,不会发生因湿腐蚀的腐蚀损伤引起的缺陷。
虽然通过举例叙述了本发明,但是应当理解,所用术语是叙述本发明的特性,而不是限制本发明。
由于上述教导的启发,可能对本发明进行各种修改和变化。因此,应当理解,除了特别说明之外,只要在权利要求范围之内,本发明不限于具体的实施方式。
Claims (11)
1、一种隔离半导体器件的元件的方法,包括下列步骤:
在硅衬底上形成应力缓冲层;
在含氮气体气氛中进行退火,在硅衬底和缓冲层之间的界面处形成积累氮的层;
在所得结构的整个表面上淀积防氧化层;
选择地腐蚀场区的防氧化层和缓冲层,以形成第一凹进区;
形成隔离层,以便限制在第一凹进区侧壁处鸟嘴图形的形成;
在第一次氧化过程中形成牺牲氧化膜;
用湿腐蚀工艺除掉牺牲氧化膜,以便在硅衬底中形成第二凹进区;
在第二氧化工艺形成场氧化膜。
2、根据权利要求1所述的方法,其中,在NH3气体气氛中进行所述的退火步骤。
3、根据权利要求2所述的方法,其中,在大约800到1000℃、在10到100乇压下进行所述的退火步骤,时间为0.5到2小时。
4、根据权利要求1所述的方法,其中,进行所述的选择腐蚀步骤,直到腐蚀积累氮的层。
5、根据权利要求1所述的方法,其中,在所述侧壁的方向形成所述的隔离层,厚度为100到700。
6、根据权利要求1所述的方法,其中,所述第二凹进区具有100到500的深度。
7、根据权利要求1所述的方法,其中,在700到900℃进行所述的第一氧化工艺。
8、根据权利要求7所述的方法,其中,形成100到1000厚的所述牺牲氧化膜。
9、根据权利要求1所述的方法,其中,除去总厚度的80到100%的所述的牺牲氧化膜。
10、根据权利要求1所述的方法,其中,所述限制氧化层和隔离层各包含一个氮化物膜。
11、根据权利要求10所述的方法,其中,所述缓冲层包括一个氧化膜。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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KR39693/95 | 1995-11-03 | ||
KR39693/1995 | 1995-11-03 | ||
KR1019950039693A KR100197651B1 (ko) | 1995-11-03 | 1995-11-03 | 반도체 소자의 소자 분리막 제조방법 |
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CN1156325A CN1156325A (zh) | 1997-08-06 |
CN1073745C true CN1073745C (zh) | 2001-10-24 |
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CN96121653A Expired - Fee Related CN1073745C (zh) | 1995-11-03 | 1996-11-03 | 隔离半导体器件的元件的方法 |
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Country | Link |
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US (1) | US5719086A (zh) |
JP (1) | JP2875787B2 (zh) |
KR (1) | KR100197651B1 (zh) |
CN (1) | CN1073745C (zh) |
DE (1) | DE19645440C2 (zh) |
GB (1) | GB2306780B (zh) |
TW (1) | TW312039B (zh) |
Families Citing this family (9)
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KR100209367B1 (ko) * | 1996-04-22 | 1999-07-15 | 김영환 | 반도체 소자의 소자분리 절연막 형성방법 |
KR100232899B1 (ko) * | 1997-06-02 | 1999-12-01 | 김영환 | 반도체소자의 소자분리막 제조방법 |
KR100235950B1 (ko) * | 1997-06-26 | 1999-12-15 | 김영환 | 반도체 소자의 필드 산화막 제조방법 |
US5940718A (en) * | 1998-07-20 | 1999-08-17 | Advanced Micro Devices | Nitridation assisted polysilicon sidewall protection in self-aligned shallow trench isolation |
KR100369776B1 (ko) * | 1999-12-28 | 2003-01-30 | 페어차일드코리아반도체 주식회사 | 반도체 소자용 박막의 표면 처리 방법 및 사진 식각 방법 |
KR100672761B1 (ko) * | 2001-06-28 | 2007-01-22 | 주식회사 하이닉스반도체 | 콘택 플러그 형성방법 |
US6495430B1 (en) * | 2002-05-21 | 2002-12-17 | Macronix International Co., Ltd. | Process for fabricating sharp corner-free shallow trench isolation structure |
KR100672753B1 (ko) | 2003-07-24 | 2007-01-22 | 주식회사 하이닉스반도체 | 전자트랩을 억제할 수 있는 트렌치형 소자분리막의 형성방법 |
US7804143B2 (en) * | 2008-08-13 | 2010-09-28 | Intersil Americas, Inc. | Radiation hardened device |
Citations (3)
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US5087586A (en) * | 1991-07-03 | 1992-02-11 | Micron Technology, Inc. | Process for creating fully-recessed field isolation regions by oxidizing a selectively-grown epitaxial silicon layer |
US5256895A (en) * | 1987-02-24 | 1993-10-26 | Sgs-Thomson Microelectronics, Inc. | Pad oxide protect sealed interface isolation |
US5399520A (en) * | 1993-03-31 | 1995-03-21 | Hyundai Electronics Industries Co., Ltd. | Method for the formation of field oxide film in semiconductor device |
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JPS5965445A (ja) * | 1982-10-05 | 1984-04-13 | Matsushita Electronics Corp | 半導体素子分離領域の形成方法 |
JPS5975667A (ja) * | 1982-10-25 | 1984-04-28 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JPS6072245A (ja) * | 1983-09-28 | 1985-04-24 | Toshiba Corp | 半導体装置の製造方法 |
DE3832450A1 (de) * | 1987-10-19 | 1989-04-27 | Ncr Co | Verfahren zum bilden von feldoxidbereichen in einem siliziumsubstrat |
NL8800903A (nl) * | 1988-04-08 | 1989-11-01 | Koninkl Philips Electronics Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumsubstraat met geheel of gedeeltelijk verzonken veldoxide-gebieden. |
US5298451A (en) * | 1991-04-30 | 1994-03-29 | Texas Instruments Incorporated | Recessed and sidewall-sealed poly-buffered LOCOS isolation methods |
KR940003224B1 (ko) * | 1991-10-12 | 1994-04-16 | 금성일렉트론 주식회사 | 반도체 소자의 격리방법 |
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1995
- 1995-11-03 KR KR1019950039693A patent/KR100197651B1/ko not_active IP Right Cessation
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1996
- 1996-11-01 US US08/742,885 patent/US5719086A/en not_active Expired - Lifetime
- 1996-11-01 GB GB9622822A patent/GB2306780B/en not_active Expired - Fee Related
- 1996-11-02 TW TW085113365A patent/TW312039B/zh active
- 1996-11-03 CN CN96121653A patent/CN1073745C/zh not_active Expired - Fee Related
- 1996-11-04 DE DE19645440A patent/DE19645440C2/de not_active Expired - Fee Related
- 1996-11-05 JP JP8292758A patent/JP2875787B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US5256895A (en) * | 1987-02-24 | 1993-10-26 | Sgs-Thomson Microelectronics, Inc. | Pad oxide protect sealed interface isolation |
US5087586A (en) * | 1991-07-03 | 1992-02-11 | Micron Technology, Inc. | Process for creating fully-recessed field isolation regions by oxidizing a selectively-grown epitaxial silicon layer |
US5399520A (en) * | 1993-03-31 | 1995-03-21 | Hyundai Electronics Industries Co., Ltd. | Method for the formation of field oxide film in semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
GB9622822D0 (en) | 1997-01-08 |
CN1156325A (zh) | 1997-08-06 |
US5719086A (en) | 1998-02-17 |
GB2306780B (en) | 2000-03-08 |
JP2875787B2 (ja) | 1999-03-31 |
KR970030626A (ko) | 1997-06-26 |
KR100197651B1 (ko) | 1999-06-15 |
DE19645440A1 (de) | 1997-05-07 |
DE19645440C2 (de) | 2002-06-20 |
GB2306780A (en) | 1997-05-07 |
JPH09181069A (ja) | 1997-07-11 |
TW312039B (zh) | 1997-08-01 |
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