CN107134414A - 半导体装置及其制造方法、倒装芯片型半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法、倒装芯片型半导体装置及其制造方法 Download PDF

Info

Publication number
CN107134414A
CN107134414A CN201710107328.7A CN201710107328A CN107134414A CN 107134414 A CN107134414 A CN 107134414A CN 201710107328 A CN201710107328 A CN 201710107328A CN 107134414 A CN107134414 A CN 107134414A
Authority
CN
China
Prior art keywords
substrate
semiconductor device
foregoing
insulating barrier
conductive plug
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710107328.7A
Other languages
English (en)
Other versions
CN107134414B (zh
Inventor
曾我恭子
浅井聪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Chemical Co Ltd
Original Assignee
Shin Etsu Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Publication of CN107134414A publication Critical patent/CN107134414A/zh
Application granted granted Critical
Publication of CN107134414B publication Critical patent/CN107134414B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G59/00—Polycondensates containing more than one epoxy group per molecule; Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups
    • C08G59/18—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing
    • C08G59/40—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing characterised by the curing agents used
    • C08G59/62—Alcohols or phenols
    • C08G59/621—Phenols
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G59/00—Polycondensates containing more than one epoxy group per molecule; Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups
    • C08G59/18—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing
    • C08G59/40—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing characterised by the curing agents used
    • C08G59/62—Alcohols or phenols
    • C08G59/621—Phenols
    • C08G59/623—Aminophenols
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G77/00—Macromolecular compounds obtained by reactions forming a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon in the main chain of the macromolecule
    • C08G77/04—Polysiloxanes
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G77/00—Macromolecular compounds obtained by reactions forming a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon in the main chain of the macromolecule
    • C08G77/04—Polysiloxanes
    • C08G77/14—Polysiloxanes containing silicon bound to oxygen-containing groups
    • C08G77/18—Polysiloxanes containing silicon bound to oxygen-containing groups to alkoxy or aryloxy groups
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L63/00—Compositions of epoxy resins; Compositions of derivatives of epoxy resins
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L83/00—Compositions of macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon only; Compositions of derivatives of such polymers
    • C08L83/14—Compositions of macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon only; Compositions of derivatives of such polymers in which at least two but not all the silicon atoms are connected by linkages other than oxygen atoms
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/038—Macromolecular compounds which are rendered insoluble or differentially wettable
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/038—Macromolecular compounds which are rendered insoluble or differentially wettable
    • G03F7/0382—Macromolecular compounds which are rendered insoluble or differentially wettable the macromolecular compound being present in a chemically amplified negative photoresist composition
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/075—Silicon-containing compounds
    • G03F7/0757—Macromolecular compounds containing Si-O, Si-C or Si-N bonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/296—Organo-silicon compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G77/00—Macromolecular compounds obtained by reactions forming a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon in the main chain of the macromolecule
    • C08G77/48—Macromolecular compounds obtained by reactions forming a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon in the main chain of the macromolecule in which at least two but not all the silicon atoms are connected by linkages other than oxygen atoms
    • C08G77/50—Macromolecular compounds obtained by reactions forming a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon in the main chain of the macromolecule in which at least two but not all the silicon atoms are connected by linkages other than oxygen atoms by carbon linkages
    • C08G77/52—Macromolecular compounds obtained by reactions forming a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon in the main chain of the macromolecule in which at least two but not all the silicon atoms are connected by linkages other than oxygen atoms by carbon linkages containing aromatic rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/13291—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/13393—Base material with a principal constituent of the material being a solid not provided for in groups H01L2224/133 - H01L2224/13391, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/271—Manufacture and pre-treatment of the layer connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H01L2224/27416—Spin coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H01L2224/27422—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form by dipping, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/276—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/27618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive layer material, e.g. of a photosensitive conductive resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/27848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/81204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053—Bonding environment
    • H01L2224/83054—Composition of the atmosphere
    • H01L2224/83075—Composition of the atmosphere being inert
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/83204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92143—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Organic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Polymers & Plastics (AREA)
  • Medicinal Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Materials For Photolithography (AREA)
  • Epoxy Resins (AREA)
  • Wire Bonding (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明提供一种半导体装置的制造方法，所述半导体装置的基板彼此或基板与元件的粘接良好，且它们的电性连接也良好。所述制造方法具备以下步骤：准备设置有衬垫或在衬垫上更设置有插头的第一基板与设置有插头的第二基板或元件；在第一基板的衬垫或插头及第二基板或元件的插头的至少一个上形成焊球；利用感光性绝缘层覆盖第一基板的衬垫形成面及第二基板或元件的插头形成面的至少一个；利用光刻在被感光性绝缘层覆盖的基板或元件中的衬垫或插头上形成开口；通过开口将第二基板或元件的插头经由焊球压接接合至第一基板的衬垫或插头；根据烘烤将第一基板的衬垫或插头与第二基板或元件的插头电性连接；利用烘烤将感光性绝缘层固化。

Description

半导体装置及其制造方法、倒装芯片型半导体装置及其制造 方法
技术领域
本发明涉及一种半导体装置的制造方法、倒装芯片型半导体装置的制造方法、半导体装置及倒装芯片型半导体装置。
背景技术
随着个人电脑、数码照相机、手机等各式各样的电子设备的小型化和高性能化，对于半导体元件的进一步小型化、薄型化及高密度化的要求也急速增加。因此，期望开发一种绝缘材料、绝缘材料积层的半导体装置和半导体装置的制造方法，所述绝缘材料可以应对生产率提升而伴随的基板面积增大，且可以应用在芯片尺寸封装或芯片级封装(chipscale package，CSP)或三维积层这样的高密度安装技术中。
而且，随着电子设备的高性能化、小型化发展，为了满足半导体元件对高密度化、高性能化的要求，半导体元件的制造工序也在持续发展。例如，实现布线规则的微细化以应对窄间距化、高速化，向使用超低电介质材料的脆弱半导体元件转变以应对高频化。
以往，作为将形成在半导体元件中的电极与形成在基板上的布线图案连接而得到的半导体装置的制造方法，可以列举一种利用引线接合而实施的半导体元件与基板的接合来作为示例。但是，在利用引线接合而实施的半导体元件与基板的接合中，需要在半导体元件上设置用以引出金属引线的空间，因此装置变大，难以实现小型化，无法满足这种高密度安装的要求。因此，设计出一种将已形成布线的基板彼此接合的晶片接合(waferbonding)、和将半导体元件搭载在基板上的芯片级封装或者倒装芯片安装，来作为实现三维安装的半导体元件的安装方法。尤其，为了实现布线规则的微细化以应对窄间距化、高速化，并灵活利用已使用了超低电介质材料的半导体元件的电路上的特性以应对高频化，而期望一种利用形成短布线连接的电极上的凸块而进行的倒装芯片安装方式；并且，为了应对半导体元件的上述脆弱化，而要求在低负载下形成凸块，并在低负载下安装。
在这种背景下，提出有一种技术作为在半导体元件的电极上形成用于进行倒装芯片安装的凸块的方法，所述技术根据在半导体或晶片等基材的电极形成面上对感光性树脂层体进行热压接、曝光、及显影，而在感光性树脂层体的电极上形成开口，并根据对暴露在此开口处的电极部进行镀敷来形成凸块(例如，参照专利文献1)。
以下，参照图9(a)、图9(b)来对现有的带凸块半导体元件的制造方法进行说明。
关于带凸块半导体元件的制造，首先，如图9(a)所示，在半导体元件或基板2102的电极形成面上涂布感光性聚酰亚胺树脂2101并使其干燥后，进行掩模曝光、及显影来去除电极衬垫2110上的感光性聚酰亚胺树脂2101的一部分来形成开口部。接着，使感光性聚酰亚胺树脂2101热固化而制成保护膜后，如图9(b)所示，根据镀敷技术而在暴露于开口处的电极衬垫2110上形成凸块2114，获得带凸块半导体元件2120。在这里，镀敷，例如是以下述方式进行：在半导体元件或基板2102的铝制电极衬垫2110上形成钛(Ti)膜等钝化膜后，重复镀铬(Cr)或镍(Ni)及金(Au)，来形成总厚度5～30μm左右的根据镀敷而得到的凸块2114。
在如上所述的现有例子中，为了根据近来的要求以窄间距形成凸块时，形成于保护膜的电极上部的通孔会成为与窄间距相称的小直径通孔，但这种形态的开口也就是所谓的通孔的纵横比较高，形成凸块的镀敷液难以渗入，不易进行更新，因此镀敷速度较慢，镀层的厚度容易不均匀。
而且，由于根据镀敷而得到的凸块是刚性较高的金属凸块，因此凸块本身不能在可以避免破坏脆弱的半导体元件的程度的低负载应力下，充分获得追随变形性，为了在安装倒装芯片时使半导体元件的各凸块追随电路基板的翘曲或隆起而充分进行电性连接，需要在高负载下进行倒装芯片安装，因此，由此还存在这种问题：采用超低电介质材料的近来的脆弱的半导体元件容易破坏，从而导致损坏电极下的主动元件。
为了解决这种问题，在专利文献2中，提出一种带凸块半导体元件，其在电极形成面形成有保护膜，并具有与电极电性连接且突出至保护膜外的凸块，在保护膜形成有从保护膜的表面贯通到电极的通孔，在这个通孔内形成由导电性树脂构成且与电极电性连接的通孔柱，这个通孔柱具有向保护膜的表面外突出的凸块。这种带凸块半导体元件，由于在通孔内具有由应力吸收性优异的导电性树脂构成的通孔柱，因此即便在低负载下，也可以对应电路基板的翘曲或隆起而追随变形。
然而，根据倒装芯片安装，若直接使用将如上所述的具有凸块的半导体元件与基板连接而成的半导体元件安装基板，则半导体的电极部会暴露在空气中，耐湿可靠性明显较低。另外，存在因应力施加到电极连接部分而使连接产生偏差这样的问题。
因此，进行以下方法：连接凸块与电路基板后，从后方填充被称作底部填充材的液状树脂到半导体元件与电路基板的空隙并使其固化以提升接合部分的可靠性，并固定半导体元件与电路基板。
然而，尤其是如同进行倒装芯片安装的半导体元件，通常其电极数较多，从半导体元件的电路设计方面来看，电极会被设置在半导体元件的周边。填充底部填充材时，利用重力与毛细管现象，从这些半导体元件的电极间流入液状树脂，但是若半导体元件与电路基板的间隔变窄为数10μm至500μm左右，则树脂不会充分地遍布半导体元件中央部分，因此，存在容易出现未填充部分，半导体元件的操作变不稳定这样的问题。另外，由于底部填充材的填充取决于重力与毛细管现象，因此较耗费时间。另外，针对半导体元件的电极与电路基板的电性连接，由于电极间隔较窄，因而还存在容易发生导电性树脂和焊料短路这样的问题。
在专利文献3中，提出以下方法以解决这种问题，所述方法是在将半导体元件的凸块电极直接连接到电路基板时，玻璃转移温度低于连接半导体元件的凸块时的温度，并隔着热塑性绝缘粘接膜来实施半导体元件的固定。在专利文献3中，根据使半导体元件的凸块电极嵌入到因加热而软化的绝缘粘接膜，并贯通绝缘粘接膜，来连接电路基板与半导体元件的凸块电极。然而，如果是此方法，绝缘粘接膜的材料可选择性较低，另外，电路基板与半导体元件的粘接也不充分。
现有技术文献
专利文献
专利文献1：日本专利特开2000-357704号公报；
专利文献2：日本专利特开2007-53256号公报；
专利文献3：日本专利特开平10-270497号公报。
发明内容
本发明是鉴于上述情况而完成的，目的在于提供一种半导体装置及半导体装置的制造方法，所述半导体装置的基板彼此或基板与元件的粘接良好，且它们的电性连接也良好。另外，本发明的目的还在于提供一种倒装芯片型半导体装置及倒装芯片型半导体装置的制造方法，所述倒装芯片型半导体装置具有这种半导体装置。
为了实现上述目的，本发明提供一种半导体装置的制造方法，其具备将多个半导体电路层积层而构成的三维积层结构，所述半导体装置的制造方法的特征在于，具有以下步骤：
准备第一基板与第二基板或第二元件，所述第一基板设置有暴露于基板的外部的导电性连接部也就是电极衬垫、或进一步设置有从该电极衬垫突出的由导电性材料构成的导电性插头，所述第二基板或第二元件积层在该第一基板上，且设置有暴露于基板或元件的外部的由导电性材料构成的导电性插头；
在前述第一基板的电极衬垫或导电性插头、及前述第二基板或前述第二元件的导电性插头的至少一个上形成焊球；
利用感光性绝缘层来覆盖前述第一基板的形成有电极衬垫的面、及前述第二基板或前述第二元件的形成有导电性插头的面中的至少一个面；
根据使用掩模的光刻，在前述被感光性绝缘层覆盖的基板或元件中的电极衬垫或导电性插头上形成开口部；
通过前述形成的开口部，并经由前述焊球将前述第二基板或前述第二元件的导电性插头压接接合于前述第一基板的电极衬垫或导电性插头；
根据熔融前述焊球的烘烤，将前述第一基板的电极衬垫或导电性插头与前述第二基板或前述第二元件的导电性插头固接并且电性连接；以及，
利用烘烤将前述感光性绝缘层固化。
如果是这种半导体装置的制造方法，根据预先利用感光性绝缘层来覆盖基板或元件，然后根据光刻在感光性绝缘层形成开口部，可以制造一种半导体装置，所述半导体装置的基板彼此或基板与元件的粘接良好，且它们的电性连接也良好。
另外，优选为同时进行前述压接接合步骤与前述电性连接的步骤。
如此一来，可以进一步减少步骤数，可以提高生产率。
另外，优选为，在前述准备步骤中，根据将具有元件的基板分成小片、或者根据剥离预先暂时粘接在基板上的元件，来准备前述第二元件。
如此一来，作为准备第二元件的方法，可以列举：将具有元件的基板分成小片方法、及剥离预先暂时粘接在基板上的元件的方法。
另外，优选为，将前述感光性绝缘层制成包含以下树脂的有机层，所述树脂为选自含芳香族基硅酮类树脂及含环氧基硅酮树脂中的一种。
由于这种树脂的弹性模量较低，因此包含这种树脂的感光性绝缘层在根据光刻形成图案后的基板粘接中，可以充分吸收基板表面的凹凸，难以产生空隙(孔洞)。
另外，优选为利用化学放大型负型抗蚀剂组合物材料来形成前述感光性绝缘层，所述化学放大型负型抗蚀剂组合物材料含有：
(A)含硅酮骨架高分子化合物，其具有由下述通式(1)表示的重复单元，重均分子量为3000～500000；
式(1)中，R1～R4表示可以相同也可以不同的碳数1～8的一价烃基；m为1～100的整数；a、b、c、d为0或正数，且a、b、c、d不同时为0；其中，a+b+c+d＝1；而且，X为由下述通式(2)表示的有机基团，Y为由下述通式(3)表示的有机基团；
式(2)中，Z为选自
-CH2-中的任一种二价有机基团，n为0或1；R5及R6分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；k为0、1、2中的任一者；
式(3)中，V为选自
-CH2-中的任一种二价有机基团，p为0或1；R7及R8分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；h为0、1、2中的任一者；
(B)交联剂，其选自被甲醛或甲醛-醇改性而成的氨基缩合物及在1分子中平均具有两个以上的羟甲基或烷氧基羟甲基的酚化合物中的一种或两种以上；
(C)光致产酸剂，其被波长190～500 nm的光分解而产生酸；
(D)含环氧基交联剂；以及，
(E)溶剂。
当将这种化学放大型负型抗蚀剂组合物材料用于形成感光性绝缘层时，即便是固化后，也是低弹性模量，因此，积层基板或芯片后，可以缓和因所使用的材料的热膨胀差而产生的应力，另外，这种化学放大型负型抗蚀剂组合物材料由于可以减轻分成小片时所担心的半导体装置的翘曲，因此适合积层或搭载到布线基板上。
另外，优选为，在利用前述感光性绝缘层来进行覆盖的步骤中，根据在前述第一基板的形成有电极衬垫的面、及前述第二基板或前述第二元件的形成有导电性插头的面中的至少一个面上涂布感光性材料后使其干燥，来形成前述感光性绝缘层。
另外，优选为，在利用前述感光性绝缘层来进行覆盖的步骤中，根据在前述第一基板的形成有电极衬垫的面、及前述第二基板或前述第二元件的形成有导电性插头的面中的至少一个面上粘贴光固化性干膜，来形成前述感光性绝缘层，所述光固化性干膜是将感光性材料涂布在支撑膜上后进行干燥而获得。
如此一来，作为形成感光性绝缘层的方法，可以列举：涂布感光性材料的方法、及粘贴光固化性干膜的方法。
本发明更提供一种倒装芯片型半导体装置的制造方法，其特征在于，根据使利用上述本发明的半导体装置的制造方法所制造的半导体装置积层多层，来制造倒装芯片型半导体装置。
如果是这种倒装芯片型半导体装置的制造方法，可以容易地制造倒装芯片型半导体装置。
本发明更提供一种半导体装置，其具备将多个半导体电路层积层而构成的三维积层结构，所述半导体装置的特征在于，具有：
第一基板，其设置有暴露于基板的外部的导电性连接部也就是电极衬垫、或更设置有从该电极衬垫突出的由导电性材料构成的导电性插头；
感光性绝缘层，其积层在该第一基板上，且在前述电极衬垫或前述导电性插头上具有开口部；以及，
第二基板或第二元件，其积层在该感光性绝缘层上，且设置有暴露于基板或元件的外部的由导电性材料构成的导电性插头；
其中，通过前述开口部，前述第二基板或前述第二元件的导电性插头与前述第一基板的电极衬垫或导电性插头经由焊球电性连接，
并且，前述感光性绝缘层是利用化学放大型负型抗蚀剂组合物材料来形成，所述化学放大型负型抗蚀剂组合物材料含有：
(A)含硅酮骨架高分子化合物，其具有由下述通式(1)表示的重复单元，重均分子量为3000～500000；
式(1)中，R1～R4表示可以相同也可以不同的碳数1～8的一价烃基；m为1～100的整数；a、b、c、d为0或正数，且a、b、c、d不同时为0；其中，a+b+c+d＝1；而且，X为由下述通式(2)表示的有机基团，Y为由下述通式(3)表示的有机基团；
式(2)中，Z为选自
-CH2-中的任一种二价有机基团，n为0或1；R5及R6分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；k为0、1、2中的任一者；
式(3)中，V为选自
-CH2-中的任一种二价有机基团，p为0或1；R7及R8分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；h为0、1、2中的任一者；
(B)交联剂，其选自被甲醛或甲醛-醇改性而成的氨基缩合物及在1分子中平均具有两个以上的羟甲基或烷氧基羟甲基的酚化合物中的一种或两种以上；
(C)光致产酸剂，其被波长190～500nm的光分解而产生酸；
(D)含环氧基交联剂；以及，
(E)溶剂。
如果是这种半导体装置，基板彼此或基板与元件的粘接良好，且它们的电性连接也良好。尤其是由于本发明的半导体装置使用感光性绝缘层，所述感光性绝缘层由即便在固化后弹性模量也较低的化学放大型负型抗蚀剂组合物材料形成，因此，在积层基板或芯片后，可以缓和因所使用的材料的热膨胀差而产生的应力，另外，可以减轻分成小片时担心的半导体装置的翘曲，因此适合积层或载置于布线基板上。
本发明更提供一种倒装芯片型半导体装置，其特征在于，积层有多层上述本发明的半导体装置而成。
这种倒装芯片型半导体装置由于积层有多层本发明的半导体装置，因此可靠性较高。
根据本发明的半导体装置及半导体装置的制造方法，可以赋予以下所示的效果。
如果是本发明的半导体装置的制造方法，由于在形成感光性绝缘层时，根据使用旋涂等涂布或光固化性干膜，可以形成感光性绝缘层，因此可以配合连接后的导电性插头的高度来形成感光性绝缘层。
另外，即便电极衬垫或导电性插头在感光性绝缘层形成步骤中被绝缘层覆盖，由于根据利用掩模的光刻来形成图案，可以容易地去除感光性绝缘层的无用部分，因此可以容易地确保电极衬垫、导电性插头的电性连接。
另外，根据配合电极衬垫或导电性插头的大小、设置来进行光刻，可以确保插头间绝缘。
尤其，由于本发明中的由化学放大型负型抗蚀剂组合物材料形成的感光性绝缘层，其构成也就是化学放大型负型抗蚀剂组合物材料在光交联反应及热交联反应中不会产生副反应气体，所述化学放大型负型抗蚀剂组合物材料含有含硅酮骨架高分子化合物，因此在基板贴合用途中不会引起贴合缺陷。
另外，由于本发明中的化学放大型负型抗蚀剂组合物材料在曝光波长范围内具有较高的透明性，因此即便当基板上的感光性绝缘层变厚时，感光性绝缘层本身的光吸收较少，可以在高灵敏度下形成图案。
另外，本发明中的化学放大型负型抗蚀剂组合物材料，由于根据在利用光形成图案后进行250℃以下的低温加热处理，对被用于电子部件或半导体元件、电路基板的基板的密接性、机械特性及电绝缘性优异，作为化学放大型负型抗蚀剂组合物材料的绝缘保护膜的可靠性较高，更可以防止保护膜产生裂纹，因此适合用于形成电路基板、半导体元件、显示元件等各种电气电子部件保护用皮膜。
另外，本发明中的化学放大型负型抗蚀剂组合物材料可以容易地形成作为基板接合材料也优异的皮膜。尤其是从其耐热性、绝缘性及可挠性来看，这种皮膜可以用作含有再布线用途的半导体元件用绝缘膜、多层印刷基板用绝缘膜、贯穿硅基板布线(硅通孔(through silicon via，TSV))的贯穿电极用绝缘膜、覆盖层膜，且由于这种皮膜具有粘接性，因此可以用于具有包含导电性插头的电性连接的基板贴合或者芯片积层步骤的半导体装置制造用途等。因此，具有感光性绝缘层的本发明的半导体装置，可靠性优异，所述感光性绝缘层由这种化学放大型负型抗蚀剂组合物材料形成。
另外，当将本发明中的化学放大型负型抗蚀剂组合物材料用于形成感光性绝缘层时，由于即便固化后它的弹性模量仍较低，因此积层基板或芯片后，可以缓和因所使用的材料的热膨胀差而产生的应力，还可以减轻分成小片时担心的半导体装置的翘曲，因此适合积层和载置于布线基板上。
附图说明
图1是表示本发明的半导体装置的一个示例的剖面概要图。
图2是表示用于说明本发明的半导体装置的制造方法中的准备步骤及形成焊球的步骤的第一基板与第二基板或第二元件的剖面概要图。
图3是用于说明本发明的半导体装置的制造方法中的利用感光性绝缘层来进行覆盖的步骤的第一基板与第二基板或第二元件的剖面概要图。
图4是用于说明本发明的半导体装置的制造方法中的形成开口部的步骤的第一基板与第二基板或第二元件的剖面概要图。
图5是用于说明本发明的半导体装置的制造方法中的压接接合步骤、电性连接步骤及利用烘烤将感光性绝缘层固化的步骤的第一基板与第二基板或第二元件的剖面概要图。
图6是表示具有多个第二元件的本发明的半导体装置的一个示例的剖面概要图。
图7是表示本发明的倒装芯片型半导体装置的一个示例的剖面概要图。
图8是用于说明本发明的半导体装置的制造方法的第一基板与第二基板或第二元件的剖面概要图，所述半导体装置使用了一种导电性插头突出至感光性绝缘层外的第二基板或第二元件。
图9是表示现有的带凸块半导体元件的制造方法的一个示例的图。
其中，附图标记说明如下：
11 电极衬垫；
12 第一基板的导电性插头；
13 第一基板；
14 第二基板或第二元件的导电性插头；
15 第二基板或第二元件；
16 焊球；
17 感光性绝缘层；
18 电极衬垫上的开口部；
19 导电性插头上的开口部；
2101 感光性聚酰亚胺树脂；
2102 半导体元件或基板；
2110 电极衬垫；
2114 凸块；
2120 带凸块半导体元件。
具体实施方式
以下，更详细地说明本发明。
如上所述，对半导体装置进一步小型化、薄型化及高密度化的要求正在快速增加，需要开发一种半导体装置及半导体装置的制造方法，所述半导体装置在半导体元件上形成微细电极，将这些电极直接电性接合，并且确保电极间的绝缘性，且所述半导体装置容易载置于具有充分的粘接性的粘接材料以及布线基板上并容易积层半导体装置。
本发明人进行了潜心研究以实现上述目的。结果发现，在半导体装置的基板的接合部分使用感光性绝缘层，且利用该感光性绝缘层来覆盖基板或元件，具体来说，通过将上述感光性绝缘层旋涂在基板或元件上或者利用在感光性绝缘层中使用抗蚀剂组合物材料等而得到的干膜来进行层压，可以埋入感光性绝缘层，而不会在第一基板与第二基板或第二元件之间产生空隙等，且根据使用掩模的光刻，对形成在基板或元件上的感光性绝缘层进行图案化，由此，即便第一基板与第二基板或第二元件的间隔为数10μm至500μm，也可以形成位于第二基板或第二元件上的导电性插头上的开口与位于第一基板上的电极衬垫或导电性插头上的开口，从而完成了本发明。
以下，参照附图具体地说明本发明的实施方式，但本发明并不限定于这些。
首先，说明本发明的半导体装置。如图1(a)所示，本发明的半导体装置具备将多个半导体电路层积层而构成的三维积层结构，所述半导体装置具有：第一基板(第1半导体基板)13，其设置有暴露于基板的外部的导电性连接部也就是电极衬垫11；感光性绝缘层17，其积层在该第一基板13上，且在电极衬垫11上具有开口部；以及，第二基板(第二半导体基板)或第二元件(第二半导体元件)15，其积层在该感光性绝缘层17上，且设置有暴露于基板或元件的外部的由导电性材料构成的导电性插头14；其中，通过开口部，第二基板或第二元件的导电性插头14与第一基板的电极衬垫11经由焊球(焊料凸块)16电性连接。
如果是这种半导体装置，由于在第一基板与第二基板或第二元件之间形成有感光性绝缘层，因此基板彼此或基板与元件的粘接良好，且它们的电性连接也良好。另外，由于第二基板或第二元件具有导电性插头，因此第二基板或第二元件变得容易对应第一基板的翘曲或隆起而追随变形。
此外，如图1(b)所示，第一基板13也可以具有电极衬垫11、及自该电极衬垫11突出的由导电性材料构成的导电性插头12。此时，第二基板或第二元件的导电性插头14与第一基板的导电性插头12经由焊球16电性连接。此时，可以进一步提高上述第二基板或第二元件的追随变形性。
另外，本发明的半导体装置，也可以如图6所示具有多个第二元件。图6所示的半导体装置具有第一基板13、感光性绝缘层17及多个第二元件15，其中，所述感光性绝缘层17积层在第一基板13上，且在第一基板的电极衬垫11上具有开口部，所述多个第二元件15积层在感光性绝缘层17上，且设置有导电性插头14，通过开口部，第二元件的导电性插头14与第一基板的电极衬垫11经由焊球16电性连接。
在这里，本发明的半导体装置，其感光性绝缘层是利用化学放大型负型抗蚀剂组合物材料来形成，所述化学放大型负型抗蚀剂组合物材料含有：
(A)含硅酮骨架高分子化合物，其具有由下述通式(1)表示的重复单元，重均分子量为3000～500000；
式(1)中，R1～R4表示可以相同也可以不同的碳数1～8的一价烃基；m为1～100的整数；a、b、c、d为0或正数，且a、b、c、d不同时为0；其中，a+b+c+d＝1；而且，X为由下述通式(2)表示的有机基团，Y为由下述通式(3)表示的有机基团；
式(2)中，Z为选自
-CH2-中的任一种二价有机基团，n为0或1；R5及R6分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；k为0、1、2中的任一者；
式(3)中，V为选自
-CH2-中的任一种二价有机基团，p为0或1；R7及R8分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；h为0、1、2中的任一者；
(B)交联剂，其选自被甲醛或甲醛-醇改性而成的氨基缩合物及在1分子中平均具有两个以上的羟甲基或烷氧基羟甲基的酚化合物中的一种或两种以上；
(C)光致产酸剂，其被波长190～500nm的光分解而产生酸；
(D)含环氧基交联剂；以及，
(E)溶剂。
如此一来，本发明的半导体装置，使用由化学放大型负型抗蚀剂组合物材料形成的感光性绝缘层，所述化学放大型负型抗蚀剂组合物材料即便固化后弹性模量也很低，因此在积层基板或芯片后，可以缓和因所使用的材料的热膨胀差而产生的应力，还可以减轻分成小片时担心的半导体装置翘曲，因此适合积层或载置在布线基板上。
另外，本发明提供一种倒装芯片型半导体装置，其特征在于，积层多层上述本发明的半导体装置而成。
这种倒装芯片型半导体装置由于积层有多层本发明的半导体装置，因此可靠性较高。
图7(a)表示积层有两层本发明的半导体装置所得到的倒装芯片型半导体装置。图7(a)表示经由电极衬垫11、焊球16、导电性插头14及感光性绝缘层17积层两个半导体装置的例子。此外，如图7(b)所示，倒装芯片型半导体装置也可以经由电极衬垫11、焊球16及感光性绝缘层17将具有导电性插头14的第二基板或第二元件15积层在本发明的半导体装置上。
以下，对本发明的半导体装置使用的化学放大型负型抗蚀剂组合物材料的各成分进行说明。
(A)成分是含硅酮骨架高分子化合物，其具有由上述通式(1)表示的重复单元，重均分子量为3000～500000。
作为(B)交联剂，可以使用公知的交联剂，可以使用选自被甲醛或甲醛-醇改性而成的氨基缩合物、及1分子中平均具有两个以上的羟甲基或烷氧基羟甲基的酚化合物中的一种或两种以上。
作为这种被甲醛或甲醛-醇改性而成的氨基缩合物，可以列举例如：被甲醛或甲醛-醇改性而成的三聚氰胺缩合物、或被甲醛或甲醛-醇改性而成的脲缩合物。此外，可以使用这些改性三聚氰胺缩合物及改性脲缩合物中的一种或将两种以上混合后使用。
另外，作为在1分子中平均具有两个以上的羟甲基或烷氧基羟甲基的酚化合物，可以列举例如：(2-羟基-5-甲基)-1,3-苯二甲醇、2,2’,6,6’-四甲氧基甲基双酚A等。此外，可以使用这些酚化合物中的一种或将两种以上混合后使用。
作为(C)产酸剂，可以使用一种被照射波长190～500nm的光而产生酸，成为固化催化剂的产酸剂。作为这种光致产酸剂，可以列举：鎓盐、重氮甲烷衍生物、乙二肟衍生物、β-酮砜衍生物、二磺酸衍生物、硝基苄基磺酸盐衍生物、磺酸酯衍生物、酰亚胺-基-磺酸盐衍生物、肟磺酸盐衍生物、亚氨基磺酸盐衍生物、三嗪衍生物等。
作为(D)含环氧基交联剂，并无特别限定，可以含有在1分子中平均具有两个以上的环氧基的环氧化合物。作为上述交联剂，可以列举例如：双酚A型环氧树脂、双酚F型环氧树脂等双酚型环氧树脂；苯酚酚醛清漆型环氧树脂、甲酚酚醛清漆型环氧树脂等酚醛清漆型环氧树脂；三酚烷烃型环氧树脂及三酚烷烃型环氧树脂的聚合物、联苯型环氧树脂、二环戊二烯改性酚醛清漆型环氧树脂、苯酚芳烷基型环氧树脂、联苯芳烷基型环氧树脂、含萘环的环氧树脂、缩水甘油酯型环氧树脂、脂环式环氧树脂、杂环型环氧树脂等。在上述交联剂中，优选使用双酚型环氧树脂及酚醛清漆型环氧树脂。上述交联剂可以单独使用一种或将两种以上混合后使用。
作为(E)溶剂，可以使用一种可以溶解(A)含硅酮骨架高分子化合物、(B)交联剂、(C)光致产酸剂及(D)含环氧基交联剂的溶剂。作为这种溶剂，可以列举例如：环己酮、环戊酮、甲基-2-正戊基酮等酮类；3-甲氧基丁醇、3-甲基-3-甲氧基丁醇、1-甲氧基-2-丙醇、1-乙氧基-2-丙醇等醇类；丙二醇单甲醚、乙二醇单甲醚、丙二醇单乙醚、乙二醇单乙醚、丙二醇二甲醚、二乙二醇二甲醚等醚类；以及，丙二醇单甲醚乙酸酯、丙二醇单乙醚乙酸酯、乳酸乙酯、丙酮酸乙酯、乙酸丁酯、3-甲氧基丙酸甲酯、3-乙氧基丙酸乙酯、乙酸叔丁酯、丙酸叔丁酯、丙二醇-单叔丁基醚乙酸酯、γ-丁内酯等酯类等。
利用通常的方法来制备本发明中的化学放大型负型抗蚀剂组合物材料。将上述各成分搅拌混合，然后根据需要利用过滤器过滤固体成分，由此，可以制备一种可以形成本发明的感光性绝缘层的化学放大型负型抗蚀剂组合物材料。
接着，说明本发明的半导体装置的制造方法。本发明的半导体装置的制造方法是制造半导体装置的方法，所述半导体装置具备积层多个半导体电路层而构成的三维积层结构，所述半导体装置的制造方法具有以下步骤：
准备第一基板与第二基板或第二元件，所述第一基板设置有暴露于基板的外部的导电性连接部也就是电极衬垫、或更设置有从该电极衬垫突出的由导电性材料构成的导电性插头，所述第二基板或第二元件积层在该第一基板上，且设置有暴露于基板或元件的外部的由导电性材料构成的导电性插头；
在前述第一基板的电极衬垫或导电性插头、及前述第二基板或前述第二元件的导电性插头的至少一个上形成焊球；
利用感光性绝缘层来覆盖前述第一基板的形成有电极衬垫的面、及前述第二基板或前述第二元件的形成有导电性插头的面中的至少一个面；
根据使用掩模的光刻，在前述被感光性绝缘层覆盖的基板或元件上的电极衬垫或导电性插头上，形成开口部；
通过前述所形成的开口部，并经由前述焊球将前述第二基板或前述第二元件的导电性插头压接接合于前述第一基板的电极衬垫或导电性插头；
根据熔融前述焊球的烘烤，将前述第一基板的电极衬垫或导电性插头与前述第二基板或前述第二元件的导电性插头固接并且电性连接；以及，
利用烘烤将前述感光性绝缘层固化。
如果是这种半导体装置的制造方法，根据预先利用感光性绝缘层来覆盖基板或元件，然后根据光刻在感光性绝缘层形成开口部，可以制造一种半导体装置，所述半导体装置的基板彼此或基板与元件的粘接良好，且它们的电性连接也良好。
以下，详细说明各步骤。
首先，准备第一基板与第二基板或第二元件，所述第一基板设置有暴露于基板的外部的导电性连接部也就是电极衬垫、或更设置有从该电极衬垫突出的由导电性材料构成的导电性插头，所述第二基板或第二元件积层在该第一基板上，且设置有暴露于基板或元件的外部的由导电性材料构成的导电性插头。此时，当第二基板或第二元件被设置在第一基板的上侧的特定位置时，可以将第二基板或第二元件的导电性插头设计为位于第一基板的电极衬垫或导电性插头。
以下，使用图2来说明本发明的半导体装置的制造方法中的准备步骤及后述的形成焊球的步骤。例如，如图2(a)所示，可以准备一种设置有电极衬垫11的第一基板作为第一基板13。另外，如图2(b)所示，可以准备一种设置有电极衬垫11及导电性插头12的第一基板作为第一基板13。另外，如图2(c)所示，可以准备一种设置有导电性插头14的第二基板或第二元件作为第二基板或第二元件15。图2(c)图示进行形成焊球的步骤，在导电性插头14的前端形成焊球16。
此时优选为，根据将具有元件的基板分成小片、或者根据剥离预先暂时粘接在基板上的元件，来准备第二元件。在本发明中，不仅是第二基板，这种第二元件也可以连接在第一基板上。
作为第一基板、第二基板及第二元件的材料，列举掺杂有硼等掺杂物的硅。
以下，说明第一基板、第二基板及第二元件的制作方法。在这里，以根据将具有元件的基板分成小片来准备第二元件的方法为一个示例进行说明。此时，可以使用导电性基板、或利用溅镀等在表面形成有导电性膜的基板作为具有元件的基板。首先，利用感光性树脂层来覆盖基板的插头形成面。最好使感光性树脂层的厚度比形成的插头高度更厚。在这里，并不特别限制使用的感光性树脂层，但优选为由含有公知的正型抗蚀剂材料(碱溶性树脂)的组合物构成的树脂层。接着，经由光掩模将感光性树脂层曝光，所述光掩模具有将插头形成部曝光的图案，然后喷洒碱性水溶液来显影去除曝光部，获得插头形成部凹陷入凹坑的感光性树脂膜。接着，通过氧(O2)灰化去除凹陷孔底部的残渣，并根据镀敷来形成规定高度的插头。虽然插头形成通常使用镀铜，但只要是导电性材料，就不特别限制。
作为其他导电性材料，可以列举：在硅酮树脂、环氧树脂等树脂中添加有碳粒子、金属粒子等导电性填料所得到的导电性材料。如此一来，如果是除镀敷以外的由导电性材料构成的导电性插头，可以进一步提高追随变形性。
此外，第一基板的电极衬垫也可以根据镀铜等来形成。
根据在形成插头后去除感光性树脂层，可以获得具有导电性插头的基板。此外，可以使用具有导电性插头的基板作为第二基板。
另外，根据切割将利用上述方法得到的基板来分成小片，由此可以获得具有导电性插头的第二元件。
接着，在第一基板的电极衬垫或导电性插头及第二基板或第二元件的导电性插头的至少一个上形成焊球。不论在导电性插头的前端等形成焊球的方法如何，通常是利用搭载焊球等的方法来形成焊球，所述方法在镀敷或填充其他导电性材料来形成导电性插头时，继续进行镀敷。
设置例如熔点为200℃以上的焊料(焊球)，以在第一基板的电极衬垫或导电性插头及第二基板或第二元件的导电性插头的至少一个上取得两基板间的电性连接。构成这个电性粘接部的焊料由例如下述合金构成：铅(Pb)与锡(Sn)的合金、铅与银(Ag)的合金、在铅与锡中添加有锑(Sb)的合金。作为在已形成于第二基板或第二元件的导电性插头前端上、或者第一基板的电极衬垫或导电性插头上形成焊料的方法，并不特别限制，可以利用继上述准备步骤中的根据镀敷来形成插头或形成电极衬垫后，实施镀敷来形成。另外，也可以在插头或电极衬垫与焊料之间插入镍(Ni)层。
此外，当在第二元件上形成焊球时，也可以一并进行准备步骤与形成焊球的步骤。也就是说，也可以根据在具有元件的基板上形成焊球后将基板分成小片、或者根据在预先暂时粘接在基板上的元件上形成焊球后剥离元件，来制作具有焊球的第二元件。
接着，利用感光性绝缘层来覆盖第一基板的形成有电极衬垫的面、及第二基板或第二元件的形成有导电性插头的面中的至少一个面(感光性绝缘层形成面)。形成感光性绝缘层的方法并无特别限定，可以列举：方法一，根据在感光性绝缘层形成面涂布感光性材料后干燥，来形成感光性绝缘层；以及，方法二，根据在感光性绝缘层形成面粘贴光固化性干膜来形成感光性绝缘层，所述光固化性干膜是将感光性材料涂布在支撑膜上后进行干燥而获得。
以下，使用图3对本发明的半导体装置的制造方法中利用感光性绝缘层进行覆盖的步骤作说明。例如，如图3(a)所示，可以利用感光性绝缘层17来覆盖图2(a)的第一基板的形成有电极衬垫11的面。另外，如图3(b)所示，可以利用感光性绝缘层17来覆盖图2(b)的第一基板的形成有电极衬垫11的面，所述第一基板形成有导电性插头。另外，如图3(c)所示，可以利用感光性绝缘层17来覆盖图2(c)的第二基板或第二元件的形成有导电性插头14的面。
在本发明的半导体装置的制造方法中，感光性绝缘层的材料并无特别限定，作为感光性材料，优选为弹性模量较低的材料。更优选为弹性模量为2GPa以下的材料，尤其优选为弹性模量为1GPa以下的材料。具体来说，可以列举包含树脂的材料，所述树脂选自含芳香族基硅酮类树脂及含环氧基硅酮树脂中的一种。其中，作为感光性材料的具体例，优选为重均分子量为3000～500000，含有含硅酮骨架高分子化合物的光固化性树脂组合物，尤其优选为上述化学放大型负型抗蚀剂组合物材料。由此，可以制造一种即便固化后感光性绝缘层仍具有低弹性模量，且翘曲得以减轻的半导体装置。
此外，在本发明的半导体装置的制造方法中，通常可以使用弹性模量超过2GPa的感光性聚酰亚胺树脂来作为感光性绝缘层的材料，但根据使用如上所述的弹性模量低于感光性聚酰亚胺树脂的材料，在利用光刻形成图案后的基板粘接中，可以充分吸收基板表面的凹凸，且不容易产生空隙(孔洞)。根据消除孔洞，基板粘接力提升，可靠性提升。
另外，当在低弹性模量材料处进行基板接合时，可以吸收因基板和封装时使用的材料的热膨胀差而产生的应力，可以防止应力集中在凸块或凸块与感光性绝缘层的界面，因此可以防止在凸块与感光性绝缘层界面处发生剥离、感光性绝缘层产生裂纹，因此封装的可靠性变良好。
作为化学放大型负型抗蚀剂组合物材料的涂布方法，可采用公知的光刻技术进行。可以利用例如浸渍法、旋涂法、辊涂法等方法进行涂布。涂布量可以结合目的适当选择，该涂布量为可以形成膜厚10～500μm、优选为10～50μm的感光性绝缘层的量。也可以在涂布感光性材料前将溶剂滴加到基板上(预湿法)，以提升基板面的膜厚均匀性。滴加的溶剂与量可以结合目的适当选择，用作溶剂的有机溶剂类，优选为例如异丙醇(isopropylalcohol；IPA)等醇类或环己酮等酮类，更优选为丙二醇单甲醚等二醇等，也可以使用感光性材料所使用的溶剂(例如上述的(E)成分)。
在这里，可以根据需要利用预加热(预烘烤(pre-bake，PB))预先使溶剂等挥发，以有效进行光固化反应。预加热例如能以40～140℃进行1分钟～1小时左右。
接着，对根据粘贴光固化性干膜来形成感光性绝缘层的方法进行说明。
将上述感光性材料涂布在支撑膜上后进行干燥而获得本发明中的光固化性干膜。通常，本发明中的光固化性干膜的感光性绝缘层具有被支撑膜和保护膜夹持的结构，所述感光性绝缘层是将上述感光性材料涂布在支撑膜上后进行干燥而获得。
用于本发明的半导体装置的制造方法的光固化性干膜(感光性绝缘干膜)中使用的支撑膜，可以是单层膜，也可以是积层多层聚合物膜所得到的多层膜。作为材质，可以列举聚乙烯、聚丙烯、聚碳酸酯、聚对苯二甲酸乙二酯等合成树脂膜等，优选为具有适度可挠性、机械强度及耐热性的聚对苯二甲酸乙二酯。另外，也可以对这些膜进行电晕处理或涂布剥离剂等各种处理。这些膜可以使用市面上销售的商品，可以列举例如：CERAPEEL WZ(RX)、CERAPEELBX8(R)(以上，东丽薄膜加工股份有限公司(TORAY ADVANCED FILM CO.,LTD)制造)、E7302、E7304(以上，东洋纺织股份有限公司(TOYOBO CO.,LTD.)制造)、Purex G31、Purex G71T1(以上，帝人杜邦薄膜股份有限公司(Teijin DuPont Films Japan Limited)制造)、PET 38X1-A3、PET 38X1-V8、PET 38X1-X08(以上，NIPPA股份有限公司(NippaCorporatin.)制造)等。
用于本发明的半导体装置的制造方法的光固化性干膜中使用的保护膜，可以使用与上述支撑膜相同的保护膜，但优选为具有适度的可挠性的聚对苯二甲酸乙二酯及聚乙烯。这些可以使用市面上销售的商品，作为聚对苯二甲酸乙二酯，可以列举已经例示的聚对苯二甲酸乙二酯，作为聚乙烯，可以列举例如GF-8(TAMAPOLY股份有限公司(TAMAPOLY CO.,LTD.)制造)、聚乙烯(Polyethylene，PE)膜0型(NIPPA股份有限公司(Nippa Corporatin.)制造)。
从光固化性干膜制造的稳定性及防止向卷芯缠卷也就是所谓卷曲的观点来看，上述支撑膜及保护膜的厚度均优选为10～300μm。
接着，对本发明的半导体装置的制造方法所使用的光固化性干膜的制造方法进行说明。上述光固化性干膜的制造装置通常可以使用用于制造粘合剂产品的膜涂布机。作为上述膜涂布机，可以列举例如：逗号涂布机、逗号反向涂布机、多重涂布机、模压涂布机、唇涂布机、唇反向涂布机、直接凹版印刷涂布机、平版印刷涂布机、三辊底部喂料反向涂布机、四辊底部喂料反向涂布机等。
将支撑膜从膜涂布机的卷出轴卷出后使其通过膜涂布机的涂布机头时，以特定厚度在支撑膜上涂布感光性材料形成感光性绝缘层后，以特定温度与特定时间通过热风循环烘箱，将在上述支撑膜上干燥后的感光性绝缘层与从膜涂布机的另一卷出轴卷出的保护膜一起，在特定压力下通过层压辊而与支撑膜上的感光性绝缘层贴合后，卷绕到膜涂布机的卷取轴，由此进行制造。此时，作为热风循环烘箱的温度，优选为25～150℃，作为通过时间，优选为1～100分钟，作为层压辊的压力，优选为0.01～5MPa。
另外，本发明的半导体装置的制造方法中使用的光固化性干膜的感光性绝缘层的膜厚通常为10～500μm，优选为10～300μm，更优选为10～150μm。
可以利用如上所述的方法制作光固化性干膜，通过使用这种光固化性干膜，可以减轻翘曲。
利用光固化性干膜形成感光性绝缘层时，通过层压光固化性干膜的感光性绝缘层，覆盖第一基板的形成有电极衬垫的面及第二基板或第二元件的形成有导电性插头的面的至少一个面，来形成感光性绝缘层。
首先，从上述的光固化性干膜上剥离保护膜，在半导体基板或半导体元件上层压光固化性干膜的感光性绝缘层，形成感光性绝缘层。
作为在半导体基板或半导体元件上贴合光固化性干膜的装置，优选为真空层压机。将光固化性干膜安装在膜贴合装置上，剥离光固化性干膜的保护膜后暴露感光性绝缘层，在特定真空度的真空腔内使用特定压力的贴合辊，在特定温度的工作台上使感光性绝缘层与基板密接。此外，作为工作台的温度，优选为60～120℃，作为贴合辊的压力，优选为0～5.0MPa，作为真空腔的真空度，优选为50～500Pa。如此一来，通过进行真空层压，不会在半导体基板或元件上的电极衬垫及导电性插头周边产生空隙，因此优选。
在这里，也可以根据需要预加热(预烘烤(pre-bake，PB))，以有效地进行感光性绝缘层的光固化反应、或者提升感光性绝缘层与基板或者半导体元件的密接性、或者提升密接的感光性绝缘层的平坦性。预烘烤例如能以40～140℃进行1分钟～1小时左右。
另外，通过根据第一基板与第二基板或第二元件电性接合后的间隙调整感光性绝缘层的涂布厚度或干膜厚度，可以在后述压接接合步骤中，埋入基板间或基板与半导体元件间而不留空隙。
接着，根据使用掩模的光刻，在被感光性绝缘层覆盖的基板或元件中的电极衬垫或导电性插头上形成开口部。也就是说，当感光性绝缘层覆盖第一基板的形成有电极衬垫的面时，根据使用掩模的光刻，在第一基板的电极衬垫或导电性插头上形成开口部。另外，当感光性绝缘层覆盖第二基板或第二元件的形成有导电性插头的面时，根据使用掩模的光刻，在第二基板或第二元件的导电性插头上形成开口部。另外，当感光性绝缘层覆盖第一基板的形成有电极衬垫的面及第二基板或第二元件的形成有导电性插头的面时，根据使用掩模的光刻，在第一基板的电极衬垫或导电性插头上形成开口部，且根据使用掩模的光刻，在第二基板或第二元件的导电性插头上形成开口部。
以下，使用图4对本发明的半导体装置的制造方法中的形成开口部的步骤进行说明。例如，如图4(a)所示，可以根据使用掩模的光刻，在图3(a)的被感光性绝缘层17覆盖的第一基板的电极衬垫11上形成开口部18。另外，如图4(b)所示，可以根据使用掩模的光刻，在图3(b)的被感光性绝缘层17覆盖的第一基板的导电性插头12上形成开口部19。另外，如图4(c)所示，可以根据使用掩模的光刻，在图3(c)的被感光性绝缘层17覆盖的第二基板或第二元件的导电性插头14上形成开口部19。
在形成开口部的步骤中，根据使用掩模的光刻，对感光性绝缘层进行图案化，形成电极衬垫上的开口部与导电性插头上的开口部，所述感光性绝缘层是通过利用感光性绝缘层进行覆盖的步骤形成。开口部取决于所插入的电极衬垫的直径，但最好成型为5～300μm直径的开口。
在这个图案化中，形成感光性绝缘层后进行曝光，进行曝光后加热处理(曝光后烘烤(post exposure bake，PEB))后显影。也就是说，可以使用公知的光刻技术形成图案。
经由光掩模用波长190～500nm的光，将在利用感光性绝缘层覆盖的步骤中形成的感光性绝缘层曝光后使其固化。光掩模也可以例如钻穿所需要的图案。此外，光掩模的材质优选为遮蔽波长190～500nm的光的材质，适合使用例如铬等，但并不限定于此。作为波长190～500nm的光，可以列举例如由放射线产生装置产生的各种波长的光，例如g射线、i射线等紫外线光、远紫外线光(248nm、193nm)等。而且，波长优选为248～436nm。曝光量优选为例如10～3000mJ/cm2。如此一来，通过进行曝光，曝光部分进行交联形成不溶于后述显影液的图案。
更进行PEB以提高显影灵敏度。PEB例如能以40～140℃进行0.5～10分钟。
然后，利用显影液进行显影。作为优选的显影液，可以列举：异丙醇(IsopropylAlcohol，IPA)或丙二醇单甲醚醋酸酯(Propylene Glycol Methyl Ether Acetate，PGMEA)之类的有机溶剂。另外，优选的碱水溶液也就是显影液为2.38％的四甲基氢氧化铵(tetramethylammonium hydroxide，TMAH)水溶液。在本发明的半导体装置的制造方法中，优选使用有机溶剂作为显影液。可以利用通常的方法例如将形成有图案的基板浸渍在显影液中来进行显影。然后，根据需要进行清洗、冲洗、干燥等，获得具有所需图案的感光性绝缘层的皮膜。
接着，在形成开口部的步骤中，通过所形成的开口部，将第二基板或第二元件的导电性插头经由焊球压接接合在第一基板的电极衬垫或导电性插头。根据将第二基板或第二元件压接接合在第一基板的特定位置，并经由前述形成有图案的感光性绝缘层来粘接第一基板与第二基板或第二元件。可以根据利用上述感光性绝缘层来进行覆盖的步骤及形成开口部的步骤，在第一基板与第二基板或第二元件的至少一个上形成具有开口部的感光性绝缘层。因此，在压接接合步骤中，在例如第一基板的上侧设置第二基板或第二元件，并进行热压接，由此可以固定第一基板与第二基板或第二元件和使电极间绝缘。
以下，使用图5，对本发明的半导体装置的制造方法中的压接接合步骤、后述电性连接步骤及后述利用烘烤将感光性绝缘层固化的步骤进行说明。例如，如图5(a)所示，可以通过图4(a)中形成的开口部18，并经由焊球16将图2(c)的第二基板或第二元件的导电性插头14压接接合在图4(a)的第一基板的电极衬垫11上。然后，可以进行电性连接及感光性绝缘层的固化。另外，如图5(b)所示，通过图4(c)中形成的开口部19，并经由焊球16将图4(c)的第二基板或第二元件的导电性插头14压接接合在图2(a)的第一基板的电极衬垫11上。然后，可以进行电性连接及感光性绝缘层的固化。另外，图5(c)所示，可以通过图4(b)中形成的开口部19及图4(c)中形成的开口部19，并经由焊球16将图4(c)的第二基板或第二元件的导电性插头14压接接合在图4(b)的第一基板的导电性插头12上。然后，可以进行电性连接及感光性绝缘层的固化。此外，图5(c)的情况下，第一基板侧的感光性绝缘层17与第二基板或第二元件侧的感光性绝缘层17的材料可以相同也可以不同。
本发明中的上述感光性绝缘层为基板粘接剂，可以用作例如使本发明中的由感光性材料形成皮膜的第一基板与第二基板或第二元件接合的粘接剂，以在热及压力适当的条件下在两个基板间或基板与半导体元件间形成粘接性结合。如上所述，也可以在第二基板或第二元件上形成感光性绝缘层。
作为接合条件，优选设为以50～200℃的加热温度进行1～60分钟。也可以使用晶片粘合装置作为接合装置，施加负载并在减压下贴合晶片彼此、或使用倒装芯片粘合装置进行芯片-晶片接合。形成于基板间的粘接层，由于后述后固化处理而结合力提高，成为永久接合，发挥与底部填充同等的作用。
接着，根据熔融焊球的烘烤，将第一基板的电极衬垫或导电性插头与第二基板或第二元件的导电性插头固接并且电性连接。在这个步骤中，更以凸块连接温度(熔融焊球的温度)，加热经由感光性绝缘层所接合的第一基板与第二基板或第二元件，并进行凸块连接。
连接凸块时的温度，可以根据焊球的种类适当设定，可以设为例如250～270℃。另外，连接凸块时的时间也可以根据焊球的种类适当设定，可以设为例如5秒～1分钟。
连接凸块时，也可以施加压力。当利用压接将第一基板与第二基板或第二元件电性连接时，可以同时进行利用1次压接并经由感光性绝缘层来粘接第一基板与第二基板或第二元件、及电性连接第一基板的电极衬垫或导电性插头与第二基板或第二元件的导电性插头。也就是说，可以同时进行压接接合步骤与电性连接步骤。如此一来，可以进一步削减步骤数，可以提高生产率。另一方面，也可以分两步进行压接接合步骤与电性连接步骤。
如上所述，利用感光性绝缘层来连接第一基板与第二基板或第二元件时，可以利用1次压接同时进行凸块连接与半导体元件的固定，但也可以分两步进行压接。也就是说，这种方法是第一次以低于凸块连接温度的温度进行压接，第二次以凸块连接温度进行压接。
当施加压力来连接凸块时，也可以使用晶片粘合装置作为接合装置，施加负载并且在减压下贴合晶片彼此、或使用倒装芯片粘合装置进行芯片-晶片接合。
此外，当使用倒装芯片粘合装置来进行第一基板与第二基板或第二元件的压接接合时，也可以继经由前述感光性绝缘层来压接接合第一基板与第二基板或第二元件后，进行电性连接步骤。
此外，进行压接接合步骤、电性连接步骤及后述利用烘烤将感光性绝缘层固化的步骤的顺序并无特别限定。例如，在这些步骤中，也可以最初进行利用烘烤将感光性绝缘层固化的步骤。另外，也可以利用一次热处理同时进行这些步骤。
接着，利用烘烤将粘接第一基板与第二基板或第二元件之间的感光性绝缘层固化。使用烘箱或加热板，以100～250℃、优选为150～220℃的温度，将进行过压接接合步骤与电性连接步骤的基板进行后固化。此外，如果后固化温度为100～250℃，可以提高感光性绝缘层的交联密度，并去除残存的挥发成分，从对基板的密接力、耐热性或强度、以及电绝缘性、接合强度的观点来看为优选。进行过贴合(积层)的基板，根据上述后固化处理，树脂皮膜的交联密度增加，可以提高基板粘接力。此外，在本发明中的化学放大型负型抗蚀剂组合物材料的交联反应中，不会发生伴随脱气的副反应，因此尤其是在用作基板粘接剂时，不会引起贴合缺陷(孔洞)。后固化时间可以设为10分钟～10小时，尤其是可以设为10分钟～3小时。
以这样的方式固化后的感光性绝缘固化层会成为永久接合，可以不使用底部填充就固定基板间或基板与芯片(元件)间，可以使导电性插头间绝缘。
另外，所形成的感光性绝缘层的固化后弹性模量优选为0.05～2GPa，尤其优选为0.05～1GPa。如此，根据使用经由弹性模量为2GPa以下的感光性绝缘层的粘接，半导体元件的电极即便密度较高，也容易粘接半导体元件与电路基板，并且可以进行具有高密接性的接合，且可以进行作为电气电子部材的具有高可靠性、绝缘性的连接。
此外，也可以利用切割加工等将形成有感光性绝缘层的基板分成小片(制成芯片)来制作具有感光性绝缘层的第二元件。
此外，如图8所示，在本发明的半导体装置的制造方法中，也可以使用一种导电性插头突出至感光性绝缘层外的第二基板或第二元件。如图8(b)所示，可以使用导电性插头14突出至感光性绝缘层17外的第二基板或第二元件15作为第二基板或第二元件。在图8(b)中，图示在导电性插头14的前端形成有焊球16的第二基板或第二元件。可以如图8(c)所示将图8(b)的第二基板或第二元件15与图8(a)(制作方法与图4(a)相同)的第一基板13压接接合。
一种半导体装置及将这种装置分成小片所得到的半导体元件可以适合用于施加到半导体芯片的扇出布线和晶片级芯片尺寸封装(wafer chip scale package，WCSP)，所述半导体装置的特征在于，具有上述连接部结构，且残存感光性绝缘层作为第一基板与第二基板或第二元件之间的绝缘层。
如以上所述，如果是本发明的半导体装置的制造方法，即便当在半导体元件上形成微细电极时，也可以容易地载置在布线基板上或积层半导体装置，可以容易地进行电极衬垫与导电性插头的电性接合加工。另外，根据使用如上所述的感光性绝缘层，可以减轻翘曲，且不会受到半导体元件的高度、导电性插头的密度的影响，在不使用底部填充的情况下，不仅是半导体元件周边，连在导电性插头周边，也无空隙地埋入感光性绝缘层，因而可以制造确保充分的绝缘性的半导体装置。
而且，由于以这样的方式获得的本发明的半导体装置容易载置在布线基板上且容易积层半导体装置，因此可以制作一种积层了半导体装置所得到的积层型半导体装置(倒装芯片型半导体装置)、和将积层型半导体装置载置在布线基板上后密封所得到的密封后积层型半导体装置。
例如，根据积层多层已利用上述本发明的半导体装置的制造方法制造的半导体装置，可以制造倒装芯片型半导体装置。例如，根据利用与上述本发明的半导体装置的制造方法相同的方法，积层两个半导体装置来代替第一基板与第二基板或第二元件，可以制造如图7(a)所示的倒装芯片型半导体装置。
[实施例]
以下，示出合成例、实施例具体地说明本发明，但本发明并不限制于下述例。
首先，以下显示在本发明的合成例中使用的化合物(M-1)～(M-5)的化学结构式。
[合成例1]
在具备搅拌机、温度计、氮气置换装置及回流冷却器的5L烧瓶内，将化合物(M-1)396.9g、化合物(M-12)45.0g溶解在甲苯1875g后，添加化合物(M-3)949.6g、化合物(M-4)6.1g，并加热至60℃。然后，投入碳担载铂催化剂(5质量％)2.2g，确认内部反应温度升温至65～67℃后，进一步加热3小时至90℃，再冷却至60℃，投入碳担载铂催化剂(5质量％)2.2g，花费一个小时将化合物(M-5)107.3g滴加到烧瓶内。此时烧瓶内温度上升至78℃。滴加结束后，进一步在90℃熟成3小时后冷却至室温，添加甲基异丁基酮1700g，并利用过滤器对本反应溶液进行加压过滤，由此来去除铂催化剂。再向所得到的高分子化合物溶液中添加纯水760g后进行搅拌，进行静置分液，去除下层的水层。重复6次这种分液水洗操作，去除高分子化合物溶液中的微量酸成分。减压馏去这种高分子化合物溶液中的溶剂，并且添加环戊酮950g，获得以固体成分浓度为60质量％的环戊酮为主溶剂的高分子化合物溶液(A-1)。利用凝胶渗透层析法(Gel Permeation Chromatography，GPC)测定这种高分子化合物溶液中高分子化合物的分子量的结果，以聚苯乙烯换算重均分子量为62000，式(1)中的(c+d)/(a+b+c+d)为0.10。
[合成例2]
在具备搅拌机、温度计、氮气置换装置及回流冷却器的5L烧瓶内，将化合物(M-1)441.0g溶解在甲苯1875g后，添加化合物(M-3)949.6g、化合物(M-4)6.1g，并加热至60℃。然后，投入碳担载铂催化剂(5质量％)2.2g，确认内部反应温度升温至65～67℃后，进一步加热3小时至90℃，再冷却至60℃，投入碳担载铂催化剂(5质量％)2.2g，花费1小时向烧瓶内滴加化合物(M-5)107.3g。此时烧瓶内温度上升至78℃。滴加结束后，进一步以90℃熟成5小时后，冷却至室温，添加甲基异丁基酮1700g，并利用过滤器对本反应溶液进行加压过滤，由此来去除铂催化剂。进一步向所得到的高分子化合物溶液中添加纯水760g后进行搅拌，进行静置分液，去除下层的水层。重复进行6次这种分液水洗操作，去除高分子化合物溶液中的微量酸成分。减压馏去这种高分子化合物溶液中的溶剂，并且添加环戊酮950g，获得以固体成分浓度为60质量％的环戊酮为主溶剂的高分子化合物溶液(A-2)。利用GPC测定这种高分子化合物溶液中的高分子化合物的分子量的结果，以聚苯乙烯换算重均分子量为51000，式(1)中的(c+d)/(a+b+c+d)为0。
本发明的调配例中使用的表1中记载的(C)光致产酸剂，如下所述。
另外，本发明的调配例中使用的下述表1中记载的(B)交联剂，如以下所述。
烷基化三聚氰胺树脂、H-1(由三和化学股份有限公司(SANWA CHEMICAL co.,ltd.)制造)
另外，本发明的调配例中使用的下述表1中记载的(D)含环氧基交联剂，如下所述。
而且，按照表1记载的调配量，调配含硅酮骨架高分子化合物((A)成分)、交联剂((B)成分)、光致产酸剂((C)成分)、含环氧基交联剂((D)成分)及溶剂((E)成分)，然后在常温下搅拌、混合、溶解后，利用铁氟龙(注册商标，Teflon)制1.0μm过滤器进行精密过滤，获得调配例1～3的化学放大型负型抗蚀剂组合物材料作为感光性材料。
[表1]
[光固化性干膜的制作]
使用模压涂布机作为薄膜涂布机，并使用聚对苯二甲酸乙二酯膜(厚度38μm)作为支撑膜，将调配例1的感光性材料涂布在上述支撑膜上。接着，费时5分钟，通过设定为100℃的热风循环烘箱(长度4m)，由此在支撑膜上形成感光性绝缘层。感光性绝缘层的膜厚设为100μm。使用聚乙烯膜(厚度50μm)作为保护膜，利用层压辊以1MPa的压力，从上述感光性绝缘层的上面贴合上述保护膜，制作光固化性干膜。此外，调配例2、3的感光性材料也与调配例1的感光性材料同样地制作光固化性干膜。
(实施例1)
使用具有导电性连接部的第一基板与具有导电性插头的第二基板，所述导电性连接部也就是直径20μm、高度4μm的电极衬垫，所述导电性插头突出至基板的外部，直径为15μm，高度为5μm。在这个第二基板的导电性插头的前端镀敷有1μm厚的SnAg。当第二基板的导电性插头设置在第一基板上侧的特定位置时，设计成位于第一基板的电极衬垫处。
使用旋转涂布机，在直径200mm(8英寸)的第一基板上，以膜厚成为9.5μm的方式涂布调配例1的感光性材料溶液。利用加热板以130℃预烘烤2分钟后，经由具有将电极衬垫遮光的设计的石英制掩模进行曝光，以去除溶剂。曝光机使用苏斯微技术公司(SUSSMicroTec Group)制造的接触光刻机型曝光装置。照射后，利用加热板以130℃进行3分钟PEB后冷却。然后，使用2-丙醇对上述涂布后的第一基板进行5分钟喷洒显影，在第一基板上形成光固化性树脂膜(感光性绝缘层)，所述光固化性树脂膜在电极衬垫上具有开口。
将显影后的第一基板与具有导电性插头的第二基板进行定位，并设置成电极衬垫与导电性插头连接，一边加热至160℃一边施加5分钟10kN的力，由此经由光固化性树脂膜来粘接第一基板与第二基板。粘接基板时，使用EV集团(EV Group)制造的晶片粘合机。接着，根据以260℃加热30秒，来熔融插头前端的SnAg，实施导电性插头与电极衬垫的电性连接。进一步在惰性气体下在烘箱中以180℃加热2小时进行最终固化。固化后的第一基板与第二基板的粘接良好，电性连接也良好。
(实施例2)
使用具有导电性连接部的第一基板与具有导电性插头的第二基板，所述导电性连接部也就是直径100μm、高度4μm的电极衬垫，所述导电性插头突出至基板的外部，直径为60μm，高度为40μm。在这个第二基板的导电性插头的前端镀敷有3μm厚的SnAg。当第二基板的导电性插头设置在第一基板上侧的特定位置时，设计成位于第一基板的电极衬垫处。
将使用调配例2的感光性材料制作的树脂厚45μm的光固化性干膜的保护膜剥离，使用真空层压机TEAM-100RF(Takatori公司(Takatori Corporation)制造)将真空腔内设定为真空度80Pa，使支撑膜上的感光性绝缘层与直径200mm的第二基板密接。温度条件设为110℃。恢复到常压后，从真空层压机中取出上述基板后剥离支撑膜。接着，利用加热板以130℃进行5分钟预烘烤以提高与基板的密接性。使用接触光刻机型曝光装置以与上述相同的方式对所得到的感光性绝缘层进行曝光。照射光后，利用加热板以130℃进行5分钟PEB后冷却，对上述基板使用PGMEA进行6次50秒旋覆浸没(puddle)显影，接着，进一步使用IPA进行1分钟喷洒显影，在第二基板上形成光固化性树脂膜(感光性绝缘层)，所述光固化性树脂膜在导电性插头上具有开口。
将第一基板与显影后的第二基板进行定位，并设置成电极衬垫与导电性插头连接，一边加热至160℃一边施加5分钟10kN的力，由此，经由光固化性树脂膜来粘接第一基板与第二基板。粘接基板时，使用EV集团制造的晶片粘合机。接着，根据以260℃加热30秒，来熔融插头前端的SnAg，实施导电性插头与电极衬垫的电性连接。进一步在惰性气体烘箱中以180℃加热2小时进行最终固化。固化后的第一基板与第二基板的粘接良好，电性连接也良好。
(实施例3)
使用具有导电性连接部的第一基板与具有导电性插头的第二基板，所述导电性连接部也就是直径15μm、高度4μm的电极衬垫，所述导电性插头突出至基板的外部，直径为10μm，高度为3μm。在这个第二基板的导电性插头的前端镀敷1μm厚的SnAg。当第二基板的导电性插头设置在第一基板上侧的特定位置时，设计成位于第一基板的电极衬垫处。
使用旋转涂布机，在直径200mm的第一基板上，以膜厚成为7.5μm的方式涂布调配例3的感光性材料溶液。利用加热板以130℃预烘烤2分钟后，经由具有将电极衬垫遮光的设计的石英制掩模进行曝光，以去除溶剂。曝光机使用苏斯微技术公司制接触光刻机型曝光装置。照射后，利用加热板以130℃进行3分钟PEB后冷却。然后，使用2-丙醇对上述涂布后的第一基板进行5分钟喷洒显影，在第一基板上形成光固化性树脂膜(感光性绝缘层)，所述光固化性树脂膜在电极衬垫上具有开口。
将第二元件的形成有导电性插头的面与第一基板上的连接用端子(电极衬垫)定位，同时进行压接接合步骤与电性连接步骤。具体来说，以260℃熔融插头前端的SnAg5秒，并且压接第一基板与第二元件，使电极衬垫与导电性插头连接，接着，将第二元件加热至160℃，并且持续压接15秒后，经由光固化性树脂膜粘接第二元件与第一基板。进一步在惰性气体下在烘箱中以180℃加热2小时进行最终固化。固化后的第一基板与第二元件的粘接良好，电性连接良好。
(实施例4)
在导电性连接部也就是具有直径20μm、高度4μm的电极衬垫的直径200mm的第一基板上，使用旋转涂布机以膜厚成为6μm的方式涂布调配例2的感光性材料溶液。利用加热板以130℃预烘烤2分钟后，经由具有将电极衬垫遮光的设计的石英制掩模进行曝光，以去除溶剂。曝光机使用苏斯微技术公司制造的接触光刻机型曝光装置。照射后，利用加热板以130℃进行3分钟PEB后冷却。然后，使用2-丙醇对上述涂布后的第一基板进行5分钟喷洒显影，在第一基板上形成光固化性树脂膜(感光性绝缘层)，所述光固化性树脂膜在电极衬垫上具有开口。
第二基板是具有直径15μm、高度6.5μm的插头且直径为200mm的基板。在这个第二基板的导电性插头的前端镀敷有1μm厚的SnAg。使用旋转涂布机，在形成插头的第二基板上，以膜厚成为10μm的方式涂布调配例2的感光性材料溶液。利用加热板以130℃预烘烤2分钟后，经由具有将电极衬垫遮光的设计的石英制掩模进行曝光，以去除溶剂。曝光机使用苏斯微技术公司制造的接触光刻机型曝光装置。照射后，利用加热板以130℃进行3分钟PEB后冷却。然后，使用2-丙醇对上述涂布后的第二基板进行5分钟喷洒显影，在第二基板上形成电光固化性树脂膜(感光性绝缘层)，所述光固化性树脂膜在导电性插头上具有开口。
将第一基板与第二基板进行定位，并设置成电极衬垫与导电性插头连接，一边加热至160℃一边施加5分钟10kN的力，经由光固化性树脂膜粘接第一基板与第二基板。粘接基板时，使用EV集团制造的晶片粘合机。接着，根据以260℃加热30秒，来熔融插头前端的SnAg，实施导电性插头与电极衬垫的电性连接。进一步在惰性气体烘箱中以180℃加热2小时进行最终固化。固化后的第一基板与第二基板的粘接良好，电性连接也良好。
此外，本发明并不限定于上述实施方式。上述实施方式为示例，具有与本发明的权利要求书记载的技术思想实质相同的构成，发挥相同作用效果的发明均包含在本发明的技术范围内。

Claims (12)

1.一种半导体装置的制造方法，所述半导体装置具备积层多层半导体电路层而构成的三维积层结构，所述半导体装置的制造方法的特征在于，具有以下步骤：
准备第一基板与第二基板或第二元件，所述第一基板上设置有暴露于基板的外部的导电性连接部也就是电极衬垫、或更设置有从该电极衬垫突出的由导电性材料构成的导电性插头，所述第二基板或第二元件积层在该第一基板上，且设置有暴露于基板或元件的外部的由导电性材料构成的导电性插头；
在前述第一基板的电极衬垫或导电性插头、及前述第二基板或前述第二元件的导电性插头中的至少一个上形成焊球；
利用感光性绝缘层来覆盖前述第一基板的形成有电极衬垫的面、及前述第二基板或前述第二元件的形成有导电性插头的面中的至少一个面；
根据使用掩模的光刻，在前述被感光性绝缘层覆盖的基板或元件中的电极衬垫或导电性插头上形成开口部；
通过前述形成的开口部，并经由前述焊球将前述第二基板或前述第二元件的导电性插头压接接合于前述第一基板的电极衬垫或导电性插头；
根据熔融前述焊球的烘烤，将前述第一基板的电极衬垫或导电性插头与前述第二基板或前述第二元件的导电性插头固接并且电性连接；以及，
利用烘烤将前述感光性绝缘层固化。
2.如权利要求1所述的半导体装置的制造方法，其中，同时进行前述压接接合步骤与前述电性连接步骤。
3.如权利要求1所述的半导体装置的制造方法，其中，在前述准备步骤中，根据将具有元件的基板分成小片、或者根据剥离预先暂时粘接在基板上的元件来准备前述第二元件。
4.如权利要求2所述的半导体装置的制造方法，其中，在前述准备步骤中，根据将具有元件的基板分成小片、或者根据剥离预先暂时粘接在基板上的元件来准备前述第二元件。
5.如权利要求1至4中任一项所述的半导体装置的制造方法，其中，将前述感光性绝缘层制成包含以下树脂的有机层，所述树脂为选自含芳香族基硅酮类树脂及含环氧基硅酮树脂中的一种。
6.如权利要求1至4中任一项所述的半导体装置的制造方法，其中，利用化学放大型负型抗蚀剂组合物材料来形成前述感光性绝缘层，所述化学放大型负型抗蚀剂组合物材料含有：
(A)含硅酮骨架高分子化合物，其具有由下述通式(1)表示的重复单元，重均分子量为3000～500000；
式(1)中，R1～R4表示可以相同也可以不同的碳数1～8的一价烃基；m为1～100的整数；a、b、c、d为0或正数，且a、b、c、d不同时为0；a+b+c+d＝1；而且，X为由下述通式(2)表示的有机基团，Y为由下述通式(3)表示的有机基团；
式(2)中，Z为选自
-CH2-中的任一种二价有机基团，n为0或1；R5及R6分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；k为0、1、2中的任一者；
式(3)中，V为选自
-CH2-中的任一种二价有机基团，p为0或1；R7及R8分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；h为0、1、2中的任一者；
(B)交联剂，其选自被甲醛或甲醛-醇改性而成的氨基缩合物、及在1分子中平均具有两个以上的羟甲基或烷氧基羟甲基的酚化合物中的一种或两种以上；
(C)光致产酸剂，其被波长190～500nm的光分解而产生酸；
(D)含环氧基交联剂；以及，
(E)溶剂。
7.如权利要求5所述的半导体装置的制造方法，其中，利用化学放大型负型抗蚀剂组合物材料来形成前述感光性绝缘层，所述化学放大型负型抗蚀剂组合物材料含有：
(A)含硅酮骨架高分子化合物，其具有由下述通式(1)表示的重复单元，重均分子量为3000～500000；
式(1)中，R1～R4表示可以相同也可以不同的碳数1～8的一价烃基；m为1～100的整数；a、b、c、d为0或正数，且a、b、c、d不同时为0；a+b+c+d＝1；而且，X为由下述通式(2)表示的有机基团，Y为由下述通式(3)表示的有机基团；
式(2)中，Z为选自
-CH2-中的任一种二价有机基团，n为0或1；R5及R6分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；k为0、1、2中的任一者；
式(3)中，V为选自
-CH2-中的任一种二价有机基团，p为0或1；R7及R8分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；h为0、1、2中的任一者；
(B)交联剂，其选自被甲醛或甲醛-醇改性而成的氨基缩合物及在1分子中平均具有两个以上的羟甲基或烷氧基羟甲基的酚化合物中的一种或两种以上；
(C)光致产酸剂，其被波长190～500nm的光分解而产生酸；
(D)含环氧基交联剂；以及，
(E)溶剂。
8.如权利要求1至4中任一项所述的半导体装置的制造方法，其中，在利用前述感光性绝缘层来进行覆盖的步骤中，根据在前述第一基板的形成有电极衬垫的面、及前述第二基板或前述第二元件的形成有导电性插头的面中的至少一个面上涂布感光性材料后干燥，来形成前述感光性绝缘层。
9.如权利要求1至4中任一项所述的半导体装置的制造方法，其中，在利用前述感光性绝缘层来进行覆盖的步骤中，根据在前述第一基板的形成有电极衬垫的面、及前述第二基板或前述第二元件的形成有导电性插头的面中的至少一个面上粘贴光固化性干膜，来形成前述感光性绝缘层，所述光固化性干膜是将感光性材料涂布在支撑膜上后进行干燥而获得。
10.一种倒装芯片型半导体装置的制造方法，其特征在于，根据将利用权利要求1至4中任一项所述的半导体装置的制造方法制造的半导体装置积层为多层，来制造倒装芯片型半导体装置。
11.一种半导体装置，其具备将多个半导体电路层积层而构成的三维积层结构，所述半导体装置的特征在于，具有：
第一基板，其设置有暴露于基板的外部的导电性连接部也就是电极衬垫、或更设置有从该电极衬垫突出的由导电性材料构成的导电性插头；
感光性绝缘层，其积层在该第一基板上，且在前述电极衬垫或前述导电性插头上具有开口部；以及，
第二基板或第二元件，其积层在该感光性绝缘层上，且设置有暴露于基板或元件的外部的由导电性材料构成的导电性插头；
其中，通过前述开口部，前述第二基板或前述第二元件的导电性插头与前述第一基板的电极衬垫或导电性插头经由焊球电性连接，
并且，前述感光性绝缘层是利用化学放大型负型抗蚀剂组合物材料来形成，所述化学放大型负型抗蚀剂组合物材料含有：
(A)含硅酮骨架高分子化合物，其具有由下述通式(1)表示的重复单元，重均分子量为3000～500000；
式(1)中，R1～R4表示可以相同也可以不同的碳数1～8的一价烃基；m为1～100的整数；a、b、c、d为0或正数，且a、b、c、d不同时为0；a+b+c+d＝1；而且，X为由下述通式(2)表示的有机基团，Y为由下述通式(3)表示的有机基团；
式(2)中，Z为选自
-CH2-中的任一种二价有机基团，n为0或1；R5及R6分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；k为0、1、2中的任一者；
式(3)中，V为选自
-CH2-中的任一种二价有机基团，p为0或1；R7及R8分别为碳数1～4的烷基或烷氧基，可以相互不同也可以相同；h为0、1、2中的任一者；
(B)交联剂，其选自被甲醛或甲醛-醇改性而成的氨基缩合物及在1分子中平均具有两个以上的羟甲基或烷氧基羟甲基的酚化合物中的一种或两种以上；
(C)光致产酸剂，其被波长190～500nm的光分解而产生酸；
(D)含环氧基交联剂；以及，
(E)溶剂。
12.一种倒装芯片型半导体装置，其特征在于，将权利要求11所述的半导体装置积层多层而成。
CN201710107328.7A 2016-02-26 2017-02-27 半导体装置及其制造方法、倒装芯片型半导体装置及其制造方法 Active CN107134414B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-035304 2016-02-26
JP2016035304A JP6534948B2 (ja) 2016-02-26 2016-02-26 半導体装置の製造方法、フリップチップ型半導体装置の製造方法、半導体装置及びフリップチップ型半導体装置

Publications (2)

Publication Number Publication Date
CN107134414A true CN107134414A (zh) 2017-09-05
CN107134414B CN107134414B (zh) 2021-10-22

Family

ID=58162416

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710107328.7A Active CN107134414B (zh) 2016-02-26 2017-02-27 半导体装置及其制造方法、倒装芯片型半导体装置及其制造方法

Country Status (6)

Country Link
US (1) US10416557B2 (zh)
EP (1) EP3211661A3 (zh)
JP (1) JP6534948B2 (zh)
KR (1) KR102560487B1 (zh)
CN (1) CN107134414B (zh)
TW (1) TWI715734B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6866802B2 (ja) 2017-08-09 2021-04-28 信越化学工業株式会社 シリコーン骨格含有高分子化合物、感光性樹脂組成物、感光性樹脂皮膜、感光性ドライフィルム、積層体、及びパターン形成方法
JP6874584B2 (ja) * 2017-08-09 2021-05-19 信越化学工業株式会社 感光性樹脂組成物、感光性樹脂皮膜、感光性ドライフィルム、積層体、及びパターン形成方法
JP6787286B2 (ja) * 2017-09-20 2020-11-18 株式会社村田製作所 インダクタ部品の製造方法
JP7062943B2 (ja) * 2017-12-22 2022-05-09 住友ベークライト株式会社 感光性接着剤組成物および構造体
JP6870657B2 (ja) 2018-05-17 2021-05-12 信越化学工業株式会社 感光性樹脂組成物、感光性ドライフィルム、及びパターン形成方法
US11548985B2 (en) 2018-11-28 2023-01-10 Shin-Etsu Chemical Co., Ltd. Siloxane polymer containing isocyanuric acid and polyether skeletons, photosensitive resin composition, pattern forming process, and fabrication of opto-semiconductor device
JP7056541B2 (ja) 2018-12-19 2022-04-19 信越化学工業株式会社 感光性樹脂組成物、感光性ドライフィルム及びパターン形成方法
KR102227212B1 (ko) * 2019-06-24 2021-03-12 안상정 반도체 발광소자용 지지 기판을 제조하는 방법
CN111564414B (zh) * 2019-12-12 2021-09-24 奥特斯(中国)有限公司 部件承载件及制造部件承载件的方法
JP7348857B2 (ja) * 2020-02-14 2023-09-21 信越化学工業株式会社 半導体装置の製造方法
JP7371566B2 (ja) * 2020-04-24 2023-10-31 信越化学工業株式会社 感光性樹脂組成物、感光性樹脂皮膜、感光性ドライフィルム及びパターン形成方法
JP7371565B2 (ja) * 2020-04-24 2023-10-31 信越化学工業株式会社 感光性樹脂組成物、感光性樹脂皮膜、感光性ドライフィルム及びパターン形成方法
US11348901B1 (en) 2020-11-30 2022-05-31 Sandisk Technologies Llc Interfacial tilt-resistant bonded assembly and methods for forming the same
IT202100014198A1 (it) * 2021-05-31 2022-12-01 St Microelectronics Srl Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08160605A (ja) * 1994-12-09 1996-06-21 Shin Etsu Chem Co Ltd ポジ型レジスト材料
US6210856B1 (en) * 1999-01-27 2001-04-03 International Business Machines Corporation Resist composition and process of forming a patterned resist layer on a substrate
JP2004063770A (ja) * 2002-07-29 2004-02-26 Fujitsu Ltd 電極間接続構造体の形成方法
JP2006143835A (ja) * 2004-11-18 2006-06-08 Hitachi Chem Co Ltd 放射線硬化性樹脂組成物、これを用いた光導波路、及び光導路の製造方法
US20090218702A1 (en) * 2005-06-08 2009-09-03 Interuniversitair Microelektronica Centrum Vzw (Imec) Methods for bonding and micro-electronic devices produced according to such methods
TW201241090A (en) * 2010-10-13 2012-10-16 Shinetsu Chemical Co Photo-curable resin composition, dry film thereof, pattern formation method and film for protecting electric/electronic component
US20130299986A1 (en) * 2012-05-14 2013-11-14 Micron Technology, Inc. Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages
US20140220483A1 (en) * 2013-02-01 2014-08-07 Shin-Etsu Chemical Co., Ltd. Photo-curable resin composition, photo-curable dry film, patterning process, protective film, and electric/electronic part

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2305754A (en) * 1941-03-04 1942-12-22 Bancroft & Sons Co J Display rack
JPH10270497A (ja) 1997-03-27 1998-10-09 Sumitomo Bakelite Co Ltd 半導体素子固定方法
JP2000357704A (ja) 1999-04-16 2000-12-26 Asahi Chem Ind Co Ltd バンプ形成方法
US6707153B2 (en) 2000-03-23 2004-03-16 Seiko Epson Corporation Semiconductor chip with plural resin layers on a surface thereof and method of manufacturing same
KR100994818B1 (ko) 2002-03-04 2010-11-16 롬 앤드 하스 일렉트로닉 머트어리얼즈, 엘.엘.씨 단파장 이미지화용 네거티브 포토레지스트
US20050026667A1 (en) * 2003-07-10 2005-02-03 Moody Ernest W. Video poker with continuous play
TWI230989B (en) * 2004-05-05 2005-04-11 Megic Corp Chip bonding method
US20060068521A1 (en) 2004-09-29 2006-03-30 Song-Hua Shi Method of fabricating microelectronic package using no-flow underfill technology and microelectronic package formed according to the method
JP2007053256A (ja) 2005-08-18 2007-03-01 Matsushita Electric Ind Co Ltd バンプ付き半導体素子とこれを回路基板に実装した半導体デバイス、これらの製造方法
JP5413340B2 (ja) 2009-09-30 2014-02-12 信越化学工業株式会社 エポキシ基含有高分子化合物、これを用いた光硬化性樹脂組成物、パターン形成方法及び電気・電子部品保護用皮膜
JP5459196B2 (ja) 2009-12-15 2014-04-02 信越化学工業株式会社 光硬化性ドライフィルム、その製造方法、パターン形成方法及び電気・電子部品保護用皮膜
JP5630451B2 (ja) 2011-02-23 2014-11-26 信越化学工業株式会社 接着剤組成物及び接着性ドライフィルム
JP5846060B2 (ja) 2011-07-27 2016-01-20 信越化学工業株式会社 ウエハ加工体、ウエハ加工用部材、ウエハ加工用仮接着材、及び薄型ウエハの製造方法
JP5975528B2 (ja) 2012-10-11 2016-08-23 信越化学工業株式会社 ウエハ加工体、ウエハ加工用部材、ウエハ加工用仮接着材、及び薄型ウエハの製造方法
US9704824B2 (en) * 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
JP6224509B2 (ja) 2013-05-14 2017-11-01 信越化学工業株式会社 ウエハ用仮接着材料、それらを用いた仮接着用フィルム、及びウエハ加工体並びにそれらを使用した薄型ウエハの製造方法
JP2015026638A (ja) * 2013-07-24 2015-02-05 マイクロン テクノロジー， インク． 半導体チップ、半導体チップの接合方法及び半導体装置の製造方法
JP6031059B2 (ja) 2014-03-31 2016-11-24 信越化学工業株式会社 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法
JP6031060B2 (ja) 2014-03-31 2016-11-24 信越化学工業株式会社 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法
JP6115514B2 (ja) * 2014-05-01 2017-04-19 信越化学工業株式会社 ネガ型レジスト材料及びパターン形成方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08160605A (ja) * 1994-12-09 1996-06-21 Shin Etsu Chem Co Ltd ポジ型レジスト材料
US6210856B1 (en) * 1999-01-27 2001-04-03 International Business Machines Corporation Resist composition and process of forming a patterned resist layer on a substrate
JP2004063770A (ja) * 2002-07-29 2004-02-26 Fujitsu Ltd 電極間接続構造体の形成方法
JP2006143835A (ja) * 2004-11-18 2006-06-08 Hitachi Chem Co Ltd 放射線硬化性樹脂組成物、これを用いた光導波路、及び光導路の製造方法
US20090218702A1 (en) * 2005-06-08 2009-09-03 Interuniversitair Microelektronica Centrum Vzw (Imec) Methods for bonding and micro-electronic devices produced according to such methods
TW201241090A (en) * 2010-10-13 2012-10-16 Shinetsu Chemical Co Photo-curable resin composition, dry film thereof, pattern formation method and film for protecting electric/electronic component
US20130299986A1 (en) * 2012-05-14 2013-11-14 Micron Technology, Inc. Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages
US20140220483A1 (en) * 2013-02-01 2014-08-07 Shin-Etsu Chemical Co., Ltd. Photo-curable resin composition, photo-curable dry film, patterning process, protective film, and electric/electronic part

Also Published As

Publication number Publication date
TW201742216A (zh) 2017-12-01
CN107134414B (zh) 2021-10-22
JP2017152602A (ja) 2017-08-31
EP3211661A2 (en) 2017-08-30
KR102560487B1 (ko) 2023-07-28
JP6534948B2 (ja) 2019-06-26
KR20170101131A (ko) 2017-09-05
US20170250162A1 (en) 2017-08-31
EP3211661A3 (en) 2017-09-13
US10416557B2 (en) 2019-09-17
TWI715734B (zh) 2021-01-11

Similar Documents

Publication Publication Date Title
CN107134414A (zh) 半导体装置及其制造方法、倒装芯片型半导体装置及其制造方法
JP6571585B2 (ja) 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法
CN106415823B (zh) 半导体装置、积层型半导体装置、密封后积层型半导体装置以及这些装置的制造方法
TWI502659B (zh) 電子裝置之製造方法及電子裝置封裝之製造方法
CN106165086B (zh) 半导体装置、积层型半导体装置、密封后积层型半导体装置以及这些装置的制造方法
JP2003500832A (ja) 高密度電子パッケージ及びその製造方法
TW201019451A (en) Interconnect structure
JP6377894B2 (ja) 半導体装置の製造方法、積層型半導体装置の製造方法、及び封止後積層型半導体装置の製造方法
JP6468017B2 (ja) 半導体装置の製造方法
JP2016090667A (ja) ポジ型感光性樹脂組成物、接着シート、接着剤パターン、接着剤層付半導体ウェハ及び半導体装置
JP7348857B2 (ja) 半導体装置の製造方法
JP2014143308A (ja) 仮固定用組成物及び半導体装置の製造方法
JP2016139754A (ja) 半導体装置の製造方法
JP6291094B2 (ja) 積層型半導体装置、及び封止後積層型半導体装置
JP2015215453A (ja) ネガ型感光性樹脂組成物、接着シート、接着剤パターン、接着剤層付半導体ウェハ及び半導体装置
JP6511830B2 (ja) 半導体装置の製造方法
JP2018151475A (ja) 電子装置の製造方法
JP2021128300A (ja) 感光性樹脂組成物、および半導体装置の製造方法
TW201139599A (en) Method for forming an adhesive layer and adhesive composition
JP2003179047A (ja) 半導体装置の製造方法および半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant