CN107045882A - 能够快速写入数据的存储电路 - Google Patents
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Abstract
本发明公开了一种能够快速写入数据的存储电路。所述存储电路包含多个存储区块,且所述多个存储区块中的每一存储区块包含多个存储区段。所述多个存储区段中的每一存储区段对应多组位线,且所述多组位线中的每一组位线对应一预充电线。当一预定信号启用时,一电平通过所述预充电线和所述每一组位线写入所述每一存储区段内对应所述每一组位线的存储单元。因此,本发明适用于需要快速地写入所述数据至所述每一存储区段的存储单元的应用。
Description
技术领域
本发明涉及一种存储电路,尤其涉及一种能够快速写入数据的存储电路。
背景技术
如图1所示,当耦接于存储电路的一应用单元(未绘示于图1)欲写入数据至所述存储电路的一存储区块B1内的一存储区段MS1的存储单元MC1-MCM时,所述存储电路的控制器(未绘示于图1)先启用对应存储区块B1的地址和一字符线WL1的激活(active)指令ACT。然后在所述控制器启用激活指令ACT后,对应字符线WL1的一字符开关即可根据激活指令ACT开启。在所述控制器启用激活指令ACT后,所述控制器接着启用对应存储区块B1的地址和存储区段MS1的地址的一写入指令WRC。然后在所述控制器启用写入指令WRC后,对应存储区段MS1的位线BL1-BLM的位开关即可根据写入指令WRC开启。因此,在对应位线BL1-BLM的位开关开启后,所述数据即可依序通过所述存储电路的数据线(未绘示于图1)、位线BL1-BLM和一读出放大器SA写入存储单元MC1-MCM。另外,如图1所示,符号WL2-WLN也代表字符线,MS2也代表存储区段,M、N为大于1的正整数,以及读出放大器SA是共享于所述存储电路的所有存储区块。
如图2所示,因为对应存储区段MS1的位线BL1-BLM的位开关是根据写入指令WRC开启,所以在激活指令ACT之后,写入指令WRC必须包含M个使对应位线BL1-BLM的位开关开启的时钟信号,其中在写入指令WRC之后,所述控制器会启用对应存储区块B1的地址的一预充电指令PREC,其中图2是说明所述控制器所产生的激活指令ACT、写入指令WRC和预充电指令PREC的时序。
如图2所示,因为写入指令WRC包含M个使对应位线BL1-BLM的位开关开启的时钟信号,所以写入所述数据至存储单元MC1-MCM的时间至少包含M个时钟信号的时间和激活指令ACT的时间,也就是说写入所述数据至存储单元MC1-MCM将耗费太多的时间。
发明内容
本发明的一实施例公开一种能够快速写入数据的存储电路。所述存储电路包含多个存储区块,其中所述多个存储区块中的每一存储区块包含多个存储区段。所述多个存储区段中的每一存储区段包含多组位线,所述多组位线中的每一组位线对应一预充电线,以及当一预定信号启用时,一电平通过所述预充电线和所述每一组位线写入所述每一存储区段内对应所述每一组位线的存储单元。
本发明的另一实施例公开一种能够快速写入数据的存储电路。所述存储电路包含多个存储区块和一接收器,所述多个存储区块中的每一存储区块包含多个存储区段,且所述多个存储区段中的每一存储区段包含多组位线。所述接收器用于从所述存储电路外接收一数据所对应的多个电平,且当一预定信号启用时,对应地输入所述多个电平中的每一电平至所述多组位线中的一组位线,其中在所述每一电平输入至所述组位线后,所述每一电平通过所述组位线写入所述每一存储区段内对应所述组位线的存储单元。
本发明的另一实施例公开一种能够快速写入数据的存储电路。所述存储电路包含多个存储区块,其中所述多个存储区块中的每一存储区块包含多个存储区段。所述多个存储区段中的每一存储区段包含多组位线,所述多组位线中的每一组位线耦接一预充电线,以及当一预定信号启用时,不同的预充电线接收相同或不同的电平。
本发明的另一实施例公开一种能够快速写入数据的存储电路。所述存储电路包含多个存储区块和一接收器,其中所述多个存储区块中的每一存储区块包含多个存储区段,且所述多个存储区段中的每一存储区段包含多组位线。所述接收器用于从所述存储电路外接收一数据所对应的多个电平,且当一预定信号启用时,所述接收器接收所述多个电平,并对应地输入所述多个电平中的每一电平至所述多组位线中的一组位线,使所述数据所对应的所述多个电平一次性地被写入至所述多组位线对应的所述每一存储区段内的存储单元。
本发明的另一实施例公开一种能够快速写入数据的存储电路。所述存储电路包含多个存储区块和一控制器。所述多个存储区块中的每一存储区块包含多个存储区段,所述多个存储区段中一第一存储区段包含多组位线与多条字符线,所述多条字符线中一第一字符线对应的所有存储单元分成多组存储单元。所述控制器用于接收一组控制信号。当所述存储电路的一预定信号启用时,所述控制器依据所述组控制信号,一次性地对所述第一字符线对应的多组存储单元进行写入动作,其中同一组存储单元被写入的数据相同,不同组存储单元被写入的数据可相同或不同。
本发明的另一实施例公开一种能够快速写入数据的存储电路。所述存储电路包含多个存储区块、一缓存器和一控制器。所述多个存储区块中每一存储区块包含多个存储区段,所述多个存储区段中一第一存储区段包含多组位线与多条字符线,所述多条字符线中一第一字符线对应的所有存储单元分成多组存储单元。所述缓存器用于储存一组控制信号。所述控制器依据一被启用的预定信号与所述组控制信号,一次性地对所述第一字符线对应的多组存储单元进行写入动作。
本发明所公开一种能够快速写入数据的存储电路。所述存储电路是当多个均衡器根据一预定信号开启时利用多条预充电线快速地写入数据至所述存储电路的一存储区段内的存储单元。如此,因为在一激活指令之后,写入所述数据至所述存储区段的存储单元的时间仅包含所述预定信号的时间和所述激活指令的时间,所以相较于现有技术,写入所述数据至所述存储区段的存储单元的时间将大幅缩短。因此,本发明适用于需要快速地写入所述数据至所述存储区段的存储单元的应用。
附图说明
图1是说明所述存储电路的存储区块内的存储区段的存储单元、字符线、位线和读出放大器的示意图。
图2是说明现有技术所公开的激活指令、写入指令和预充电指令的时序示意图。
图3是本发明的一第一实施例所公开的一种能够快速写入数据的存储电路的均衡器、所述存储电路的存储区块内的存储区段的位线和译码器的示意图。
图4是说明激活指令、预定信号和预充电指令的时序示意图。
图5是本发明的一第二实施例所公开的一种能够快速写入数据的存储电路的均衡器、所述存储电路的一存储区块内的一存储区段的位线和接收器的示意图。
图6是本发明的一第三实施例所公开的一种能够快速写入数据至存储电路的操作方法的流程图。
其中,附图标记说明如下:
300 译码器
302-306 晶体管
500 接收器
ACT 激活指令
B1 存储区块
BL1-BLM 位线
DC 数据码
DA 数据
EQ1-EQM 均衡器
EQBL 预定信号
MC1-MCM 存储单元
MS1、MS2 存储区段
PREC 预充电指令
SA 读出放大器
VBL1-VBL4 预充电线
WL1-WLN 字符线
WRC 写入指令
600-610 步骤
具体实施方式
请参照图3,图3是本发明的一第一实施例所公开的一种能够快速写入数据的存储电路的均衡器EQ1-EQM、所述存储电路的一存储区块内的一存储区段的位线BL1-BLM和一译码器300的示意图,其中所述存储电路包含多个存储区块,所述多个存储区块中的每一存储区块包含多个存储区段,M为大于1的正整数,位线BL1-BLM被分成4组位线,所述4组位线中的每一组位线包含至少一条位线,所述4组位线所包含的位线数目可相同或不同,且所述存储电路是一动态随机存取存储器(Dynamic random access memory,DRAM)。但本发明并不受限于位线BL1-BLM被分成4组位线,也就是说位线BL1-BLM可分成多组位线。如图3所示,位线BL1-BLM-3对应一预充电线VBL1、位线BL2-BLM-2对应一预充电线VBL2、位线BL3-BLM-1对应一预充电线VBL3以及位线BL4-BLM对应一预充电线VBL4,其中位线BL1通过均衡器EQ1耦接于预充电线VBL1、位线BL2通过均衡器EQ2耦接于预充电线VBL2、位线BL3通过均衡器EQ3耦接于预充电线VBL3以及位线BL4通过均衡器EQ4耦接于预充电线VBL4等。如图3所示,译码器300耦接于预充电线VBL1-VBL4,用于根据一数据码DC,产生对应数据码DC的4个电平,以及将所述4个电平对应地输入预充电线VBL1-VBL4,其中数据码DC为一4位的二进制代码。例如,当数据码DC为“0001”时,译码器300根据数据码DC“0001”,产生对应数据码DC“0001”的4个电平(逻辑低电平“L”、逻辑低电平“L”、逻辑低电平“L”、逻辑高电平“H”),以及将所述4个电平(逻辑低电平“L”、逻辑低电平“L”、逻辑低电平“L”、逻辑高电平“H”)对应地输入预充电线VBL1-VBL4,其中数据码DC与对应数据码DC的4个电平的关系可参见表一,以及本发明并不受限于表一所示的关系。另外,本发明也不受限于数据码DC为一4位的二进制代码。
表一
如图3所示,当一预定信号EQBL启用时,均衡器EQ1内的晶体管302-306会根据预定信号EQBL开启。因此,当数据码DC为“0001”时,逻辑低电平“L”可快速地通过预充电线VBL1和位线BL1-BLM-3写入所述存储区段内对应位线BL1-BLM-3的存储单元,逻辑低电平“L”可快速地通过预充电线VBL2和位线BL2-BLM-2写入所述存储区段内对应位线BL2-BLM-2的存储单元,逻辑低电平“L”可快速地通过预充电线VBL3和位线BL3-BLM-1写入所述存储区段内对应位线BL3-BLM-1的存储单元,以及逻辑高电平“H”可快速地通过预充电线VBL4和位线BL4-BLM写入所述存储区段内对应位线BL4-BLM的存储单元。另外,均衡器EQ2-EQM的电路架构和操作原理都和均衡器EQ1的电路架构和操作原理相同,在此不再赘述。
另外,如图4所示,因为在一激活指令ACT之后,所述存储电路仅根据预定信号EQBL即可将数据(也就是说逻辑低电平“L”或逻辑高电平“H”)快速地写入所述存储区段内的存储单元,所以写入所述数据至所述存储区段内的存储单元的时间至少包含预定信号EQBL的时间和激活指令ACT的时间,也就是说写入所述数据至所述存储区段内的存储单元的时间将大幅缩短(如图4所示)。因此,本发明适用于需要快速地写入所述数据至所述存储区段内的存储单元的应用,例如需要快速地测试所述存储区段内的存储单元是否正常运作的应用。另外,图4是说明所述存储电路内的一控制器所产生的激活指令ACT、预定信号EQBL和一预充电指令PREC的时序。
另外,当所述数据通过预充电线VBL1-VBL4和位线BL1-BLM写入所述存储区段内的存储单元后,且当预充电信号PREC启用时,一预充电电平可通过预充电线VBL1-VBL4和位线BL1-BLM写入所述存储区段内的存储单元,其中所述预充电电平介于逻辑低电平“L”和逻辑高电平“H”之间。
另外,请参照图5,图5是本发明的一第二实施例所公开的一种能够快速写入数据的存储电路的均衡器EQ1-EQM、所述存储电路的一存储区块内的一存储区段的位线BL1-BLM和一接收器500的示意图。如图5所示,因为所述存储电路并不包含译码器300,所以由接收器500直接从所述存储电路外接收一数据DA所对应的4个电平(例如4个逻辑低电平“L”或逻辑高电平“H”),且当预定信号EQBL启用时,一次性地对应地通过一预充电线输入所述4个电平中的每一电平至所述4组位线中的一组位线,其中所述4个电平可相同或不同。另外,如图5所示,每一组位线(例如位线BL1-BLM-3)中的每一位线(例如位线BL1)通过一对应的均衡器(例如均衡器EQ1)耦接于接收器500,且当预定信号EQBL启用时,预定信号EQBL开启所述对应的均衡器。
另外,当数据DA通过图5所示的接收器500和位线BL1-BLM写入所述存储区段内的存储单元后,且当预充电信号PREC启用时,所述预充电电平可通过接收器500和位线BL1-BLM一次性地写入所述存储区段内的存储单元。另外,图5所示的所述存储电路的其余操作原理都和图3所示的所述存储电路的操作原理相同,在此不再赘述。
另外,在本发明的另一实施例中,数据不仅可通过上述图3或图5的方式写入所述存储区段内的存储单元,也可通过图2的现有技术所公开的方式写入所述存储区段内的存储单元。另外,均衡器EQ1-EQM可共享于图3或图5的所述存储电路的多个存储区块的存储区段。
另外,在本发明的另一实施例中,所述存储电路的控制器可取代接收器500,也就是说所述存储电路的控制器不仅可产生如图4所示的激活指令ACT、预定信号EQBL和预充电指令PREC,也可直接从所述存储电路外接收数据DA所对应的4个电平(也就是说一组控制信号)。但在本发明的另一实施例中,所述存储电路所包含的另一控制器取代接收器500,且由所述另一控制器直接从所述存储电路外接收数据DA所对应的4个电平(也就是说所述组控制信号)。然而,在本发明的另一实施例中,数据DA所对应的4个电平(也就是说所述组控制信号)是储存在所述存储电路另包含的一缓存器(例如所述存储电路内的模式缓存器(moderegister)或扩展缓存器(extended register))内,以及所述存储电路的控制器由所述缓存器接收数据DA所对应的4个电平(也就是说所述组控制信号)。然后,所述控制器依据数据DA所对应的4个电平(也就是说所述组控制信号),一次性地对一存储区段内的一字符线对应的多组存储单元(所述多组存储单元中的每一组存储单元可对应如图5所示的所述4组位线中的一组位线)进行写入动作,其中所述每一组存储单元被写入的数据相同,不同组存储单元被写入的数据可相同或不同。
另外,请参照图3、4、6,图6是本发明的一第三实施例所公开的一种能够快速写入数据至存储电路的操作方法的流程图。图6的方法是利用图3的均衡器EQ1-EQM、所述存储区段的位线BL1-BLM和译码器300说明,详细步骤如下:
步骤600:开始;
步骤602:译码器300根据数据码DC,产生对应数据码DC的4个电平;
步骤604:译码器300对应地输入对应数据码DC的4个电平至预充电线VBL-VBL4;
步骤606:当预定信号EQBL启用时,对应数据码DC的4个电平中的每一电平通过预充电线VBL-VBL4中的一对应的预充电线写入所述存储区段内的对应的位线;
步骤608:所述每一电平通过所述对应的位线写入所述存储区段内对应所述对应的位线的存储单元;
步骤610:结束。
在步骤602和步骤604中,如图3所示,译码器300用于根据数据码DC,产生对应数据码DC的4个电平,以及将所述4个电平对应地输入预充电线VBL1-VBL4。例如,当数据码DC为“0001”时,译码器300根据数据码DC“0001”,产生对应数据码DC“0001”的4个电平(逻辑低电平“L”、逻辑低电平“L”、逻辑低电平“L”、逻辑高电平“H”),以及将所述4个电平(逻辑低电平“L”、逻辑低电平“L”、逻辑低电平“L”、逻辑高电平“H”)对应地输入预充电线VBL1-VBL4,其中数据码DC与对应数据码DC的4个电平的关系可参见表一。
在步骤606和步骤608中,如图3所示,当预定信号EQBL启用时,均衡器EQ1内的晶体管302-306会根据预定信号EQBL开启。因此,当数据码DC为“0001”时,逻辑低电平“L”可快速地通过预充电线VBL1和位线BL1-BLM-3写入所述存储区段内对应位线BL1-BLM-3的存储单元,逻辑低电平“L”可快速地通过预充电线VBL2和位线BL2-BLM-2写入所述存储区段内对应位线BL2-BLM-2的存储单元,逻辑低电平“L”可快速地通过预充电线VBL3和位线BL3-BLM-1写入所述存储区段内对应位线BL3-BLM-1的存储单元,以及逻辑高电平“H”可快速地通过预充电线VBL4和位线BL4-BLM写入所述存储区段内对应位线BL4-BLM的存储单元。
另外,如图4所示,因为在激活指令ACT之后,所述存储电路仅根据预定信号EQBL即可将所述数据(也就是说逻辑低电平“L”或逻辑高电平“H”)快速地写入所述存储区段内对应位线BL1-BLM的存储单元,所以写入所述数据至所述存储区段内对应位线BL1-BLM的存储单元的时间至少包含预定信号EQBL的时间和激活指令ACT的时间,也就是说写入所述数据至所述存储区段内对应位线BL1-BLM的存储单元的时间将大幅缩短(如图4所示)。
另外,在所述数据通过预充电线VBL1-VBL4和位线BL1-BLM写入所述存储区段内对应位线BL1-BLM的存储单元后,且当预充电信号PREC启用时,所述预充电电平可通过预充电线VBL1-VBL4和位线BL1-BLM写入所述存储区段内对应位线BL1-BLM的存储单元,其中所述预充电电平介于逻辑低电平“L”和逻辑高电平“H”之间。
综上所述,本发明所公开的存储电路是当所述均衡器根据所述预定信号开启时利用所述预充电线快速地写入所述数据至所述存储区段内的存储单元。如此,因为在所述激活指令之后,写入所述数据至所述存储区段的存储单元的时间仅包含所述预定信号的时间和所述激活指令的时间,所以相较于现有技术,写入所述数据至所述存储区段的存储单元的时间将大幅缩短。因此,本发明适用于需要快速地写入所述数据至所述存储区段的存储单元的应用。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (17)
1.一种能够快速写入数据的存储电路,包含:
多个存储区块,其中所述多个存储区块中的每一存储区块包含多个存储区段;
其特征在于还包含:
所述多个存储区段中的每一存储区段包含多组位线,所述多组位线中的每一组位线对应一预充电线,以及当一预定信号启用时,一电平通过所述预充电线和所述每一组位线写入所述每一存储区段内对应所述每一组位线的存储单元。
2.如权利要求1所述的存储电路,其特征在于还包含:
一译码器,耦接于所述多组位线所对应的多条预充电线,用于根据一数据码,产生对应所述数据码的多个电平,以及将所述多个电平对应地输入所述多条预充电线。
3.如权利要求2所述的存储电路,其特征在于:所述数据码为一二进制代码。
4.如权利要求1所述的存储电路,其特征在于:所述每一组位线包含至少一条位线。
5.如权利要求1所述的存储电路,其特征在于:所述每一组位线中的每一位线通过一对应的均衡器耦接于所述预充电线,且当所述预定信号启用时,所述预定信号通过所述预充电线开启所述对应的均衡器。
6.如权利要求1所述的存储电路,其特征在于:所述电平通过所述预充电线和所述每一组位线写入所述每一存储区段内对应所述每一组位线的存储单元后,且当一预充电信号启用时,一预充电电平通过所述预充电线和所述每一组位线写入所述每一存储区段内对应所述每一组位线的存储单元。
7.如权利要求1所述的存储电路,其特征在于:所述电平是一逻辑高电平或一逻辑低电平。
8.一种能够快速写入数据的存储电路,其特征在于包含:
多个存储区块,其中所述多个存储区块中的每一存储区块包含多个存储区段,且所述多个存储区段中的每一存储区段包含多组位线;及
一接收器,用于从所述存储电路外接收一数据所对应的多个电平,且当一预定信号启用时,对应地输入所述多个电平中的每一电平至所述多组位线中的一组位线,其中在所述每一电平输入至所述组位线后,所述每一电平通过所述组位线写入所述每一存储区段内对应所述组位线的存储单元。
9.如权利要求8所述的存储电路,其特征在于:所述组位线中的每一位线通过一对应的均衡器耦接于所述接收器,且当所述预定信号启用时,所述预定信号开启所述对应的均衡器。
10.如权利要求8所述的存储电路,其特征在于:所述组位线包含至少一条位线。
11.如权利要求8所述的存储电路,其特征在于:所述所述每一电平通过所述接收器和所述组位线写入所述每一存储区段内对应所述组位线的存储单元后,且当一预充电信号启用时,所述接收器接收一预充电电平,且所述预充电电平通过所述接收器和所述组位线写入所述每一存储区段内对应所述组位线的存储单元。
12.如权利要求8所述的存储电路,其特征在于:所述每一电平是一逻辑高电平或一逻辑低电平。
13.一种能够快速写入数据的存储电路,包含:
多个存储区块,其中所述多个存储区块中的每一存储区块包含多个存储区段;
其特征在于还包含:
所述多个存储区段中的每一存储区段包含多组位线,所述多组位线中的每一组位线耦接一预充电线,以及当一预定信号启用时,不同的预充电线接收相同或不同的电平。
14.如权利要求13所述的存储电路,其特征在于:所述每一组位线写入所述预充电线所接收的电平至所述每一存储区段内对应所述每一组位线的存储单元。
15.一种能够快速写入数据的存储电路,其特征在于包含:
多个存储区块,其中所述多个存储区块中的每一存储区块包含多个存储区段,且所述多个存储区段中的每一存储区段包含多组位线;以及
一接收器,用于从所述存储电路外接收一数据所对应的多个电平,且当一预定信号启用时,所述接收器接收所述多个电平,并对应地输入所述多个电平中的每一电平至所述多组位线中的一组位线,使所述数据所对应的所述多个电平一次性地被写入至所述多组位线对应的所述每一存储区段内的存储单元。
16.一种能够快速写入数据的存储电路,其特征在于包含:
多个存储区块,每一存储区块包含多个存储区段,所述多个存储区段中一第一存储区段包含多组位线与多条字符线,所述多条字符线中一第一字符线对应的所有存储单元分成多组存储单元;以及
一控制器,用于接收一组控制信号;
其中当所述存储电路的一预定信号启用时,所述控制器依据所述组控制信号,一次性地对所述第一字符线对应的多组存储单元进行写入动作,其中同一组存储单元被写入的数据相同,不同组存储单元被写入的数据可相同或不同。
17.一种能够快速写入数据的存储电路,其特征在于包含:
多个存储区块,每一存储区块包含多个存储区段,所述多个存储区段中一第一存储区段包含多组位线与多条字符线,所述多条字符线中一第一字符线对应的所有存储单元分成多组存储单元;
一缓存器,用于储存一组控制信号;以及
一控制器,依据一被启用的预定信号与所述组控制信号,一次性地对所述第一字符线对应的多组存储单元进行写入动作。
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CN114155896B (zh) * | 2020-09-04 | 2024-03-29 | 长鑫存储技术有限公司 | 半导体装置 |
KR20220133003A (ko) * | 2021-03-24 | 2022-10-04 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 그것의 동작 방법 |
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US20170147211A1 (en) | 2017-05-25 |
TWI648737B (zh) | 2019-01-21 |
TW201719646A (zh) | 2017-06-01 |
TW201732805A (zh) | 2017-09-16 |
TWI619122B (zh) | 2018-03-21 |
US10255965B2 (en) | 2019-04-09 |
CN107045882B (zh) | 2021-05-18 |
US20170148500A1 (en) | 2017-05-25 |
US10387047B2 (en) | 2019-08-20 |
CN107017012B (zh) | 2020-12-01 |
CN107017012A (zh) | 2017-08-04 |
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