CN107017012B - 能够快速写入/读取数据的存储电路 - Google Patents

能够快速写入/读取数据的存储电路 Download PDF

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CN107017012B
CN107017012B CN201611022734.5A CN201611022734A CN107017012B CN 107017012 B CN107017012 B CN 107017012B CN 201611022734 A CN201611022734 A CN 201611022734A CN 107017012 B CN107017012 B CN 107017012B
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memory
memory cells
data
word line
controller
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CN107017012A (zh
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夏浚
张正男
宋玉惠
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Etron Technology Inc
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Abstract

本发明公开了一种能够快速写入/读取数据的存储电路。所述存储电路包含多个存储区块和一控制器，所述多个存储区块中的每一存储区块包含多个存储区段，且所述多个存储区段中的每一存储区段包含多条位线和多条字符线。当所述控制器启用对应一存储区段的一字符线的激活指令后，对应所述字符线的字符开关开启且数据依序写入所述存储区段内耦接于所述存储区段的多条位线且对应所述字符线的存储单元；当所述控制器启用至少一复制列写入指令时，所述数据被同时写入与所述存储区段的多条位线共享多个读出放大器且对应至少一其他字符线的存储单元。如此，本发明可缩短所述数据被写入对应所述至少一其他字符线的存储单元的时间。

Description

能够快速写入/读取数据的存储电路
技术领域
本发明涉及一种存储电路，尤其涉及一种能够快速写入/读取数据的存储电路。
背景技术
当耦接于存储电路的一应用单元欲写入数据至对应所述存储电路的一存储区块的一存储区段内一字符线WL1的存储单元时，所述存储电路的控制器会先启用对应字符线WL1的激活(active)指令ACTWL1(如图1所示)。然后在所述控制器启用激活指令ACTWL1后，对应字符线WL1的一字符开关即可根据激活指令ACTWL1开启。在所述控制器启用激活指令ACTWL1后，所述控制器接着启用一写入指令WRC。然后在所述控制器启用写入指令WRC后，所述存储区段内对应字符线WL1的存储单元的位开关即可根据写入指令WRC开启，其中所述位开关的数量为M，且M为大于1的整数。因此，在所述位开关开启后，所述数据即可依序写入对应字符线WL1的存储单元。
如图1所示，因为所述位开关是根据写入指令WRC开启，所以在激活指令ACT之后，写入指令WRC必须包含M个使所述位开关开启的时钟信号，其中写入所述数据至对应字符线WL1的存储单元的时间至少包含M个时钟信号的时间和激活指令ACTWL1的时间。另外，在写入指令WRC之后，所述控制器会启用对应字符线WL1的地址的一预充电指令PREC，且对应字符线WL1的字符开关即可根据预充电指令PREC关闭。
如图1所示，如果所述应用单元欲写入所述数据至对应所述存储区段内一字符线WLM的存储单元，则上述写入所述数据至对应字符线WL1的存储单元的步骤必须再重复一次，也就是说虽然所述应用单元是写入同样数据(所述数据)至对应字符线WLM的存储单元，但写入所述同样数据(所述数据)至对应字符线WLM的存储单元还是必须要花至少包含M个时钟信号的时间和激活指令ACTWLM的时间，其中图1是说明所述控制器所启用的激活指令ACTWL1、ACTWLM、写入指令WRC和预充电指令PREC的时序。因此，对于所述存储电路而言，现有技术并不是一个好的操作方案。
发明内容
本发明的一实施例公开一种能够快速写入数据的存储电路。所述存储电路包含多个存储区块和一控制器，所述多个存储区块中的每一存储区块包含多个存储区段，且所述多个存储区段中的每一存储区段包含多条位线和多条字符线。在所述数据依序写入一存储区段内耦接于所述存储区段内的多条位线且对应所述存储区段内的一字符线的存储单元后且当所述控制器启用至少一复制列(copy row)写入指令时，所述数据被同时写入与所述存储区段的多条位线共享多个读出放大器且对应至少一其他字符线的存储单元，其中所述至少一其他字符线对应所述至少一复制列写入指令。
本发明的另一实施例公开一种能够快速读取数据的存储电路。所述存储电路包含多个存储区块和一控制器，所述多个存储区块中的每一存储区块包含多个存储区段，且所述多个存储区段中的每一存储区段包含多条位线和多条字符线。在所述数据依序写入一存储区段内耦接于所述存储区段内的多条位线且对应所述存储区段内的一字符线的存储单元后，所述控制器控制对应所述字符线的字符开关关闭，当所述控制器启用对应所述字符线的激活指令时，对应所述字符线的字符开关开启，所述数据被读取至耦接所述存储区段的多条位线的多个读出放大器，以及所述多个读出放大器同时将所述数据写入与所述存储区段的多条位线共享所述多个读出放大器且对应至少一其他字符线的存储单元。
本发明的另一实施例公开一种能够快速写入数据的存储电路。所述存储电路包含多个存储单元和一控制器。所述多个存储单元共同耦接至一读出放大器，以及所述控制器耦接所述多个存储单元。当所述控制器欲写入相同的一数据至所述多个存储单元中的一第一组存储单元以及至少一第二组存储单元时，所述控制器利用所述读出放大器直接复制被写入所述第一组存储单元的数据至所述至少一第二组存储单元。
本发明的另一实施例公开一种能够快速读取数据的存储电路。所述存储电路包含多个存储单元和一控制器。所述多个存储单元共同耦接至一读出放大器，以及所述控制器耦接所述多个存储单元。当所述控制器欲写入所述多个存储单元中的一第一组存储单元储存的数据至所述多个存储单元中的至少一第二组存储单元时，所述控制器控制所述第一组存储单元重新电连接所述读出放大器，以及利用所述读出放大器直接复制所述数据至所述至少一第二组存储单元。
本发明的另一实施例公开一种能够快速写入数据的存储电路。所述存储电路包含一命令译码器、多组存储单元和一控制器。所述命令译码器用于接收一组命令控制信号并产生一译码命令。所述多组存储单元共同耦接至一读出放大电路，其中所述读出放大电路包含多个读出放大器。所述控制器用于接收所述译码命令，并依据所述译码命令选择性地将所述多组存储单元中的一第一组存储单元储存的数据一次性地复制至所述多组存储单元中的一第二组存储单元。
本发明公开一种能够快速写入/读取数据的存储电路。所述存储电路是根据所述存储电路内多条位线共享一读出放大器的特征，将原来写入耦接于一存储区段内的位线且对应所述存储区段内的一字符线的存储单元的数据同时写入与所述存储区段内的位线共享多个读出放大器且对应至少一其他字符线的存储单元。如此，相较于现有技术，本发明可大幅缩短所述数据被写入对应所述至少一其他字符线的存储单元的时间。
附图说明
图1是说明现有技术所公开的激活指令、写入指令和预充电指令的时序示意图。
图2是本发明的一第一实施例所公开的一种存储电路的一存储区块内的存储区段的示意图。
图3是本发明的一第二实施例所公开的一种能够快速写入数据的存储电路的操作方法的流程图。
图4是说明激活指令、写入指令、复制列写入指令和预充电指令的时序示意图。
图5是本发明的一第三实施例所公开的一种存储电路的一存储区块内的存储区段的示意图。
图6是本发明的一第四实施例所公开的一种能够快速读取数据的存储电路的操作方法的流程图。
图7是说明激活指令、写入指令、复制列写入指令和预充电指令的时序示意图。
其中，附图标记说明如下：
200 控制器
ACTWL1、ACTWLM、ACTWL11 激活指令
B1、B2 存储区块
BL11-BL1M、BL21-BL2M 位线
CRWRC(WL1N)、CRWRC(WL12)、 复制列写入指令
CRWRC(WL21)
MS1、MS2 存储区段
PREC 预充电指令
MC111、MC11M、MC1N1、MC1NM、 存储单元
MC211、MC21M、MC2N1、MC2NM
SA11-SA1M、SA21-SA2M、 读出放大器
SA31-SA3M
WRC 写入指令
WL11-WL1N、WL21-WL2N 字符线
300-310、600-616 步骤
具体实施方式
请参照图2，图2是本发明的一第一实施例所公开的一种存储电路的一存储区块B1内的存储区段MS1、MS2的示意图，其中所述存储电路包含多个存储区块和一控制器200，BL11-BL1M是存储区段MS1的位线，WL11-WL1N是存储区段MS1的字符线，MC111、MC11M、MC1N1、MC1NM是存储区段MS1的存储单元，BL21-BL2M是存储区段MS2的位线，WL21-WL2N是存储区段MS2的字符线，MC211、MC21M、MC2N1、MC2NM是存储区段MS2的存储单元，SA11-SA1M、SA21-SA2M、SA31-SA3M是所述存储电路的读出放大器，每两条位线共享一读出放大器(例如存储区段MS1的位线BL11和存储区段MS2的位线BL21共享读出放大器SA21，以及存储区段MS1的位线BL13和存储区段MS2的位线BL23共享读出放大器SA23等)，所述存储电路是一动态随机存取存储器(Dynamic random access memory,DRAM)，以及N、M是大于1的整数。但本发明并不受限于两条位线共享一读出放大器，也就是说在本发明的另一实施例中，多条位线共享一读出放大器。
请参照图2-4，图3是本发明的一第二实施例所公开的一种能够快速写入数据至存储电路的操作方法的流程图。图3的操作方法是利用图2的存储区段MS1、MS2和读出放大器SA11-SA1M、SA21-SA2M说明，详细步骤如下：
步骤300：开始；
步骤302：控制器200启用对应存储区段MS1的字符线WL11的激活指令ACTWL11；
步骤304：对应字符线WL11的字符开关开启且一数据依序写入存储区段MS1内耦接于存储区段MS1内的位线BL11-BL1M且对应字符线WL11的存储单元MC111-MC11M；
步骤306：在所述数据依序写入存储单元MC111-MC11M后，控制器200是否启用至少一复制列(copy row)写入指令；如果是，进行步骤308；如果否，进行步骤310；
步骤308：所述数据被同时写入与位线BL11-BL1M共享多个读出放大器SA21、SA12、SA23、…、SA2M且对应至少一其他字符线的存储单元，跳回步骤306；
步骤310：控制器200启用对应字符线WL11的地址的预充电指令PREC。
在步骤304中，如图2、4所示，控制器200启用激活指令ACTWL11后，对应字符线WL11的字符开关(未绘示于图2)即可根据激活指令ACTWL11开启。在控制器200启用激活指令ACTWL11后，控制器200接着启用一写入指令WRC。然后在控制器200启用写入指令WRC后，存储区段MS1内对应字符线WL11的存储单元MC111-MC11M的位开关即可根据写入指令WRC开启。在存储区段MS1内对应字符线WL11的存储单元MC111-MC11M的位开关开启后，所述数据即可依序通过读出放大器SA21、SA12、SA23、…、SA2M写入存储单元MC111-MC11M。在步骤306中，因为存储区段MS1内对应字符线WL1N的存储单元MC1N1-MC1NM和位线BL11-BL1M共享读出放大器SA21、SA12、SA23、…、SA2M，所以如果所述数据还要被写入存储区段MS1内对应字符线WL1N的存储单元MC1N1-MC1NM，则控制器200可启用对应字符线WL1N的复制列写入指令CRWRC(WL1N)，其中因为对应字符线WL11的字符开关尚未关闭，所以读出放大器SA21、SA12、SA23、…、SA2M可栓锁住所述数据，且复制列写入指令CRWRC(WL1N)可用于开启对应字符线WL1N的字符开关。在步骤308中，因为对应字符线WL11的字符开关尚未关闭且复制列写入指令CRWRC(WL1N)开启对应字符线WL1N的字符开关，所以所述数据即可通过读出放大器SA21、SA12、SA23、…、SA2M同时写入存储区段MS1内对应字符线WL1N的存储单元MC1N1-MC1NM。如图4所示，因为所述数据是通过读出放大器SA21、SA12、SA23、…、SA2M同时写入存储区段MS1内对应字符线WL1N的存储单元MC1N1-MC1NM，所以所述数据写入存储区段MS1内对应字符线WL1N的存储单元MC1N1-MC1NM的时间是等于复制列写入指令CRWRC(WL1N)的时间。如图4所示，因为写入指令WRC包含M个使对应存储单元MC111-MC11M的位开关开启的时钟信号，所以所述数据写入存储单元MC1N1-MC1NM的时间是小于所述数据写入存储单元MC111-MC11M的时间。
同理，如果所述数据还要被写入存储区段MS1内对应字符线WL12的存储单元，则控制器200可启用对应字符线WL12的复制列写入指令CRWRC(WL12)；然后因为对应字符线WL11的字符开关尚未关闭且复制列写入指令CRWRC(WL12)开启对应字符线WL12的字符开关，所以所述数据即可通过读出放大器SA21、SA12、SA23、…、SA2M同时写入存储区段MS1内对应字符线WL12的存储单元。
另外，如图4所示，在步骤310中，如果所述数据不用再被写入存储区段MS1内对应其他字符线的存储单元，则在复制列写入指令CRWRC(WL12)之后，控制器200会启用对应字符线WL11的地址的预充电指令PREC，以及对应字符线WL11的字符开关会根据预充电指令PREC关闭。另外，图4是说明控制器200所启用的激活指令ACTWL11、写入指令WRC、复制列写入指令CRWRC(WL1N)、CRWRC(WL12)和预充电指令PREC的时序。
另外，在本发明的另一实施例中，控制器200耦接所述存储电路的存储单元。因此，如图2所示，因为对应字符线WL11的字符开关尚未关闭，所以控制器200可通过启用对应字符线WL12的复制列写入指令CRWRC(WL12)和对应字符线WL1N的复制列写入指令CRWRC(WL1N)，将储存在存储单元MC111的数据通过位线BL11和读出放大器SA21直接写入至存储区段MS1内耦接位线BL11且对应字符线WL12的存储单元和存储区段MS1内耦接位线BL11且对应字符线WL1N的存储单元，其中复制列写入指令CRWRC(WL1N)可开启对应字符线WL1N的字符开关，复制列写入指令CRWRC(WL12)可开启对应字符线WL12的字符开关，以及存储区段MS1内的存储单元MC111-MC1N1是通过位线BL11耦接于读出放大器SA21。
另外，在本发明的另一实施例中，控制器200耦接所述存储电路的存储单元，其中所述存储电路的存储单元中的多个存储单元(例如图2所示的存储单元MC111-MC1N1)共同耦接至一读出放大器(例如读出放大器SA21)，所述多个存储单元至少包含一第一组存储单元以及至少一第二组存储单元(例如将存储单元MC111-MC1N1区分成所述第一组存储单元以及所述至少一第二组存储单元)，且所述第一组存储单元的存储单元数目以及所述至少一第二组存储单元的存储单元数目可相同或不同。因此，当控制器200写入一数据至所述第一组存储单元后，控制器200可利用上述方式和所述读出放大器(例如读出放大器SA21)直接复制被写入所述第一组存储单元的数据至所述至少一第二组存储单元。
另外，在本发明的另一实施例中，当控制器200写入所述数据至所述第一组存储单元后，控制器200可控制所述第一组存储单元重新电连接所述读出放大器(例如读出放大器SA21)，以及利用所述读出放大器(例如读出放大器SA21)直接复制被写入所述第一组存储单元的数据至所述至少一第二组存储单元。
另外，在本发明的另一实施例中，所述存储电路包含一命令译码器(未绘示于图2)、多组存储单元和一控制器。所述命令译码器用于接收一组命令控制信号并产生一译码命令。所述多组存储单元(例如图2所示的存储单元MC111-MC11M和存储单元MC1N1-MC1NM)共同耦接至一读出放大电路，其中所述读出放大电路包含多个读出放大器(例如图2所示的读出放大器SA21、SA12、SA23、…、SA2M)；控制器200用于接收所述译码命令(例如复制列写入指令CRWRC(WL1N))，并依据所述译码命令选择性地将所述多组存储单元中的一第一组存储单元(例如图2所示的存储单元MC111-MC11M)储存的数据一次性地复制至所述多组存储单元中的一第二组存储单元(例如图2所示的存储单元MC1N1-MC1NM)。
请参照图5，图5是本发明的一第三实施例所公开的一种能够快速写入数据的存储电路的一存储区块B2内的存储区段MS1、MS2的示意图，其中如图5所示，每两条位线共享一读出放大器(例如存储区段MS1的位线BL11和存储区段MS2的位线BL21共享读出放大器SA21，以及存储区段MS1的位线BL12和存储区段MS2的位线BL22共享读出放大器SA22等)。因此，在所述数据依序通过读出放大器SA21、SA22、SA23、…、SA2M写入存储区段MS1内对应字符线WL11的存储单元MC111-MC11M后，因为对应存储区段MS2内字符线WL21的存储单元MC211-MC21M和位线BL11-BL1M共享读出放大器SA21、SA22、SA23、…、SA2M，所以如果所述数据还要被写入存储区段MS2内对应字符线WL21的存储单元MC211-MC21M，则控制器200可启用对应字符线WL21的复制列写入指令CRWRC(WL21)，其中因为对应字符线WL11的字符开关尚未关闭，所以读出放大器SA21、SA22、SA23、…、SA2M可栓锁住所述数据。因此，因为对应字符线WL11的字符开关尚未关闭且复制列写入指令CRWRC(WL21)开启对应字符线WL21的字符开关，所以所述数据即可通过读出放大器SA21、SA22、SA23、…、SA2M同时写入存储区段MS2内对应字符线WL21的存储单元MC211-MC21M，其中所述数据写入存储单元MC211-MC21M的时间是小于所述数据写入存储单元MC111-MC11M的时间。
请参照图2、6、7，图6是本发明的一第四实施例所公开的一种能够快速读取存储电路的数据的操作方法的流程图。图6的操作方法是利用图2的存储区段MS1、MS2和读出放大器SA11-SA1M、SA21-SA2M说明，详细步骤如下：
步骤600：开始；
步骤602：控制器200启用对应存储区段MS1的字符线WL11的激活指令ACTWL11；
步骤604：对应字符线WL11的字符开关开启且所述数据依序写入存储区段MS1内耦接于存储区段MS1内的位线BL11-BL1M且对应字符线WL11的存储单元MC111-MC11M；
步骤606：控制器200启用对应字符线WL11的地址的预充电指令PREC；步骤608：是否控制器200再次启用激活指令ACTWL11；如果是，进行步骤610；如果否，进行步骤616；
步骤610：所述数据被读取至耦接存储区段MS1内的位线BL11-BL1M的多个读出放大器SA21、SA12、SA23、…、SA2M；
步骤612：耦接存储区段MS1内的位线BL11-BL1M的多个读出放大器SA21、SA12、SA23、…、SA2M同时将所述数据写入与存储区段MS1内的位线BL11-BL1M共享多个读出放大器SA21、SA12、SA23、…、SA2M且对应至少一其他字符线的存储单元；
步骤614：控制器200启用对应字符线WL11的地址的预充电指令PREC；
步骤616：结束。
第四实施例和第二实施例的差别在于在步骤606中，如果所述数据暂时不用被写入存储区段MS1内对应其他字符线的存储单元时，则控制器200在所述数据依序写入存储单元MC111-MC11M后会启用对应字符线WL11的地址的预充电指令PREC(如图7所示)，以及对应字符线WL11的字符开关会根据预充电指令PREC关闭。在步骤610中，如果在对应字符线WL11的字符开关关闭后，所述数据要再被写入存储区段MS1内对应字符线WL1N的存储单元MC1N1-MC1NM，则控制器200可再次启用对应字符线WL11的激活指令ACTWL11，导致对应字符线WL11的字符开关再次开启。因为对应字符线WL11的字符开关再次开启，所以所述数据被读取至耦接存储区段MS1内的位线BL11-BL1M的多个读出放大器SA21、SA12、SA23、…、SA2M。
如图7所示，在所述数据被读取至多个读出放大器SA21、SA12、SA23、…、SA2M后，如果所述数据还要被写入存储区段MS1内对应字符线WL1N的存储单元MC1N1-MC1NM，则控制器200可在激活指令ACTWL11后启用对应字符线WL1N的复制列写入指令CRWRC(WL1N)。因此，所述数据即可通过读出放大器SA21、SA12、SA23、…、SA2M同时写入存储区段MS1内对应字符线WL1N的存储单元MC1N1-MC1NM。
另外，如图7所示，因为所述数据还要被写入存储区段MS1内字符线WL12的存储单元，则控制器200可启用对应字符线WL12的复制列写入指令CRWRC(WL12)，所以所述数据即可通过读出放大器SA21、SA12、SA23、…、SA2M同时写入存储区段MS1内字符线WL12的存储单元。另外，图7是说明控制器200所启用的激活指令ACTWL11、写入指令WRC、复制列写入指令CRWRC(WL1N)、CRWRC(WL12)和预充电指令PREC的时序。
另外，图6的操作方法也可利用图5所示的存储区块B2内的存储区段MS1、MS2和感测SA21-SA2M说明，在此不再赘述。
综上所述，本发明所公开的能够快速写入/读取数据的存储电路是根据所述存储电路内多条位线共享一读出放大器的特征，将原来写入耦接于一存储区段内的位线且对应所述存储区段内的一字符线的存储单元的数据同时写入与所述存储区段内的位线共享多个读出放大器且对应至少一其他字符线的存储单元。如此，相较于现有技术，本发明可大幅缩短所述数据被写入对应所述至少一其他字符线的存储单元的时间。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

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1.一种能够快速写入数据的存储电路，包含：
多个存储区块，其中所述多个存储区块中的每一存储区块包含多个存储区段，且所述多个存储区段中的每一存储区段包含多条位线和多条字符线；及
一控制器；
其特征在于还包含：
在所述数据依序写入一存储区段内耦接于所述存储区段内的多条位线且对应所述存储区段内的一字符线的存储单元后且当所述控制器启用至少一复制列写入指令时，耦接所述多条位线的多个读出放大器栓锁住所述数据，以及所述数据被同时写入与所述存储区段的多条位线共享所述多个读出放大器且对应至少一其他字符线的存储单元，其中所述至少一其他字符线对应所述至少一复制列写入指令，且所述至少一复制列写入指令启用时，对应所述字符线的一第一字符开关不会关闭。
2.如权利要求1所述的存储电路，其特征在于：所述至少一其他字符线包含于所述存储区段或包含于不同所述存储区段的其他存储区段。
3.如权利要求1所述的存储电路，其特征在于：所述数据依序写入所述存储区段内耦接于所述存储区段内的多条位线且对应所述存储区段内的所述字符线的存储单元包含：
当所述控制器启用对应所述字符线的激活指令后，对应所述字符线的一第一字符开关开启且所述数据依序写入对应所述字符线的存储单元。
4.一种能够快速写入数据的存储电路，其特征在于包含：
多个存储单元，共同耦接至一读出放大器；以及
一控制器，耦接所述多个存储单元，其中当所述控制器欲写入相同的一数据至所述多个存储单元中的一第一组存储单元以及至少一第二组存储单元时，所述控制器利用所述读出放大器直接复制被写入所述第一组存储单元的数据至所述至少一第二组存储单元，以及当对应所述至少一第二组存储单元的第二字符开关开启时，对应所述第一组存储单元的一第一字符开关不会关闭。
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