CN107039344A - 元件芯片的制造方法、电子部件安装构造体及其制造方法 - Google Patents

元件芯片的制造方法、电子部件安装构造体及其制造方法 Download PDF

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CN107039344A
CN107039344A CN201710057126.6A CN201710057126A CN107039344A CN 107039344 A CN107039344 A CN 107039344A CN 201710057126 A CN201710057126 A CN 201710057126A CN 107039344 A CN107039344 A CN 107039344A
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element chip
face
diaphragm
manufacture method
substrate
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CN107039344B (zh
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针贝笃史
置田尚吾
松原功幸
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Abstract

一种元件芯片的制造方法、电子部件安装构造体及其制造方法，能够抑制安装过程中的导电性材料的爬升。在对具有多个元件区域且元件面被绝缘膜覆盖的基板进行分割而制造多个元件芯片的元件芯片的制造方法中使用的等离子体处理工序中，将基板暴露于第一等离子体，从而将基板分割为元件芯片，成为使具备第一面、第二面以及侧面的元件芯片彼此隔开间隔保持在载体上且使侧面和绝缘膜露出的状态。然后，将元件芯片暴露于第二等离子体，从而将露出的侧面中的与绝缘膜相接的区域部分地除去而形成凹陷部，并通过第三等离子体从而用保护膜覆盖凹陷部，抑制安装过程中导电性材料向侧面爬升。

Description

元件芯片的制造方法、电子部件安装构造体及其制造方法
技术领域
本公开涉及将具有多个元件区域的基板按每个元件区域进行分割来制造元件芯片的元件芯片的制造方法、将该元件芯片安装到基板而成的电子部件安装构造体的制造方法以及电子部件安装构造体。
背景技术
半导体元件等元件芯片通过将具有多个元件区域的晶片状的基板分割为单片而进行制造(例如，参照专利文献1)。在该专利文献所示的现有技术中，首先，以形成有电路的晶片的表面粘附于背面研磨胶带的状态对晶片的背面进行研磨，进而通过蚀刻将晶片薄化。然后，在相当于元件区域的部分形成抗蚀剂层而进行遮盖，实施等离子体蚀刻，从而将晶片分离为单片的半导体元件。
现有技术文献
专利文献
专利文献1：日本特开2002-93752号公报
发明内容
像上述那样从晶片状的基板切出的单片状的元件芯片除了实施封装而用作器件装置以外，有时以WLCSP(Wafer Level Chip Size Package：晶片级芯片尺寸封装)等元件芯片的形态直接被送往电子部件安装工序。在这种情况下，元件芯片以使电路形成面与接合用的焊糊、银膏等导电性材料直接接触的方式进行安装。
本公开的目的在于，提供一种能够抑制安装过程中的导电性材料的爬升的元件芯片的制造方法、电子部件安装构造体的制造方法以及电子部件安装构造体。
本公开的元件芯片的制造方法是将具备具有用分割区域划分的多个元件区域且至少其一部分被绝缘膜覆盖的第一面和第一面的相反侧的第二面的基板在分割区域进行分割而制造多个元件芯片的元件芯片的制造方法，具有以下的特征。即，包括：准备基板的准备工序，基板的第一面侧被载体支承，并且基板形成有耐蚀刻层，使得覆盖与元件区域对置的第二面的区域且使与分割区域对置的第二面的区域露出；以及等离子体处理工序，在准备工序之后，对被载体支承的基板实施等离子体处理。等离子体处理工序包括分割工序、在分割工序之后进行的凹陷部形成工序、以及在凹陷部形成工序之后进行的保护膜形成工序。在分割工序中，将第二面暴露于第一等离子体，从而将未被耐蚀刻层覆盖的区域的基板在该基板的深度方向上蚀刻至到达第一面而将基板分割为元件芯片。而且，成为具备第一面、第二面以及连结第一面和第二面的侧面的元件芯片彼此隔开间隔保持在载体上并且使侧面和绝缘膜露出的状态。在凹陷部形成工序中，在彼此隔开间隔保持在载体上的状态下，将元件芯片暴露于第二等离子体，从而将露出的侧面中的与绝缘膜相接的区域部分地除去而形成凹陷部。在保护膜形成工序中，在彼此隔开间隔保持在载体上的状态下，将元件芯片暴露于供给保护膜形成用气体的同时而产生的第三等离子体，从而在元件芯片的第二面、元件芯片的侧面以及凹陷部形成保护膜。
在本公开的电子部件安装构造体的制造方法中，电子部件安装构造体是将通过本公开的元件芯片的制造方法形成的元件芯片在第一面具备的元件电极通过由元件电极和焊料形成的接合部接合到形成在印刷基板的焊盘电极而成的，电子部件安装构造体的制造方法具有以下的特征。即，包括：焊料膏供给工序，对焊盘电极供给膏状的焊料；以及搭载工序，使元件电极安放于供给到对应的焊盘电极的焊料膏，从而搭载到印刷基板。而且，包括：熔融工序，对印刷基板进行加热而使焊料熔融，从而形成对元件电极和焊盘电极进行焊料接合的接合部；以及冷却工序，对印刷基板进行冷却而使熔融的焊料固化。在熔融工序中，形成在凹陷部的保护膜抑制熔融的焊料向所述侧面爬升。
本公开的电子部件安装构造体是将形成在元件芯片的元件电极通过焊料接合到形成在印刷基板的焊盘电极而成的电子部件安装构造体，具有以下的特征。即，元件芯片具有：元件电极，形成在与印刷基板对置的面；凹陷部，形成在元件芯片的侧面的印刷基板侧的角部；以及保护膜，对凹陷部进行被覆，通过保护膜阻止所述焊料向所述侧面爬升。
根据本公开，能够抑制安装过程中的导电性材料的爬升。
附图说明
图1A是本公开的一个实施方式的元件芯片的制造方法(第一实施例)的工序说明图。
图1B是本公开的一个实施方式的元件芯片的制造方法(第一实施例)的工序说明图。
图1C是本公开的一个实施方式的元件芯片的制造方法(第一实施例)的工序说明图。
图2A是本公开的一个实施方式的元件芯片的制造方法(第一实施例)的工序说明图。
图2B是本公开的一个实施方式的元件芯片的制造方法(第一实施例)的工序说明图。
图2C是本公开的一个实施方式的元件芯片的制造方法(第一实施例)的工序说明图。
图2D是本公开的一个实施方式的元件芯片的制造方法(第一实施例)的工序说明图。
图3是在本公开的一个实施方式的元件芯片的制造方法中使用的等离子体蚀刻装置的结构说明图。
图4A是本公开的一个实施方式的元件芯片的制造方法(第一实施例)的工序说明中的放大说明图。
图4B是本公开的一个实施方式的元件芯片的制造方法(第一实施例)的工序说明中的放大说明图。
图4C是本公开的一个实施方式的元件芯片的制造方法(第一实施例)的工序说明中的放大说明图。
图5A是本公开的一个实施方式的元件芯片的制造方法(第二实施例)的工序说明图。
图5B是本公开的一个实施方式的元件芯片的制造方法(第二实施例)的工序说明图。
图5C是本公开的一个实施方式的元件芯片的制造方法(第二实施例)的工序说明图。
图5D是本公开的一个实施方式的元件芯片的制造方法(第二实施例)的工序说明图。
图6A是本公开的一个实施方式的元件芯片的制造方法(第三实施例)的工序说明图。
图6B是本公开的一个实施方式的元件芯片的制造方法(第三实施例)的工序说明图。
图6C是本公开的一个实施方式的元件芯片的制造方法(第三实施例)的工序说明图。
图6D是本公开的一个实施方式的元件芯片的制造方法(第三实施例)的工序说明图。
图7A是本公开的一个实施方式的元件芯片的制造方法(第三实施例)的工序说明中的放大说明图。
图7B是本公开的一个实施方式的元件芯片的制造方法(第三实施例)的工序说明中的放大说明图。
图7C是本公开的一个实施方式的元件芯片的制造方法(第三实施例)的工序说明中的放大说明图。
图8A是通过本公开的一个实施方式的元件芯片的制造方法制造的元件芯片的结构说明图。
图8B是通过本公开的一个实施方式的元件芯片的制造方法制造的元件芯片的结构说明图。
图9A是本公开的一个实施方式的电子部件安装构造体的制造方法的工序说明图。
图9B是本公开的一个实施方式的电子部件安装构造体的制造方法的工序说明图。
图9C是本公开的一个实施方式的电子部件安装构造体的制造方法的工序说明图。
符号说明
1：基板
1a：第一面
1b：第二面
1c：分割区域
2：元件区域
3：元件电极
4、4*：绝缘膜
5：耐蚀刻层
6：载体
10：元件芯片
10a：第一面
10b：第二面
10c：侧面
12a、12a*、12b、12c：保护膜
15：印刷基板
16：焊盘电极
17：焊料
17*：焊料接合部
C、C*：凹陷部
E：角部
具体实施方式
在对本公开的实施方式进行说明之前，先对以往的装置中的问题进行简单说明。
如上所述，在将WLCSP等元件芯片以按其原样的形态送往电子部件安装工序的情况下，元件芯片以使电路形成面与接合用的焊糊、银膏等导电性材料直接接触的方式进行安装。在该安装过程中，有时会产生所谓的“爬升”，即，在搭载元件芯片时扩展的导电性材料不只浸润扩展至电路形成面的接合部位，还浸润扩展至元件芯片的侧面、背面。这种导电性材料的爬升会成为导致相邻的电极间的短路、在元件芯片的侧面形成不需要的电路而增大消耗电流等各种不良情况的原因。因此，要求抑制这种安装过程中的导电性材料的爬升。
接着，参照附图对本公开的实施方式进行说明。
(第一实施例)
首先，参照图1A～图1C以及图2A～图2D对本实施方式的元件芯片的制造方法中的第一实施例进行说明。在此示出的元件芯片的制造方法将具备具有用分割区域划分的多个元件区域且至少其一部分被绝缘膜覆盖的第一面和该第一面的相反侧的第二面的基板在分割区域进行分割而制造多个元件芯片。
如图1A所示，基板1是在第一面1a形成有多个元件芯片10(参照图1C)的晶片状的基板。在基板1中，作为形成有元件部的元件面的第一面1a被由硅氧化膜、硅氮化膜、硅氮氧化膜等无机绝缘膜构成的绝缘膜4所覆盖。在第一面1a设定有用分割区域1c划分的多个元件区域2。在每个元件区域2形成有连接用的多个元件电极3，多个元件电极3形成为从绝缘膜4突出，或者形成为至少一部分从设置在绝缘膜4的开口露出。
基板1被送往元件芯片制造用的准备工序，并像以下说明的那样，形成掩模并被载体6支承。作为载体6，能够例示被切割架保持的切割胶带、在保持面6a具备粘接层7的支承基板。在该准备工序中，如图1B所示，在第二面1b由在等离子体切割中作为掩模发挥功能的抗蚀剂掩模、表面保护膜等形成耐蚀刻层5。即，在第二面1b形成有耐蚀刻层5，使得覆盖与元件区域2对置的第二面1b的区域，且使与分割区域1c对置的第二面1b的区域露出。此外，使元件电极3的顶端面部分地埋入到载体6的粘接层7，从而基板1的第一面1a侧被载体6的保持面6a支承。另外，准备工序中的掩模形成，可以在被载体6支承之前进行，也可以在被载体6支承之后进行。
在像这样进行准备工序之后，为了对被载体6支承的基板1实施等离子体处理，载体6被送往等离子体处理工序。参照图3对在该等离子体处理工序中使用的等离子体蚀刻装置20的结构进行说明。在图3中，作为真空容器的腔室21的内部是用于进行等离子体处理的处理室21a，在处理室21a的底部配置有载置对作为处理对象的基板1进行支承的载体6的载置台22。在腔室21的顶部的上表面配置有作为上部电极的天线23，天线23与第一高频电源部24电连接。处理室21a内的载置台22还具有作为等离子体处理用的下部电极的功能，载置台22与第二高频电源部25电连接。
在腔室21经由排气口21c连接有真空排气部27，通过驱动真空排气部27，从而对处理室21a内进行真空排气。进而，处理室21a经由气体导入口21b连接有等离子体产生用气体供给部26。在本实施方式所示的等离子体蚀刻装置20中，能够根据等离子体处理的目的，选择性地供给多种等离子体产生用气体。在此，作为等离子体产生用气体的种类，能够选择第一气体26a、第二气体26b、第三气体26c、第四气体26d以及灰化用气体26e。
作为第一气体26a，可使用SF6等以硅为对象的蚀刻效果优异的气体。在本实施方式中，第一气体26a用于产生通过等离子体蚀刻对基板1进行分割的第一等离子体P1。第二气体26b与第一气体26a同样地用于以硅为对象的蚀刻，在本实施方式中，用于在通过等离子体蚀刻对基板1进行分割之后，除去蚀刻槽11的底部的角部E，从而形成凹陷部C(参照图2A)。
第三气体26c是通过等离子体处理形成皮膜的等离子体CVD用的气体，可使用包含C4F8、C2F6、CF4、C6F6、C6F4H2、CHF3、CH2F2等氟化碳的气体。在本实施方式中，用作在分割了基板1的元件芯片10的侧面、第二面1b、侧面10c、凹陷部C形成保护膜的保护膜形成用气体。
第四气体26d是保护膜蚀刻用气体，可使用SF6气体、氧气、氩气等物理蚀刻效果优异的气体。在本实施方式中，用于除去前述的保护膜中的不需要的部分的溅射用途。灰化用气体26e是氧气，在本实施方式中，用作除去结束了掩模功能之后的耐蚀刻层5、为了形成凹陷部C*(参照图6B～图6D、图7B)而部分地除去绝缘膜4等除去有机膜的目的。
在利用等离子体蚀刻装置20进行的等离子体处理中，首先，将作为处理对象的基板1与载体6一同载置在载置台22上，并驱动真空排气部27对处理室21a内进行真空排气。与此同时，通过等离子体产生用气体供给部26将与等离子体处理的目的相应的等离子体产生用气体供给到处理室21a内并维持给定压力。然后，在该状态下通过第一高频电源部24对天线23供给高频电力，从而在处理室21a内产生与供给的等离子体产生用气体的种类相应的等离子体。
此时，通过第二高频电源部25对作为下部电极的载置台22施加偏置电压，从而能够对在处理室21a内产生的等离子体带来促进向载置台22的方向的入射的偏置作用，能够加强所希望的特定方向的等离子体处理效果而进行各向异性蚀刻。
在等离子体处理工序中，首先，利用使用了前述的第一气体26a的第一等离子体P1执行处理。如图1C所示，将基板1的第二面1b暴露于上述的第一等离子体P1，从而将未被耐蚀刻层5覆盖的区域，即，与图1A所示的分割区域1c对应的区域的基板1在该基板1的深度方向上蚀刻至到达第一面1a(参照箭头e)。然后，形成将每个元件芯片10隔开的蚀刻槽11(参照图2A)，将基板1分割为单片的元件芯片10。
即，通过该基板1的分割，具备在基板1的状态下为第一面1a的第一面10a、在基板1的状态下为第二面1b的第二面10b、以及连结第一面10a和第二面10b的侧面10c的元件芯片10彼此隔开间隔保持在载体6上。而且，与进行该分割的同时，成为在蚀刻槽11内露出元件芯片10的侧面10c和绝缘膜4的端部的状态(分割工序)。
分割工序中的蚀刻条件能够根据基板1的材质适当地进行选择。在基板1为硅基板的情况下，分割工序中的蚀刻能够使用所谓的波希法(Bosch process)。在波希法中，依次重复沉积膜沉积步骤、沉积膜蚀刻步骤、以及硅蚀刻步骤，从而能够对未被耐蚀刻层5覆盖的区域在基板1的深度方向上垂直地进行挖入。
作为沉积膜沉积步骤的条件，例如，只要作为原料气体以150～250sccm供给C4F8，并且将处理室内的压力调整为15～25Pa，并且将第一高频电源部24对天线23的投入功率设为1500～2500W，将第二高频电源部25对下部电极的投入功率设为0W，将处理时间设为5～15秒即可。作为沉积膜蚀刻步骤的条件，例如，只要作为原料气体以200～400sccm供给SF6，并且将处理室内的压力调整为5～15Pa，并且将第一高频电源部24对天线23的投入功率设为1500～2500W，将第二高频电源部25对下部电极的投入功率设为100～300W，将处理时间设为2～10秒即可。在此，sccm是表示气体的流量的单位。即，1sccm是指，一分钟流过1cm3的0℃、一个大气压(标准状态)的气体的流量。
作为硅蚀刻步骤的条件，例如，只要作为原料气体以200～400sccm供给SF6，并且将处理室内的压力调整为5～15Pa，并且将第一高频电源部24对天线23的投入功率设为1500～2500W，将第二高频电源部25对下部电极的投入功率设为50～200W，将处理时间设为10～20秒即可。然后，在这些条件下重复沉积膜沉积步骤、沉积膜蚀刻步骤以及硅蚀刻步骤，从而能够以10μm/分钟的速度对硅基板进行挖入。
然后，在上述的分割工序之后，在彼此隔开间隔保持在载体6上的状态下，将元件芯片10暴露于第二等离子体P2。即，如图2A所示，在等离子体蚀刻装置20中，在处理室21a内使用第二气体26b产生第二等离子体P2，将在分割工序中露出的侧面10c中的与绝缘膜4相接的区域部分地除去，从而在角部E形成凹陷部C(凹陷部形成工序)。
像以下那样形成该凹陷部C。即，在分割工序中进行蚀刻而除去基板1和绝缘膜4之后，入射到蚀刻槽11内的等离子体的离子入射到粘接层7。而且，由于粘接层7是绝缘体，所以粘接层7的表面由于离子的入射而积聚正电荷。当像这样成为粘接层7带正电荷的状态时，新入射的离子在蚀刻槽11的底部会由于正电荷彼此的斥力而丧失直线传播性，轨迹会弯曲。这些轨迹弯曲的离子会入射到露出在蚀刻槽11内的底部的侧面10c中的与绝缘膜4相接的区域。然后，通过这些离子的蚀刻作用，如图4A所示，在由第一面10a和侧面10c构成的角部E形成侧面10c中的与绝缘膜4相接的区域被部分地除去的凹陷部C。
作为形成凹陷部的条件，例如，只要作为原料气体以200～400sccm供给SF6，并且将处理室内的压力调整为5～15Pa，并且将第一高频电源部24对天线23的投入功率设为1500～2500W，将第二高频电源部25对下部电极的投入功率设为50～200W即可。在该条件下，能够以5μm/分钟左右的速度形成凹陷部。
然后，在上述的凹陷部形成工序之后，在彼此隔开间隔保持在载体6上的状态下，将元件芯片10暴露于灰化用等离子体。即，如图2B所示，在等离子体蚀刻装置20中，在处理室21a内使用灰化用气体26e产生灰化用等离子体，通过灰化除去以树脂为主成分的耐蚀刻层5。由此，成为分割为单片的元件芯片10的第二面10b暴露的状态。
灰化的条件能够根据耐蚀刻层5的材料适当地进行选择。例如，在耐蚀刻层5为抗蚀剂膜的情况下，只要作为原料气体以150～300sccm供给氧并以0～50sccm供给CF4，并且将处理室内的压力调整为5～15Pa，并且将第一高频电源部24对天线23的投入功率设为1500～2500W，将第二高频电源部25对下部电极的投入功率设为0～30W即可。在该条件下，能够以1μm/分钟左右的速度除去耐蚀刻层5。
接下来，在上述的灰化工序之后，如图2C所示，执行保护膜形成工序。即，在等离子体蚀刻装置20中，在彼此隔开间隔保持在载体6上的状态下，在处理室21a内供给作为保护膜形成用气体(包含氟化碳的气体)的第三气体26c，并且将元件芯片10暴露于产生的第三等离子体P3。由此，如图4B所示，在元件芯片10的第二面10b、侧面10c分别形成保护膜12b、12c，保护膜12b、12c由保护膜形成用气体中的氟化碳在等离子体中分解并在此后进行沉积而皮膜化的、以包含氟和碳的碳氟化合物作为主成分的膜构成，并且在凹陷部形成工序中形成的凹陷部C内也以填充在凹陷部C内的方式形成相同组成的保护膜12a。
形成在凹陷部C内的保护膜12a是以抑制在将元件芯片10直接接合到封装基板等的安装过程中的导电性材料的爬升为目的而形成的，因此优选吸湿性少且组成致密。在本实施方式中，作为为了形成这些保护膜而使用的第三等离子体P3的原料气体，使用包含氟化碳的保护膜形成用气体，因此能够形成由吸湿性少、组成致密且粘着性优异的碳氟化合物膜构成的保护膜。另外，在该保护膜形成工序中，对载置载体6的载置台22(参照图3)施加高频偏置。由此，可促进离子向元件芯片10的入射，能够形成更致密且粘着性更高的保护膜。
作为保护膜的形成条件，例如，只要作为原料气体以150sccm供给C4F8并以50sccm供给He，并且将处理室内的压力调整为15～25Pa，并且将第一高频电源部24对天线23的投入功率设为1500～2500W，将第二高频电源部25对下部电极的投入功率设为50～150W即可。通过在该条件下处理300秒，从而能够形成厚度为3μm的保护膜。在本实施方式中，作为原料气体，使用氟化碳和氦的混合气体，这是因为，通过混合氦，从而可促进等离子体中的原料气体的离解，其结果是，能够形成致密且粘着性高的保护膜。
另外，在上述的条件例中，He流量相对于原料气体的全部流量的比率为25％(＝50/(150+50)×100)。像以下说明的那样，该比率优选在10％至80％之间。即，当He流量相对于原料气体的全部流量的比率大于10％时，容易促进等离子体中的原料气体的离解，其结果是，容易形成更致密且粘着性更高的保护膜。另一方面，当He流量相对于原料气体的全部流量的比率大于80％时，在原料气体中C4F8所占的比率减少，因此有助于形成保护膜的等离子体中的成分(C、F以及它们的化合物)向基板表面的供给不足，基板表面的保护膜的沉积速度变慢，生产性降低。
接着，执行用于除去在保护膜形成工序中形成的保护膜中的不需要的部分的保护膜除去工序。在上述的保护膜形成工序中，在元件芯片10的第一面10a中的凹陷部C形成保护膜的同时，在侧面10c和第二面10b也形成了保护膜12b、12c(参照图4B)。在本实施方式中，不需要这些保护膜12b、12c，因此使用第四等离子体P4进行用于除去保护膜12b、12c的等离子体处理。
即，在等离子体蚀刻装置20中，在处理室21a内，供给成分为氩气、氧气的作为保护膜蚀刻用气体的第四气体26d并且产生第四等离子体P4，并如图2D所示，以彼此隔开间隔保持在载体6上的状态将元件芯片10暴露于第四等离子体P4。由此，在使形成在凹陷部C内的保护膜12a的至少一部分残留的同时，通过第四等离子体P4的蚀刻作用除去在元件芯片10中暴露于上表面的形成在第二面10b的保护膜12b、形成在侧面10c的保护膜12c。
由此，如图4C所示，元件芯片10的第二面10b和侧面10c成为暴露的状态，附着在载体6的上表面的保护膜中的未被元件芯片10覆盖的范围的保护膜12d(参照图2C)也被除去。由此，成为在保护膜除去工序之后的元件芯片10中只在凹陷部C内残留有保护膜12a的状态。
作为除去保护膜的条件，例如，只要作为原料气体以150～300sccm供给Ar并以0～150sccm供给O2，并且将处理室内的压力调整为0.2～1.5Pa，并且将第一高频电源部24对天线23的投入功率设为1500～2500W，将第二高频电源部25对下部电极的投入功率设为150～300W即可。在该条件下，能够以0.5μm/分钟左右的速度对暴露在上表面的保护膜进行蚀刻。
(第二实施例)
另外，在上述的本实施方式的第一实施例中，在通过分割工序形成的蚀刻槽11内除去绝缘膜4并使粘接层7暴露的状态下进行图2A所示的凹陷部形成工序，但是也可以像图5A～图5D所示的第二实施例那样，在残留有作为无机绝缘膜的绝缘膜4的状态下执行凹陷部形成工序。
即，在图5A所示的分割工序中，进行与图1C所示的例子同样的等离子体处理。由此，将基板1在该基板1的深度方向上进行蚀刻，形成将每个元件芯片10隔开的蚀刻槽11，从而将基板1分割为单片的元件芯片10。此时，在蚀刻槽11的底部残留有绝缘膜4的状态下停止蚀刻，并在该状态下执行凹陷部形成工序。
即，在图5B所示的凹陷部形成工序中，与图2A所示的例子同样地，将在分割工序中露出的侧面10c中的与绝缘膜4相接的区域部分地除去而在角部E形成凹陷部C。在蚀刻槽11的底部残留有作为无机绝缘膜的绝缘膜4的状态下，形成该凹陷部C。
在该情况下，在绝缘膜4带正电荷的状态下，新入射的离子在蚀刻槽11的底部由于正电荷彼此的斥力而使其轨迹弯曲，在蚀刻槽11内的底部入射到露出的侧面10c中的与绝缘膜4相接的区域。然后，与第一实施例同样地，通过这些离子的蚀刻作用，在由第一面10a和侧面10c构成的角部E，侧面10c中的与绝缘膜4相接的区域被部分地除去，从而形成凹陷部C。
此后，如图5C所示，执行通过等离子体处理除去残留在蚀刻槽11的底部的绝缘膜4的绝缘膜除去工序。在此，在蚀刻槽11的底部，进行使等离子体从垂直方向入射到绝缘膜4的各向异性蚀刻。由此，残留在蚀刻槽11的底部的绝缘膜4被除去。绝缘膜除去工序的条件能够根据绝缘膜4的材料适当地进行选择。例如，在绝缘膜4为硅氧化膜的情况下，例如，只要作为原料气体以200～500sccm供给Ar并以10～50sccm供给CF4，并且将处理室内的压力调整为0.5～5Pa，并且将第一高频电源部24对天线23的投入功率设为1500～2500W，将第二高频电源部25对下部电极的投入功率设为300～1000W即可。在该条件下，能够以0.3μm/分钟左右的速度除去绝缘膜。
接下来，与图2B所示的例子同样地，执行灰化工序。即，如图5D所示，通过灰化用等离子体除去耐蚀刻层5。由此，分割为单片的元件芯片10的第二面10b成为暴露的状态。关于此后的处理工序，与在第一实施例中用图2C、图2D示出的保护膜形成工序、保护膜除去工序相同。
图8A示出通过这样的第一实施例、第二实施例所示的制造过程制造的元件芯片10。即，如图8A所示，元件芯片10具有被由硅氧化膜等无机绝缘膜构成的绝缘膜4覆盖的第一面10a，在第一面10a形成有从绝缘膜4突出的元件电极3。在第一面10a与侧面10c构成的角部E，通过将侧面10c中的与绝缘膜4相接的区域部分地除去，从而形成有凹陷部C，凹陷部C被保护膜12a覆盖。
(第三实施例)
接着，参照图6A～图6D和图7A～图7C对本实施方式的元件芯片的制造方法中的第三实施例进行说明。在此处示出的元件芯片的制造方法中，在第一实施例、第二实施例中，作为覆盖第一面1a的绝缘膜4使用了硅氧化膜等无机绝缘膜，相对于此，在第三实施例中，示出作为绝缘膜4*而使用了聚酰亚胺等的有机膜的例子。
图6A～图6D示出在第一实施例中通过图1C所示的等离子体处理进行了分割工序之后的元件芯片10的状态。另外，图6A～图6D与第一实施例中的图2A～图2D对应。首先，在分割工序后中，如图6A所示，在彼此隔开间隔保持在载体6上的状态下，将元件芯片10暴露于第二等离子体P2。即，与第一实施例同样地，将在分割工序中露出的侧面10c中的与绝缘膜4*相接的区域部分地除去，从而在角部E形成凹陷部C(凹陷部形成工序)。
由此，如图7A所示，在由第一面10a和侧面10c构成的角部E中，形成侧面10c中的与绝缘膜4*相接的区域被部分地除去的凹陷部C。在此，形成的凹陷部C为在角部E中残留有绝缘膜4*的端部的状态。
然后，在上述的凹陷部形成工序之后进行灰化，从而如图6B所示，通过灰化用等离子体除去耐蚀刻层5。由此，分割为单片的元件芯片10的第二面10b成为暴露的状态。与此同时，通过灰化除去处于残留在角部E的状态的绝缘膜4*。即，在第三实施例中绝缘膜4*是聚酰亚胺等的有机膜，因此延伸至通过凹陷部形成工序形成的凹陷部C的端部与灰化用等离子体接触而被除去。由此，如图7B所示，凹陷部C扩大与被除去的绝缘膜4*的体积相应的量，从而成为凹陷部C*。
接下来，在上述的灰化工序之后，如图6C所示，执行保护膜形成工序，将元件芯片10暴露于第三等离子体P3。由此，如图7C所示，在元件芯片10的第二面10b、侧面10c形成由包含氟和碳的碳氟化合物膜构成的保护膜12b、12c。与此同时，在凹陷部形成工序和灰化工序中形成的凹陷部C*内，电以填充在凹陷部C*内的方式形成与第一实施例所示的保护膜组成相同、功能相同的保护膜12a。
接着，执行用于除去在保护膜形成工序中形成的保护膜中的不需要的保护膜12b、12c的保护膜除去工序。即，如图6D所示，将元件芯片10暴露于第四等离子体P4，从而在使形成在凹陷部C*内的保护膜12a的至少一部分残留的同时，通过第四等离子体P4的蚀刻作用除去形成在元件芯片10的保护膜12b、保护膜12c。
由此，元件芯片10的第二面10b和侧面10c成为暴露的状态，附着在载体6的上表面的保护膜中的未被元件芯片10覆盖的范围的保护膜12d(参照图6C)也被除去。由此，成为在保护膜除去工序之后的元件芯片10中只在凹陷部C*内残留有保护膜12a的状态。
图8B示出通过第三实施例所示的制造过程制造的元件芯片10。即，元件芯片10具有被由聚酰亚胺等的有机膜构成的绝缘膜4*覆盖的第一面10a，在第一面10a形成有从绝缘膜4*突出的元件电极3。在由第一面10a和侧面10c构成角部E，通过将侧面10c中的与绝缘膜4*相接的区域部分地除去，并且除去绝缘膜4*的端部，从而形成有凹陷部C*，凹陷部C*被保护膜12a*覆盖。
像以下说明的那样，具有图8A、图8B所示的结构的元件芯片10具有如下效果，即，在不经过树脂封装等工序而通过焊料接合直接安装到印刷基板等而形成电子部件安装构造体的情况下，可抑制第一面10a中的焊糊等导电性材料的浸润扩展，可防止导电性材料的爬升。
以下，参照图9A～图9C对将通过上述的元件芯片的制造方法形成的元件芯片10焊料接合到形成在印刷基板的焊盘电极而构成的电子部件安装构造体以及电子部件安装构造体的制造方法进行说明。在图9A中，在印刷基板15的上表面与上述构成的元件芯片10的连接用的元件电极3对应地形成有焊盘电极16。在将元件芯片10搭载到焊盘电极16之前，先对焊盘电极16供给膏状的焊料(或者，焊料膏)17(焊料膏供给工序)。
在焊料膏供给工序之后的印刷基板15搭载元件芯片10(搭载工序)。即，将元件芯片10的元件电极3与对应的焊盘电极16进行位置对齐，并如图9B所示，使元件电极3安放于焊盘电极16上的焊料17。由此，元件芯片10搭载到印刷基板15。
接下来，搭载工序之后的印刷基板15被送往回流焊工序，在此进行用于基于焊料的接合的加热。即，对印刷基板15进行加热而使焊料17熔融，从而对元件电极3和焊盘电极16进行焊料接合(熔融工序)。然后，对印刷基板15进行冷却，使熔融的焊料冷却固化(冷却工序)。由此，如图9C所示，形成通过焊料对元件电极3和焊盘电极16进行接合的焊料接合部17*。
这样，形成将形成在元件芯片10的元件电极3通过焊料17接合到形成在印刷基板15的焊盘电极16而构成的电子部件安装构造体。在该电子部件安装构造体中，元件芯片10具有形成在与印刷基板15对置的面的元件电极3、形成在元件芯片10的侧面的印刷基板15侧的角部E的凹陷部C、以及对凹陷部C进行被覆的保护膜12a，成为通过保护膜12a阻止焊料17向侧面10c爬升的方式。
即，在凹陷部C中残留有保护膜12a，因此在熔融工序中焊料17熔融而成的熔融焊料与保护膜12a接触。由碳氟化合物膜构成的保护膜12a的表面性状具有抑制熔融焊料的浸润扩展的特性，因此在熔融工序中，焊料17熔融而成的熔融焊料不会沿着第一面10a扩展，而是在元件电极3与焊盘电极16的周围进行冷却固化，从而形成良好的焊料接合部17*。即，在上述的熔融工序中，形成在凹陷部C的保护膜12a抑制熔融的焊料17向侧面10c爬升。另外，虽然在图9A～图9C中示出了使用图8A所示的元件芯片10的例子，但是对于图8B所示的元件芯片10也能够得到同样的效果。
由此，能够排除在通过焊料17等导电性材料将元件芯片10接合到印刷基板15等安装对象物的安装过程中由于焊料17向侧面10c爬升而有可能产生的各种不良情况。例如，能够排除相邻的电极间的短路、由于在元件芯片10的侧面10c形成不需要的电路而造成的消耗电流的增大等各种不良情况的原因，从而能够提高安装品质。
本公开的元件芯片的制造方法、电子部件安装构造体的制造方法以及电子部件安装构造体具有能够抑制安装过程中的导电性材料的爬升的效果，在将具有多个元件区域的基板按每个元件区域进行分割来制造元件芯片的领域中是有用的。

Claims (8)

1.一种元件芯片的制造方法，将具备第一面和所述第一面的相反侧的第二面的基板在分割区域进行分割来制造多个元件芯片，所述第一面具有用所述分割区域划分的多个元件区域且至少其一部分被绝缘膜覆盖，所述元件芯片的制造方法包括：
准备工序，准备所述基板，所述基板的所述第一面侧被载体支承，并且所述基板形成有耐蚀刻层，使得覆盖与所述元件区域对置的所述第二面的区域且使与所述分割区域对置的所述第二面的区域露出；以及
等离子体处理工序，在所述准备工序之后，对被所述载体支承的所述基板实施等离子体处理，
所述等离子体处理工序包括：
分割工序，将所述第二面暴露于第一等离子体，从而将未被所述耐蚀刻层覆盖的区域的所述基板在该基板的深度方向上蚀刻至到达所述第一面而将所述基板分割为元件芯片，并成为具备所述第一面、所述第二面以及连结所述第一面和所述第二面的侧面的元件芯片彼此隔开间隔保持在所述载体上并且使所述侧面和所述绝缘膜露出的状态；
凹陷部形成工序，在所述分割工序之后，在彼此隔开间隔保持在所述载体上的状态下，将所述元件芯片暴露于第二等离子体，从而将露出的所述侧面中的与所述绝缘膜相接的区域部分地除去而形成凹陷部；以及
保护膜形成工序，在所述凹陷部形成工序之后，在彼此隔开间隔保持在所述载体上的状态下，将所述元件芯片暴露于供给保护膜形成用气体的同时而产生的第三等离子体，从而在所述元件芯片的所述第二面、所述元件芯片的所述侧面以及所述凹陷部形成保护膜。
2.根据权利要求1所述的元件芯片的制造方法，还包括：保护膜除去工序，在所述保护膜形成工序之后，在彼此隔开间隔保持在所述载体上的状态下，将所述元件芯片暴露于第四等离子体，从而在使形成在所述凹陷部的所述保护膜的至少一部分残留的同时除去形成在所述元件芯片的所述第二面和所述侧面的所述保护膜。
3.根据权利要求1所述的元件芯片的制造方法，所述绝缘膜为无机绝缘膜。
4.根据权利要求1所述的元件芯片的制造方法，所述保护膜是以碳氟化合物为主成分的膜。
5.根据权利要求4所述的元件芯片的制造方法，所述保护膜形成用气体包含氟化碳。
6.一种电子部件安装构造体的制造方法，所述电子部件安装构造体是将利用权利要求1至5中的任一项所述的元件芯片的制造方法而形成的元件芯片在所述第一面具备的元件电极通过由所述元件电极和焊料形成的接合部接合到形成在印刷基板的焊盘电极而成的，所述电子部件安装构造体的制造方法包括：
焊料膏供给工序，对所述焊盘电极供给膏状的焊料；
搭载工序，使所述元件电极安放于供给到对应的所述焊盘电极的焊料膏，从而搭载到所述印刷基板；
熔融工序，对所述印刷基板进行加热而使所述焊料熔融，从而形成对所述元件电极和焊盘电极进行焊料接合的接合部；以及
冷却工序，对所述印刷基板进行冷却而使熔融的所述焊料固化，
在所述熔融工序中，形成在所述凹陷部的所述保护膜抑制熔融的焊料向所述侧面爬升。
7.一种电子部件安装构造体，通过焊料将形成在元件芯片的元件电极接合到形成在印刷基板的焊盘电极而成，
所述元件芯片具有：
所述元件电极，形成在与所述印刷基板对置的面；
凹陷部，形成在所述元件芯片的侧面的所述印刷基板侧的角部；以及
保护膜，被覆所述凹陷部，
通过所述保护膜阻止所述焊料向所述侧面爬升。
8.根据权利要求7所述的电子部件安装构造体，所述保护膜是以碳氟化合物为主成分的膜。
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