CN106898649A - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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CN106898649A
CN106898649A CN201611149521.9A CN201611149521A CN106898649A CN 106898649 A CN106898649 A CN 106898649A CN 201611149521 A CN201611149521 A CN 201611149521A CN 106898649 A CN106898649 A CN 106898649A
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layer
grid
semiconductor element
semiconductor fin
base material
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罗威扬
程潼文
詹佳玲
林木沧
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体元件及其制造方法。半导体元件包含基材、至少一源极漏极特征、栅极结构以及至少一栅极间隙壁。源极漏极特征至少部分位于基材中。栅极结构位于基材上。栅极间隙壁位于栅极结构的至少一侧壁上。栅极间隙壁的底部位具有掺杂物于其中。

Description

半导体元件及其制造方法
技术领域
本发明实施例是关于一种半导体元件，特别是关于一种半导体元件的制造方法。
背景技术
随着集成电路尺寸的缩小以及其运算速度需求的增加，晶体管随之具有越来越小的尺寸以及越来越高的驱动电流，因而发展出鳍式场效晶体管(Fin Field-EffectTransistors,FinFET)。鳍式场效晶体管具有渐增的通道宽度。通过形成包含鳍片的侧壁上的部位以及包含鳍片的顶面上的部位的通道来达到通道宽度的增加。因为晶体管的驱动电流正比于通道宽度，鳍式场效晶体管的驱动电流亦随着通道宽度的增加而变大。
发明内容
依据本发明实施例的一些实施方式，半导体元件包含基材、至少一源极漏极特征、栅极结构以及至少一栅极间隙壁。源极漏极特征至少部分位于基材中。栅极结构位于基材上。栅极间隙壁位于栅极结构的至少一侧壁上。栅极间隙壁的底部位具有掺杂物于其中。
依据本发明实施例的另一些实施方式，半导体元件包含基材、至少一半导体鳍片、栅极结构、至少一栅极间隙壁。半导体鳍片位于基材上。半导体鳍片包含至少一通道部位以及至少一源极漏极部位。栅极结构位于半导体鳍片的通道部位上。栅极间隙壁相邻于栅极结构，位于半导体鳍片上，且位于半导体鳍片的通道部位与该源极漏极部位之间。栅极间隙壁包含VIIIA族杂质于其中。
依据本发明实施例的再一些实施方式，半导体元件的制造方法包含形成半导体鳍片于基材上。形成栅极结构于半导体鳍片上。形成间隙层，此间隙层覆盖栅极结构以及半导体鳍片。进行等向性掺杂制程，以掺杂间隙层。图案化间隙层，以形成至少一栅极间隙壁于栅极结构的至少一侧壁上。
附图说明
图1绘示依据本发明实施例的一些实施方式的半导体元件的示意图；
图2至图11绘示依据本发明实施例的一些实施方式的图1中半导体元件于中间制造阶段下的剖视图；
图12绘示依据本发明实施例的一或多个实施方式的半导体元件的砷化物浓度对应深度的剖析图。
具体实施方式
以下的说明将提供许多不同的实施方式或实施例来实施本发明实施例的主题。元件或排列的具体范例将在以下讨论以简化本发明实施例。当然，这些描述仅为部分范例且本发明实施例并不以此为限。例如，将第一特征形成在第二特征上或上方，此一叙述不但包含第一特征与第二特征直接接触的实施方式，也包含其他特征形成在第一特征与第二特征之间，且在此情形下第一特征与第二特征不会直接接触的实施方式。此外，本发明实施例可能会在不同的范例中重复标号或文字。重复的目的是为了简化及明确叙述，而非界定所讨论的不同实施方式及配置间的关系。
此外，空间相对用语如“下面”、“下方”、“低于”、“上面”、“上方”及其他类似的用语，在此是为了方便描述图中的一个元件或特征与另一个元件或特征的关系。空间相对用语除了涵盖图中所描绘的方位外，该用语更涵盖装置在使用或操作时的其他方位。也就是说，当该装置的方位与附图不同(旋转90度或在其他方位)时，在本文中所使用的空间相对用语同样可相应地进行解释。
通过本发明实施例所示的一或多个实施方式而可被改善的元件可为半导体元件。举例来说，前述的元件可为鳍式场效晶体管(Fin Field-Effect Transistors,FinFET)元件。以下的发明实施例继续利用鳍式场效晶体管为例以描述本发明实施例不同的实施方式。然而，应了解到，本发明实施例的应用并不限于特定形式的元件。
图1绘示依据本发明实施例的一些实施方式的半导体元件的示意图。此外，图2至图11绘示依据本发明实施例的一些实施方式的图1中半导体元件于中间制造阶段下的剖视图。图2至图11的剖面部位是沿着图1的线段A-A’。请参照图2。基材110可被提供。于一些实施方式中，基材110可包含硅。可选地，基材110可包含锗、硅锗、砷化镓或其他适合的半导体材料。可选地，基材110可包含磊晶层。举例来说，基材110可具有覆盖于块状半导体的磊晶层。进一步来说，为了性能的提升，基材110可因而产生应变。举例来说，磊晶层可包含不同于块状半导体的半导体材料，例如覆盖于块状硅半导体的硅锗层或是覆盖于块状硅锗半导体的硅层。此种具有应变的基材的形成方法可包含选择性磊晶成长(selective epitaxialgrowth,SEG)。此外，基材110可包含绝缘底半导体(semiconductor-on-insulator,SOI)结构。可选地，基材110可包含埋入式界电层，例如埋入式氧化(buried oxide,BOX)层。此外，基材110的形成方法举例可包含氧离子植入硅晶隔离(Separation by implanted oxygen,SIMOX)制程、晶圆接合(wafer bonding)制程、选择性磊晶成长(selective epitaxialgrowth,SEG)制程或其他适合的方法。
至少一半导体鳍片112形成于基材110上。于一些实施方式中，半导体鳍片112可包含硅。举例来说，半导体鳍片112的形成方法可利用光微影制程来图案化并蚀刻基材110。于一些实施方式中，一层状的光阻材料(图未示)可设置于基材110上方。此层状的光阻材料可依据图案的设计(于本实施方式中所设计的图案为半导体鳍片112)而接受照射(暴露)，并经过显影以移除光阻材料的一部位。剩下的光阻材料可于后续的制程(例如：蚀刻制程)中保护其所覆盖的材料。应了解到，其他的遮罩(例如氧化物或氮硅化物遮罩)亦可使用于后续的蚀刻制程中。
请参照图1。多个绝缘结构105可形成于基材110上。绝缘结构105可于半导体鳍片112的周围作为浅沟槽隔离(shallow trench isolation,STI)。绝缘结构105的形成方法可为化学气化沉积(chemical vapor deposition,CVD)制程，且四乙基正硅酸盐(tetraethylorthosilicate,TEOS)以及氧气可作为化学气化沉积制程的前驱物。于一些实施方式中，绝缘结构105的形成方法可为离子植入制程，例如以氧离子、氮离子、碳离子等类似的离子来植入于基材110中。于一些其他的实施方式中，绝缘结构105是绝缘底半导体晶圆的绝缘层。
请参照图2。栅极介电质120是形成以覆盖于半导体鳍片112。栅极介电质120的形成方法可包含热氧化制程、化学气相沉积制程、溅镀制程或其他本领域已知用于形成栅极介电质的方法。依据形成介电层所使用的制程，于半导体鳍片112的顶部上的栅极介电质120的厚度可不同于半导体鳍片112的侧壁(图未示)上的栅极介电质120的厚度。举例来说，栅极介电质120可包含高介电常数材料，例如金属氧化物(metal oxides)、金属氮化物(metal nitrides)、金属硅化物(metal silicates)、过渡金属氧化物(transition metal-oxides)、过渡金属氮化物(transition metal-nitrides)、过渡金属硅化物(transitionmetal-silicates)、金属氮氧化物(oxynitrides of metals)、金属铝化物(metalaluminates)、硅锆化物(zirconium silicate)、铝锆化物(zirconium aluminate)或上述材料的任意组合。于一些实施方式中，栅极介电质120的材料可包含铪氧化物(hafniumoxide,HfO2)、铪硅氧化物(hafnium silicon oxide,HfSiO)、铪硅氮氧化物(hafniumsilicon oxynitride,HfSiON)、铪钽氧化物(hafnium tantalum oxide,HfTaO)、铪钛氧化物(hafnium titanium oxide,HfTiO)、铪锆氧化物(hafnium zirconium oxide,HfZrO)、镧氧化物(lanthanum oxide,LaO)、锆氧化物(zirconium oxide,ZrO)、钛氧化物(titaniumoxide,TiO)、钽氧化物(tantalum oxide,Ta2O5)、钇氧化物(yttrium oxide,Y2O3)、锶钛氧化物(strontium titanium oxide,SrTiO3,STO)、钡钛氧化物(barium titanium oxide,BaTiO3,BTO)、钡锆氧化物(barium zirconium oxide,BaZrO)、镧铪氧化物(hafniumlanthanum oxide,HfLaO)、镧硅氧化物(lanthanum silicon oxide,LaSiO)、铝硅氧化(aluminum silicon oxide,AlSiO)、铝氧化物(aluminum oxide,Al2O3)、氮硅化物(siliconnitride,Si3N4)、硅氧氮化物(oxynitrides,SiON)以及上述材料的任意组合。栅极介电质120可具有多层结构，例如其中一层结构为硅氧化物(例如介面层)而另一层结构为高介电常数的材料。
虚设层130是形成于栅极介电质120上。沉积虚设层130的方法可包含化学气相沉积制程、溅镀沉积制程或其他本领域已知用来沉积导电材料的方法。虚设层130的材料可包含多晶硅(polycrystalline-silicon,poly-Si)或多晶硅锗(poly-crystalline silicon-germanium,poly-SiGe)。举例来说，于一些实施方式中，虚设层130可包含通过低压化学气相沉积(low-pressure chemical vapor deposition,LPCVD)制程所沉积的非掺杂的多晶硅。举例来说，多晶硅亦可包含通过炉管所沉积的原位掺杂的多晶硅。可选地，虚设层130可包含其他适合的材料。进一步来说，虚设层130可利用均匀或非均匀掺杂来掺杂多晶硅。
遮罩层210是通过适合的制程而形成一适当的厚度于虚设层130上。当遮罩层210不覆盖于虚设层130的其他部位时，也可视为遮罩层210可覆盖于虚设层130的一部位。于一些实施方式中，遮罩层210为包含硅氧化物(silicon oxide)的硬遮罩层。于一些其他实施方式中，遮罩层210的材料可包含氮硅化物(silicon nitride,SiN)、氮氧硅化物(siliconoxynitride,SiON)、碳硅化物(silicon carbide,SiC)、碳氧硅化物(SiOC)、旋涂式玻璃(spin-on glass,SOG)、低介电常数膜(a low-κfilm)、四乙基正硅酸盐(tetraethylorthosilicate,TEOS)、等离子辅助化学气相沉积氧化物(plasma enhanced CVD oxide,PE-oxide)、高深宽比制程(high-aspect-ratio-process,HARP)所形成的氧化物、非结晶碳材料(amorphous carbon material)、其他适合的材料及/或上述材料的任意组合。硅氧化物层的形成方法可包含，但不限于，化学气相沉积制程、物理气象沉积制程或原子层沉积制程。此外，硅氧化物层的厚度范围实质上可从约100埃至约500埃。于一些实施方式中，遮罩层210可为光阻层。光阻层是沉积于虚设层130上。举例来说，光阻层的形成方法可包含旋转涂布制程。此外，举例来说，光阻层可通过光照制程、显影制程、干燥制程、蚀刻制程以及其他适当的制程来形成所设计的图案。于一些实施方式中，遮罩层210可包含沉积于虚设层130上的氮化硅层212以及沉积于氮化硅层212上的氧化物层214。
请参照图3。通过移除制程(或蚀刻制程)来移除虚设层130中的设计图案的外的部位(见图1)，以形成虚设栅极132。也就是说，移除未被遮罩层210覆盖的部位以形成虚设栅极132。于一些实施方式中，可进行多次的蚀刻制程。然而，图案化制程的进行是不限于利用光阻的光微影制程(photolithography process)。图案化制程的进行可通过浸润式微影(immersion lithography)制程、电子束微影(electron beam lithography)制程或其他适合的制程。因此，通过上述方法可得到如图3所示的虚设栅极132的图案。虚设栅极132所覆盖的半导体鳍片112的至少一部位可称为半导体鳍片112的通道部位114，而未被虚设栅极132所覆盖的半导体鳍片112的其他部位可称为未覆盖部位116。于一些实施方式中，栅极介电质120也可被图案化，使得半导体鳍片112具有未被栅极介电质120以及虚设栅极132所覆盖的部位(见图3)。于一些其他实施方式中，半导体鳍片112可被栅极介电质120所盖住。
请参照图4。间隙层140是形成以覆盖于虚设栅极132、遮罩层210以及半导体鳍片112。于一些实施方式中，间隙层140是复合层。此复合层包含具有不同蚀刻特性的下子结构层142以及上子结构层144。于一些实施方式中，下子结构层142是由氧化物所形成，因此亦可被称为衬垫氧化物层。上子结构层144是由氮硅化物或氮氧硅化物所形成，因此亦可被称为衬垫氮化物层。于其他一些实施方式中，间隙层140可具有单层或复合层的结构。此单层或复合层的结构可包含氧化物(oxide)、氮硅化物(silicon nitride)、氮氧硅化物(silicon oxynitride,SiON)及/或其他介电材料。间隙层140的形成方法可包含，但不限于，等离子辅助化学气相沉积(plasma enhanced chemical vapor deposition,PECVD)制程、低压化学气相沉积(low-pressure chemical vapor deposition,LPCVD)制程、次常压化学气相沉积(sub-atmospheric chemical vapor deposition,SACVD)制程。
接着，间隙层140可被掺杂。于一些实施方式中，间隙层140可通过等离子掺杂(Plasma Doping,PLAD)制程来掺杂。详细来说，富掺杂层150是形成于间隙层140上。举例来说，富掺杂层150的形成方法可包含等离子离子辅助沉积(plasma ion assisteddeposition,PIAD)制程。富掺杂层150可包含杂质。此杂质是用来形成间隙层140中的掺杂物。富掺杂层150的形成材料可包含N型杂质或P型杂质。举例来说，富掺杂层150的材质可包含硼化物(例如氟化硼(BF2)或乙硼烷(B2H6))、铟化物(indium)、磷化物(phosphorous)及/或砷化物(arsenic)。于一些实施方式中，富掺杂层150的厚度T实质上为约5纳米至约6纳米。
请参照图5。通过撞击植入制程(nock-on implantation)以将富掺杂层150中的掺杂物撞击至间隙层140中。撞击植入制程所使用的离子220可包含元素周期表中VIIIA族的元素离子或惰性气体离子，例如氙离子、氩离子、氖离子、氦离子、氪离子、上述离子的任意组合或其他不会对于鳍式场效晶体管的特性具有不利影响的离子。于一些实施方式中，通过惰性气体离子的散射可诱发出撞击植入制程。于一些实施方式中，在沉积以及离子的模式下，等离子离子辅助沉积制程以及撞击植入制程可被视为等离子掺杂(Plasma Doping,PLAD)制程。因为通过惰性气体离子的散射可诱发出等离子掺杂制程，等离子掺杂制程为等相性掺杂制程。也就是说，虚设栅极132的侧壁上的间隙层140的部位可被掺杂。因此，间隙层140可包含元素周期表中VIIIA族的元素的杂质。于一些实施方式中，已掺杂的间隙层140可通过至少一退火制程(annealing process)而扩散位于其中的掺杂物。于一些实施方式中，当掺杂物为砷化物时，间隙层140的砷化物的掺杂物浓度是实质上为一范围从约6x1019atoms/cm3至约1x1021atoms/cm3。当掺杂物是为磷化物时，间隙层140的磷化物的掺杂物浓度实质上是为一范围从约2x1019atoms/cm3至约3x1020atoms/cm3。当掺杂物是为硼化物时，间隙层140的硼化物的掺杂物浓度实质上是为一范围从约1x1020atoms/cm3至约1x1021atoms/cm3。于一些实施方式中，当掺杂物是为氙化物时，间隙层140的氙化物的掺杂物浓度实质上是为一范围从约2x1018atoms/cm3至约5x1018atoms/cm3。
请参照图6。多个轻掺杂漏极(Light-Doped Drain,LDD)区域160是形成于半导体鳍片112中。特别来说，轻掺杂漏极区域160是形成于半导体鳍片112的未覆盖部位116中。虚设栅极132插入于两个轻掺杂漏极区域160之间。也就是说，轻掺杂漏极区域160是实质上对准于虚设栅极132的侧壁134。轻掺杂漏极区域160的形成方法可包含等离子掺杂制程、离子植入制程、扩散制程及/或其他适当的制程。于一些实施方式中，若轻掺杂漏极区域160是通过等离子掺杂制程所形成，则间隙层140的掺杂以及轻掺杂漏极区域160的形成可被同时进行。也就是说，间隙层140以及轻掺杂漏极区域160具有实质上同样的掺杂物。然而，于一些其他实施方式中，间隙层140的掺杂以及轻掺杂漏极区域160的形成可被分开进行。依据鳍式场效晶体管的导电类型，轻掺杂漏极区域160可使用N型掺杂物或P型掺杂物来做掺杂。举例来说，若鳍式场效晶体管的最后结构是N型鳍式场效晶体管，则轻掺杂漏极区域160中的掺杂物可为磷化物、砷化物或上述掺杂物的任意组合。然而，若鳍式场效晶体管的最后结构是P型鳍式场效晶体管，则轻掺杂漏极区域160中的掺杂物可为硼化物、铟化物或上述掺杂物的任意组合。
请参照图7。间隙层140可被图案化为一对栅极间隙壁140’。此栅极间隙壁140’是位于虚设栅极132的相对的侧壁134上，且位于遮罩层210的相对的侧壁上。湿蚀刻或干蚀刻制程可被用来作为图案化的制程。栅极间隙壁140’可包含衬垫氧化物部位(亦可称为内部位)以及氮化物部位(亦可称为外部位)。
请参照图8。虚设栅极132以及栅极间隙壁140’所暴露的半导体鳍片112的部位可被移除(或使成为凹陷)，以形成至少一凹陷R于半导体鳍片112中。举例来说，如图8中的两个凹陷R所示的结构。此外，材料的任何适当的量可被移除。于一些实施方式中，轻掺杂漏极区域160的部位也可被移除，而剩下的轻掺杂漏极区域160是相邻于栅极间隙壁140’的凹陷R。剩下的半导体鳍片112具有凹陷部位118以及通道部位114。凹陷部位118是嵌入于基材110中，且通过凹陷R而被暴露出。通道部位114是位于虚设栅极132下方，且为鳍式场效晶体管的通道。轻掺杂漏极区域160是位于通道部位114中，且位于栅极间隙壁140’下方。
移除半导体鳍片112的部位的方法可包含形成光阻层或覆盖层(例如氧化物覆盖层)于图7所示的结构上方、图案化光阻层或覆盖层以具有可暴露出半导体鳍片112的部位的开口以及回蚀刻半导体鳍片112的材料。于一些实施方式中，半导体鳍片112可利用干蚀刻制程来蚀刻。可选地，蚀刻制程可为湿蚀刻制程或干蚀刻制程以及湿蚀刻制程的组合。移除半导体鳍片112的部位也可包含微影制程，借以进行蚀刻制程。微影制程(lithographyprocess)可包含光阻涂布(例如旋转涂布制程)、软烘烤(soft baking)、遮罩对准(maskaligning)、曝光(exposure)、曝光后烘烤(post-exposure baking)、对光阻剂显影(developing the photoresist)、洗濯(rinsing)、干燥(drying)，例如硬烘烤(hardbaking)、或其他适当的制程或上述制程的任意组合。可选地，微影制程可通过其他方法来进行或取代，例如无遮罩微影制程(maskless photolithography)、电子束写入制程(electron-beam writing)以及离子束写入制程(ion-beam writing)。于一些其他实施方式中，微影制程可包含纳米转印制程(nanoimprint technology)。于一些实施方式中，通过预清洗制程(pre-cleaning process)可利用氢氟酸(HF)或其他适合的溶液来清洗凹陷R。
请参照图9。多个磊晶结构170是分别形成于凹陷R中以及半导体鳍片112的凹陷部位118上。磊晶结构170以及凹陷部位118可形成半导体鳍片112的源极漏极部位。磊晶结构170可通过一或多个磊晶制程(epitaxy or epitaxial(epi)processes)所形成，使得硅特征、硅锗特征及/或其他适当的特征可形成位于半导体鳍片112的凹陷部位118上的结晶态。于一些实施方式中，磊晶结构170的晶格常数是不同于半导体鳍片112的晶格常数。磊晶结构170可产生应变或应力，使得半导体元件具有载子迁移率，并可提高半导体元件的性能。磊晶制程可包含化学气相沉积制程(例如气相磊晶(vapor-phase epitaxy,VPE)制程及/或超高真空化学气相沉积制程(ultra-high vacuum chemical vapor deposition,UHV-CVD))、分子束磊晶制程(molecular beam epitaxy)及/或其他适当的制程。磊晶制程可使用气态的及/或液态的前驱物。此气态的及/或液态的前驱物可交互作用于半导体鳍片112的凹陷部位118的结构(例如硅)。因此，应变通道可被形成以增加载子迁移率，并可提高元件性能。磊晶结构170可为原位掺杂。掺杂的种类可包含P型掺杂物(例如硼化物或硼氟化物(BF2))、N型掺杂物(例如磷化物(phosphorus)或砷化物(arsenic))及/或其他适当的掺杂物或及/或前述掺杂物的任意组合。若磊晶结构170非为原位掺杂，则可通过第二植入制程(例如接面植入制程(junction implant process))来掺杂磊晶结构170。一或多个退火制程可作用于磊晶结构170。退火制程可包含快速热退火(rapid thermal annealing,RTA)制程及/或激光退火制程(laser annealing processes)。
于一些实施方式中，多个硅化物接触(图未示)分别位于磊晶结构170上。硅化物为金属以及硅所形成的化合物。此硅化物于半导体元件中被用来作为接触。硅化物接触是热稳定，而相较于多晶硅具有较低的阻值，且为良好的欧姆接触。因为硅化反应可消减位于接触以及特征之间的介面的缺陷，硅化物接触是可靠的。自对准硅化物(self-alignedsilicide(“salicide”))制程可于半导体制造过程中被使用。在制造高速互补式金属氧化物半导体(complementary metal oxide semiconductor,CMOS)元件的过程中可使用硅化物制程。硅化物制程可将磊晶结构170的表面部位转变为硅化物接触。硅化物制程包含与硅(silicon,Si)一起进行硅化反应的金属沉积物。为了于磊晶结构170上形成硅化物接触，金属材料硅可沉积而覆盖于磊晶结构170上。加热晶圆至硅可与磊晶结构170的硅反应而形成接触的温度之后，移除未反应的金属。当于一区域中的未反应的金属被移除之后，硅化物接触可遗留于磊晶结构170上方的另一区域。
接着，介电层180是形成于栅极间隙壁140’的外侧，且形成于基材110上。也就是说，介电层180围绕于栅极间隙壁140’以及虚设栅极132。介电层180的材质可包含硅氧化物(silicon oxide)、氮氧化物(oxynitride)或其他适当的材料。介电层180可包含单层结构或多层结构。介电层180的形成方法可包含一适当的制程，例如化学气相沉积制程或原子层沉积制程。通过化学机械研磨(chemical mechanical planarization,CMP)制程可移除多余的介电层180，且可于后续移除虚设栅极的制程中来暴露出虚设栅极132的顶面。
请参照图10。虚设栅极132(见图9)是移除以形成开口182，并将栅极间隙壁140’作为开口182的侧壁。于一些其他实施方式中，图9所示的栅极介电质120也可一起被移除。可选地，于一些实施方式中，虚设栅极132可被移除，而栅极介电质120则被保留下来。通过干蚀刻制程、湿蚀刻制程或前述制程的组合可移除虚设栅极132(以及栅极介电质120)。举例来说，湿蚀刻制程可包含具有氢氧化物的溶液(例如氢氧化铵)、去离子水及/或其他适当的蚀刻溶液。
于图10中，因为栅极间隙壁140’已被掺杂，栅极间隙壁140’的蚀刻速率是低于未被掺杂的栅极间隙层。因此，当虚设栅极132被移除时，栅极间隙壁140’是不易被移除。在前述结构配置下，形成于开口182中的栅极结构190(见图11)是不连接于源极漏极特征(例如半导体鳍片112及/或磊晶结构170)。栅极间隙壁140’可为位于栅极结构190与于源极漏极特征之间的良好的绝缘体。
请参照图11。栅极结构190是形成于开口182上。换句话说，栅极间隙壁140’是位于栅极结构190的相对的侧壁192上。前述所形成的栅极结构190也可包含栅极介电层、覆盖层、填充层及/或其他可设计为金属栅极堆叠的适当的层状结构。包含于栅极结构190中的功函数金属层可为n型或p型功函数层。举例来说，p型功函数金属层可包含钛氮化物(TiN)、钽氮化物(TaN)、钌化物(Ru)、钼化物(Mo)、铝化物(Al)、钨氮化物(WN)、硅锆化物(ZrSi2)、硅钼化物(MoSi2)、硅钽化物(TaSi2)、硅镍化物(NiSi2)、其他适当的n型功函数材料或前述材料的任意组合。功函数层可包含多个的层状结构。功函数层的沉积方法可包含化学气相沉积制程、物理气相沉积制程、电镀制程及/或其他适当的制程。于一些实施方式中，所形成的栅极结构190是包含p型功函数层的p型金属栅极。于一些实施方式中，于栅极结构190中的覆盖层可包含耐热金属以及耐热金属的氮化物(例如钛氮化物(TiN)、钽氮化物(TaN)、钨氮化物(W2N)、钛氮硅化物(TiSiN)或钽氮硅化物(TaSiN))。覆盖层的沉积方法可包含化学气相沉积制程、物理气相沉积制程、金属有机化学气相沉积(Metal-organic chemicalvapor deposition,MOCVD)制程以及原子层沉积制程。于一些实施方式中，包含于介电层180中的填充层可包含钨化物(tungsten,W)。金属层的沉积方法可包含原子层沉积制程、物理气相沉积制程、化学气相沉积制程或其他适当的制程。于栅极结构190形成之后，半导体元件的结构可如图1所示。
请参照图1以及图11。从结构上来看，栅极间隙壁140’具有顶部位140t以及底部位140b。底部位140b是位于顶部位140t与半导体鳍片112之间。于一些实施方式中，栅极间隙壁140’的底部位140b是相邻于半导体鳍片112。因为至少栅极间隙壁140’的底部位140b已被掺杂，则栅极间隙壁140’的底部位140b的掺杂浓度实质上为约6x1019atoms/cm3至约1x1020atoms/cm3，且栅极间隙壁140’的蚀刻速率是低于未掺杂的栅极间隙壁的蚀刻速率。因此，当开口182形成之后。栅极间隙壁140’的结构可不被破坏。于前述的结构配置下，形成于开口182中的栅极结构190是不连接于源极漏极特征(例如半导体鳍片112及/或磊晶结构170)。栅极间隙壁140’可作为位于栅极结构190与于源极漏极特征之间的良好的绝缘体。
请参照图11。半导体鳍片112的轻掺杂漏极区域160具有顶部位160t以及底部位160b。顶部位160t是位于底部位160b与栅极间隙壁140’之间。轻掺杂漏极区域160的顶部位160t的掺杂浓度实质上可为约2x1020atoms/cm3至约3x1020atoms/cm3，而轻掺杂漏极区域160的底部位160b的掺杂浓度实质上可为约2x1019atoms/cm3至约4x1019atoms/cm3。也就是说，栅极间隙壁140’的底部位140b的掺杂浓度是高于轻掺杂漏极区域160的底部位160b的掺杂浓度，而栅极间隙壁140’的底部位140b的掺杂浓度是低于轻掺杂漏极区域160的顶部位160t的掺杂浓度。
图12绘示依据本发明实施例的一或多个实施方式的半导体元件的砷化物浓度-深度剖析图。栅极间隙壁以及轻掺杂漏极区域的掺杂物为砷化物。惰性气体离子为氙离子。栅极间隙壁的材质可包含氧化物以及氮化物。轻掺杂漏极区域的顶部位的厚度实质上为18纳米，而轻掺杂漏极区域的底部位的厚度实质上为6纳米。
前述多个实施方式的特征使此技术领域中具有通常知识者可更佳的理解本发明实施例的各方面，在此技术领域中具有通常知识者应了解，为了达到相同的目的及/或本发明实施例所提及的实施方式相同的优点，其可轻易利用本发明实施例为基础，进一步设计或修饰其他制程及结构，在此技术领域中具有通常知识者亦应了解，该等相同的结构并未背离本发明实施例的精神及范围，而在不背离本发明实施例的精神及范围下，其可在此进行各种改变、取代及修正。

Claims (10)

1.一种半导体元件，其特征在于，包含：
一基材；
至少一源极漏极特征，至少部分位于该基材中；
一栅极结构，位于该基材上；以及
至少一栅极间隙壁，位于该栅极结构的至少一侧壁上，其中该栅极间隙壁的至少一底部位具有多个掺杂物于其中。
2.根据权利要求1所述的半导体元件，其特征在于，所述多个掺杂物包含砷、磷、硼或上述掺杂物的任意组合。
3.根据权利要求1所述的半导体元件，其特征在于，该源极漏极特征包含一轻掺杂漏极区域。
4.根据权利要求1所述的半导体元件，其特征在于，该栅极间隙壁的该底部位是相邻于该源极漏极特征。
5.根据权利要求1所述的半导体元件，其特征在于，该源极漏极特征包含一磊晶结构。
6.一种半导体元件，其特征在于，包含：
一基材；
至少一半导体鳍片，位于该基材上，其中该半导体鳍片包含至少一通道部位以及至少一源极漏极部位；
一栅极结构，位于该半导体鳍片的该通道部位上；以及
至少一栅极间隙壁，相邻于该栅极结构，位于该半导体鳍片上，且位于该半导体鳍片的该通道部位与该源极漏极部位之间，其中该栅极间隙壁包含多个VIIIA族杂质于其中。
7.一种半导体元件的制造方法，其特征在于，包含：
形成一半导体鳍片于一基材上；
形成一栅极结构于该半导体鳍片上；
形成一间隙层以覆盖该栅极结构以及该半导体鳍片；
进行一等向性掺杂制程以掺杂该间隙层；以及
图案化该间隙层以形成至少一栅极间隙壁于该栅极结构的至少一侧壁上。
8.根据权利要求7所述的半导体元件的制造方法，其特征在于，该等向性掺杂制程包含：
形成一富掺杂层，该富掺杂层包含多个掺杂物于该间隙层上；以及
进行一撞击植入制程以将所述多个掺杂物撞击至该间隙层中。
9.根据权利要求7所述的半导体元件的制造方法，其特征在于，还包含形成一轻掺杂漏极区域于该半导体鳍片中，其中形成该轻掺杂漏极区域以及进行该等向性掺杂制程是分开进行的。
10.根据权利要求7所述的半导体元件的制造方法，其特征在于，还包含：
移除该栅极结构以形成一开口，该开口相邻于该栅极间隙壁；以及
形成一金属栅极结构于该开口中。
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