CN106816382B - 半导体器件的鳍结构及其制造方法和有源区域的制造方法 - Google Patents
半导体器件的鳍结构及其制造方法和有源区域的制造方法 Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Abstract
一种用于制造半导体器件的有源区域的方法包括在衬底中形成注入区域。该注入区域邻近衬底的顶面。对衬底的顶面实施清洗处理。烘烤衬底的顶面。在衬底的顶面上形成外延层。本发明的实施例还涉及半导体器件的鳍结构及其制造方法。
Description
技术领域
本发明的实施例涉及集成电路器件,更具体地,涉及半导体器件的鳍结构及其制造方法和有源区域的制造方法。
背景技术
随着集成电路不断地按比例缩小以及对集成电路的速度的要求越来越高,晶体管具有更高的驱动电流和更小的尺寸。因此,开发了鳍式场效应晶体管(FinFET)。FinFET晶体管具有增加的沟道宽度。通过形成包括位于鳍的侧壁上的部分以及位于鳍的顶面上的部分的沟道来获得沟道宽度的增加。由于晶体管的驱动电流与沟道的宽度成正比,因此增加了FinFET的驱动电流。
发明内容
本发明的实施例提供了一种用于制造半导体器件的有源区域的方法,包括:在衬底中形成注入区域,其中,所述注入区域邻近所述衬底的顶面;对所述衬底的所述顶面实施清洗处理;烘烤所述衬底的所述顶面;以及在所述衬底的所述顶面上形成外延层。
本发明的另一实施例提供了一种用于制造半导体器件的鳍结构的方法,包括:在衬底中形成注入区域;在包括含氢气体的环境中对所述衬底的顶面实施热处理;在所述衬底的所述顶面上沉积外延层;以及在所述外延层和所述衬底中形成至少一个沟槽以在所述衬底上形成至少一个鳍。
本发明的又一实施例提供了一种半导体器件的鳍结构,包括:衬底,在所述衬底中具有注入区域和多个沟槽,其中,所述沟槽限定至少一个底部鳍部分,所述底部鳍部分包括所述注入区域的至少部分;以及外延鳍部分,设置在所述底部鳍部分上,其中,所述底部鳍部分和所述外延鳍部分的界面的氧浓度低于1.E+19原子/立方厘米。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1A至图1G是根据本发明的一些实施例的处于各个阶段的用于制造半导体器件的鳍结构的截面图。
图2是根据本发明的一些实施例的表面处理的流程图。
图3是图2中的处于操作10(湿清洗工艺)、操作20(干清洗工艺)和操作30(烘烤工艺)的氧浓度的图。
图4是处于操作10和操作30的衬底的顶面上的缺陷的数量的图。
图5是用或没用图2中的操作30(烘烤工艺)的处理的图1C中的结构的氧浓度曲线的图。
图6A、图7、图8和图9A是根据本发明的一些实施例的处于各个阶段的用于制造使用图1G的鳍结构的半导体器件的方法的立体图。
图6B是一些实施例的图6A的半导体器件的截面图。
图9B是一些实施例的沿着图9A的线B-B截取的截面图。
图9C是一些实施例的沿着图9A的线C-C截取的截面图。
图10A是根据本发明的一些实施例的半导体器件的立体图。
图10B是一些实施例的沿着图10A的线B-B截取的截面图。
图10C是一些实施例的沿着图10A的线C-C截取的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
本发明的实施例提供了用于形成半导体器件的鳍结构的一些方法和最终的结构。如此处使用的,“鳍结构”指的是半导体材料,该半导体材料用作鳍式场效应晶体管的主体,其中,栅极电介质和栅极放置在鳍结构周围,从而使得电荷向下流动至鳍结构的两侧上的沟道并且可选择地沿着鳍结构的顶面流动。下面在块状硅衬底上形成具有单鳍或多鳍的finFET晶体管的鳍结构的上下文中讨论这些实施例。本领域中的普通技术人员应该意识到本发明的实施例可以使用其它的配置。
图1A至图1G是根据本发明的一些实施例的处于各个阶段的用于制造半导体器件的鳍结构的方法的截面图。参照图1A。提供了衬底110。在一些实施例中,衬底110可以由半导体材料制成。衬底110可以包括但是不限于块状硅、块状锗、块状硅锗合金或块状III-V族化合物半导体材料。在一些实施例中,衬底110包括未掺杂的块状硅。可以使用适用于半导体器件形成的其它材料。诸如石英、蓝宝石和玻璃的其它材料可以可选地用于衬底110。
在衬底110的顶面111上形成屏蔽层210。屏蔽层210可以防止衬底110受到随后的离子注入的损害。可以通过诸如化学汽相沉积(CVD)和/或原子层沉积(ALD)的沉积工艺形成屏蔽层210。CVD是在大于室温的温度下由于气态反应物之间的化学反应形成沉积的物质的沉积工艺;其中,在表面上沉积反应的固体产物,将在该表面上形成薄膜、涂层或固体产物的层。CVD的各个工艺包括但是不限于常压CVD(APCVD)、低压CVD(LPCVD)和等离子体增强CVD(EPCVD)、金属有机CVD(MOCVD)并且也可以采用它们的组合。可选地,可以使用诸如热氧化或热氮化的生长工艺形成屏蔽层210。在一些实施例中,通过CVD形成的屏蔽层210由诸如SiO2的氧化物制成。
之后,在屏蔽层210上形成图案化的掩模层220以用作离子注入掩模,并且在衬底110中形成穿过屏蔽层210和掩模层220的标记M。标记M可以使用蚀刻工艺形成并且配置为标记衬底110的位置。因此,可以根据标记M的位置确定衬底110中注入区域112的位置。在一些实施例中,标记M是如图1A所示的凹槽。然而,在一些其它实施例中,标记M可以是其它合适的配置,并且要求保护的范围不限于这个方面。
在一些实施例中,图案化的掩模层220可以是光刻胶,并且可以涂布在屏蔽层210上。之后,图案化光刻胶以形成具有开口222的图案化的掩模层220,开口222暴露衬底110上方的离子注入区。这样,例如,使用限定离子注入区的掩模,通过曝光和显影图案化光刻胶。在一些其它实施例中,图案化的掩模层220可以由其它合适的材料制成。
衬底110的顶面111使用诸如离子注入的工艺掺杂以形成注入区域112。术语“离子注入”是物理工艺,其中,掺杂剂原子被电离或隔离、加速、形成为光束并且目标是衬底110上。该离子穿透屏蔽层210并且残留在顶面111下方深度d处,其中,深度d由某些参数控制。注入区域112的深度d可以为从约20埃至约在一些实施例中,可以使用离子注入装置实施离子注入,其中,使用H、He、Ne、C、O、F、B、P或Si(包括它们的同位素)的至少一种。在一些实施例中,此处描述的半导体器件是P-沟道鳍式场效应晶体管(finFET),从而使得注入区域112是N-阱并且掺杂剂种类可以包括磷(P)或砷(As)。在一些其它实施例中,此处描述的半导体器件是N-沟道finFET,从而使得注入区域112是P-阱并且掺杂剂种类可以包括硼(B)。在一些其它实施例中,掺杂剂包括锗(Ge)、氙(Xe)、氩(Ar)、氪(Kr)或他们的组合。应该注意,其它的掺杂剂也是预期的并且在本发明的范围内。应该注意,如图1A所示,由于注入工艺的性质,注入区域112的边界可能不是尖锐边界,而是逐渐过渡的。
参照图1B。将离子注入至晶体材料(诸如晶体硅)可能引起缺陷。在一些实施例中,当顶面111被氧化时,氧离子可以与掺杂区域112中的掺杂剂反应并且形成氧化物化合物缺陷。其它缺陷可能是空位或间隙。空位是未由原子占据的晶格点。这是当离子与位于晶格中的原子碰撞时引起的,导致大量能量转移至原子,允许原子离开自己的晶位。当这些移位的原子或注入的离子停留在固体中但没有找到在晶格中驻留的未用空间时,产生间隙。这些点缺陷可以彼此迁移和聚集,导致位错环和其它缺陷。
为了去除这些缺陷(未示出),可以对衬底110的顶面111实施表面处理。图2是根据本发明的一些实施例的表面处理的流程图。参照图1B和图2。如操作10所示,对顶面111实施湿清洗工艺。湿清洗工艺可以从衬底110的顶面111上去除图1A的掩模层220和屏蔽层210。在一些实施例中,使用氢氟酸(HF)混合物。HF的浸泡可以使用介于大约50:1和1000:1之间(例如,基本介于100:1和500:1之间)的水:HF的比率的去离子超纯水中稀释的浓HF。在室温下实施介于约2分钟和约10分钟之间的HF浸泡。在一些实施例中,HF浸泡可以使用水和HF浴。在一些其他实施例中,可以利用水和HF清洗(例如,使用喷雾工具)。
如操作20所示,随后使用干蚀刻工艺以去除衬底110的顶面111上的氧化物层(未示出)。当将衬底110暴露至大气条件时,通常形成氧化物层。该氧化物层通常称为“原生”氧化物并且可以使用本领域中已知的各个工艺去除。例如,干蚀刻工艺可以用于去除原生氧化物。在一些实施例中,可以实施Siconi蚀刻。换句话说,含氟前体和含氢前体可以在远程等离子体区域中结合并且在等离子体中激活。Siconi蚀刻期间的原子流率H:F可以介于约0.5:1和约8:1之间以确保暴露的硅表面上的固体副产物的产生。因此,消耗了原生氧化物。
可选地,可以通过在衬底110中形成的氢等离子体去除原生氧化物。在实施例中,通过施加局部等离子体功率之上或约200瓦和之下或约3000瓦或之上或约300瓦和之下或约2000瓦来创建局部等离子体。无论使用的什么方法,在衬底110上形成外延层120(见图1C)的操作之前,去除原生氧化物(如果存在)。用于去除原生氧化物的技术可以在用于形成外延层120的衬底110的区域中执行,或可以在单独的室中实施这些工艺的每个工艺。然而,在单独的室之间的转移期间,衬底110不应该暴露于湿气或大气环境。
如操作30所示,随后实施烘烤工艺以进一步去除衬底110的顶面111上的缺陷。烘烤工艺可以去除顶面111上的原生氧化物以防止在衬底上形成的外延结构120(见图1C)上的晶体缺陷。在一些实施例中,烘烤工艺是原位烘烤工艺。原位意味着烘烤工艺在用于干清洗衬底110的顶面111的工艺室中实施。在一些其他实施例中,烘烤工艺可以在不同的室(或异位)中实施。
可以在含氢气体的存在下实施烘烤工艺。例如,含氢气体可以是氢气。烘烤温度可以在约750℃至约900℃的范围内。在一些其它实施例中,烘烤温度可以在约800℃至约900℃的范围内。在一些实施例中,氢气的压力可以介于约10托和约200托之间。例如,烘烤时间可以介于约30秒和约240秒之间。
术语“约”可以适用于修改任何定量的表示,这可能在没有引起相关的基本功能的变化的情况下改变。例如,此处公开的烘烤温度在从约750℃至约900℃的范围内,如果烘烤温度没有物理改变,可以允许烘烤温度稍低于750℃。
在烘烤工艺之后,减小了顶面111处的氧浓度,从而使得顶面111上的缺陷的量减小。图3是处于操作10(湿清洗工艺)、操作20(干清洗工艺)和操作30(烘烤工艺)的氧浓度的图。图4是处于操作10和操作30的顶面111上的缺陷的数量的图。在图3中,图的纵轴示出了氧浓度(原子/立方厘米),并且横轴示出了操作。在图4中,图的纵轴示出了缺陷的量(缺陷/每面积(ea.)),并且横轴示出了操作。如图3和图4所示,在烘烤顶面111之后,减小了其氧浓度,并且也减小了缺陷的数量。
参照图1C。在衬底110的顶面111上形成(或生长)外延层120。因此,顶面111是外延层120和衬底110的界面。在一些实施例中,外延层120的形成工艺是原位形成工艺。原位意味着形成工艺在用于烘烤衬底110的顶面111的工艺室中实施。在一些其它实施例中,形成工艺可以在不同的室(或异位)中实施。当标记M是凹槽时,外延层120也填充标记M。
外延层120和注入区域112可以是半导体器件的有源层。在一些实施例中,外延层120是未掺杂的,并且因此包括本征硅层。在一些实施例中,外延层120的厚度为从约50μm至约200μm。在一些其它实施例中,该厚度为从约75μm至约150μm。在仍一些其它实施例中,该厚度为约100μm至约125μm。
在一些实施例中,外延层120由硅制成。外延层120可以通过硅晶圆制造的领域中已知的各种方法沉积在衬底110的顶面111上。生长外延层的一些示例性方法涉及在反应器中加热衬底110至介于约1050℃和约1200℃之间;从反应器中清除HCl气体;以及使二氯硅烷和氢气在反应炉中反应以至少5μm/分钟的生长速率生长外延层120。在一些实施例中,三氯硅烷、四氯硅烷或许多其它硅烷基气体可以可选地用于代替二氯硅烷。
图5是用或没用图2中的操作30(烘烤工艺)的处理的图1C中的结构的氧浓度曲线的图。图5的纵轴示出了氧浓度(原子/立方厘米),并且横轴示出了图1C中的结构的深度。曲线C1表示用烘烤工艺的沿着深度的氧浓度,并且曲线C2表示没用烘烤工艺的沿着深度的氧浓度。如图5所示,当省略烘烤工艺时,界面(即,顶面111)处的氧浓度为约1.E+20原子/立方厘米。随着烘烤工艺的实施,界面处的氧浓度减小并且低于约1.E+19原子/立方厘米。在图5中,曲线C1的界面(即,顶面111)处的氧浓度为约1.E+18原子/立方厘米。
在图1C中,由于在干清洗工艺之后烘烤衬底110的顶面111,因此减小了顶面111中的缺陷的数量。由于顶面111中的这个较低的缺陷水平,当在衬底110上发生外延生长时,形成了没有成核扩展缺陷的高质量的外延层120,改进了引起光电性质的不想要的和突然的变化的位错问题。
参照图1D。在外延结构120的顶面121上方形成图案化的掩模层230和下面的保护层240。保护层240保护顶面121不与掩模层230直接接触。在一些实施例中,保护层240可以由热氧化物制成。保护层240的厚度在从约20nm至约100nm的范围内。在孔洞124的蚀刻期间,掩模层230协助保持图案的完整性。在一些实施例中,在过量的介电膜(填充下面的沟槽T)的去除期间,掩模层230用作平坦化停止层。在一些实施例中,掩模层230由SiN制成。然而,也可以使用诸如SiON、碳化硅或它们的组合的其它材料。掩模层230的厚度在从约200nm至约1200nm的范围内。可以通过诸如CVD、等离子体增强化学汽相沉积(PECVD)或LPCVD的工艺形成掩模层230。可选地,掩模层230可以先由氧化硅制成并且之后通过氮化转化为SiN。一旦形成,通过合适的光刻和蚀刻工艺图案化硬掩模层230和保护层240以在顶面121上方形成用于沟槽T的开口232和242。
之后,通过开口232和242在外延层120和衬底110中形成多个沟槽T。在邻近的两个沟槽T之间限定了半导体鳍102。半导体鳍102包括由外延层120形成的外延鳍部分126和由衬底110的注入区域112形成的底部鳍部分116。可以通过使用诸如反应离子蚀刻(RIE)的蚀刻工艺形成沟槽T。应该注意,虽然图1D中有两个半导体鳍102,但是本发明要求保护的范围不限于这个方面。在一些其它实施例中,本领域的普通技术人员可以根据实际情况制造半导体器件的合适数量的半导体鳍102。在一些实施例中,沟槽T的宽度W在从约20nm至约100nm的范围内。在一些实施例中,沟槽T的深度D在从约50nm至约350nm的范围内。在一些实施例中,高宽比,深度D除以宽度W,在从约5至约10的范围内。
参照图1E,之后,在沟槽T中共形地形成衬垫层130。在介电膜(将在以下描述)的热退火期间,衬垫层130提供应力缓解。在一些实施例中,衬垫层130包括非晶硅或多晶硅。衬垫层130的厚度可以介于约至约之间。可以通过在含Si2H6、SiH6、SiCl2H2或SiCl3H的气体环境中使用炉系统形成衬垫层130。在一些实施例中,Si2H6的流量可以在约10标准立方厘米每分钟(sccm)至约1000sccm的范围内。用于形成衬垫层130的温度在约200℃至约600℃的范围内。用于形成硅衬垫层130的压力范围为从约10毫托至约10托。可选地,可以通过在含Si3H8、SiH4、SiCl2H2或SiCl3H的气体环境中使用可以形成共形的硅层的沉积技术(诸如低温化学汽相沉积工艺)形成衬垫层130。气体环境也包括诸如氢气的载气。该载气有助于良好地控制处理均匀性。在一些实施例中,Si3H8和氢气的流量可以分别在约10sccm至约1000sccm的范围内以及在约5标准升每分钟(slm)至约50slm的范围内。用于在化学沉积工艺中形成衬垫层130的温度在约250℃至约550℃的范围内。
在一些其它实施例中,衬垫层130热生长在沟槽T的侧壁上。外延层120和衬底110暴露于高温下的含氧环境中并且暴露于氧气的表面转化为氧化物层。在一些实施例中,含氧环境包括蒸汽。衬垫层130可以包括位于热生长的氧化硅层上方的一个或多个附加层。在一些实施例中,可以使用等离子体增强原子层沉积(PEALD)来沉积附加氧化物层。根据各个实施例,衬垫层130形成为保护衬垫层130下面的外延层120和衬底110免受随后的氧化的影响。
在衬垫层130的沉积之后,介电材料过填充沟槽T和掩模层230以形成介电层140。在一些实施例中,介电材料是可流动的。可以通过使用旋涂电介质(SOD)形成工艺或通过诸如自由基组分CVD的CVD工艺沉积电介质来形成介电层140。前体的实例包括硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢-聚硅氮烷(PSZ)、正硅酸乙酯(TEOS)或甲硅烷基胺(SA)。
在一些实施例中,通过使用含硅前体与另一前体(诸如由等离子体产生的“氮自由基”前体)反应来沉积介电层140。在一些实施例中,含硅前体是无碳的并且包括诸如H2N(SiH3)、HN(SiH3)2、N(SiH3)3或它们的组合的甲硅烷基胺。甲硅烷基胺可以混合有可以用作载气、反应气或两者的附加气体。附加气体的实例可以包括H2、N2、NH3、He和Ar等气体。甲硅烷基胺也可以混合有诸如硅烷(SiH4)和乙硅烷(Si2H6)的其它无碳含硅气体、氢(例如,H2)和/或氮(例如,N2、NH3)。
可以在衬底110和外延层120的温度保持在相对较低的温度时进行介电层140的沉积。在一些实施例中,介电层140沉积在处于较低温度(沉积期间通过冷却衬底110和外延层120保持)的外延层120的顶面121之上。在一些实施例中,在从约-40℃至约200℃的范围内的温度下实施沉积。在一些实施例中,在小于约100℃的温度下实施沉积。
在一些实施例中,沉积压力在从约100毫托至约10托的范围内。在一些实施例中,反应源使用含三甲硅烷基胺(Si3H9N或TSA)和NH3的气体环境。在一些实施例中,Si3H9N和NH3的流量分别在约100sccm至约1000sccm的范围内以及约100sccm至约2000sccm的范围内。
在沉积工艺之后,对介电层140实施固化工艺。在一些实施例中,在约100标准立方厘米每分钟(sccm)至约5000sccm的范围内的O3的流量下操作固化工艺。用于固化工艺的温度在约10℃至约500℃的范围内。用于固化工艺的压力范围为从约1托至约760托。
随后,实施退火工艺。退火工艺可以进一步致密和改进介电层140的质量。在一些实施例中,在包含约5sccm至约20sccm的流量的蒸汽的环境中实施退火工艺。退火工艺处于约1000℃至约1200℃的范围内的温度。退火工艺开始于约200℃并且逐渐增加温度至约1000℃至约1200℃的预定的温度。在退火期间,介电层140可以由于致密而收缩。
参照图1F。通过诸如化学机械抛光(CMP)、蚀刻或它们的组合的工艺,去除沟槽T和掩模层230(见图1E)外部的过量的介电层140(见图1E)以在沟槽T中形成隔离层142。在一些实施例中,去除工艺也去除了图1E的保护层240。在一些其它实施例中,去除工艺去除了图1E的掩模层230;然而,通过蚀刻工艺去除保护层240。
参照图1G,实施蚀刻工艺以去除图1F的部分隔离层142直至到达预定的深度并且形成隔离结构144。之后,半导体鳍102突出高于隔离结构144。蚀刻工艺也可以蚀刻位于半导体鳍102的侧壁上的衬垫层130。因此,衬底110的顶面111(即,外延层120和衬底110的界面)低于隔离结构144。
在一些实施例中,蚀刻工艺可以是干蚀刻工艺以蚀刻图1F的隔离层142直至到达预定的深度。用于干蚀刻工艺的工艺气体可以包括氢原子(例如,使用氟化氢(HF)和氨(NH3)为基础的工艺气体)以蚀刻隔离层142。
图6A、图7、图8和图9A是根据本发明的一些实施例的处于各个阶段的使用图1G的鳍结构的用于制造半导体器件的方法的立体图,以及图6B是一些实施例的图6A的半导体器件的截面图。参照图6A和图6B,图6B和图1G具有基本相同的截面位置。栅极堆叠件150形成在部分半导体鳍102上并且暴露其它部分的半导体鳍102。由栅极堆叠件150覆盖的部分半导体鳍102形成沟道部件,并且未由栅极堆叠件105覆盖的其它部分的半导体鳍102形成源极/漏极部件。
栅极堆叠件105包括栅极绝缘层152和栅电极层154。栅极绝缘层152设置在栅电极层154和衬底110之间,并且形成在半导体鳍102上。例如,防止电子耗尽的栅极绝缘层152可以包括诸如金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐、金属氮氧化物、金属铝酸盐、硅酸锆、铝酸锆或它们的组合的高k介电材料。一些实施例可以包括氧化铪(HfO2)、氧化铪硅(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、氧化铪锆(HfZrO)、氧化镧(LaO)、氧化锆(ZrO)、氧化钛(TiO)、氧化钽(Ta2O5)、氧化钇(Y2O3)、钛酸锶(SrTiO3,STO)、钛酸钡(BaTiO3,BTO)、氧化钡锆(BaZrO)、氧化铪镧(HfLaO)、氧化镧硅(LaSiO)、氧化铝硅(AlSiO)、氧化铝(Al2O3)、氮化硅(Si3N4)、氮氧化硅(SiON)和它们的组合。栅极绝缘层152可以具有诸如一层氧化硅(例如,界面层)和另一层高k材料的多层结构。可以使用化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、热氧化、臭氧氧化、其它合适的工艺或它们的组合形成栅极绝缘层152。
在衬底110上方形成栅电极层154以覆盖栅极绝缘层152和部分半导体鳍102。在一些实施例中,栅电极层154包括诸如多晶硅、非晶硅等的半导体材料。栅电极层154可以是掺杂或未掺杂沉积的。例如,在一些实施例中,栅电极层154包括通过低压化学汽相沉积(LPCVCD)沉积的未掺杂的多晶硅。一旦施加,例如,该多晶硅可以掺杂有磷离子(或其它P-型掺杂剂)以形成PFET器件或可以掺杂有硼(或其它N-型掺杂剂)以形成NFET器件。例如,也可以通过原位掺杂多晶硅的炉沉积来沉积多晶硅。可选地,栅电极层154可以包括多晶硅金属合金或包括诸如钨(W)、镍(Ni)、铝(Al)、钽(Ta)、钛(Ti)或它们的任何组合的金属的金属栅极。
在一些实施例中,在栅电极层154的顶部有硬掩模层156,该硬掩模层156与光刻胶一起使用以图案化栅极堆叠件150。硬掩模层156可以由氧化物、氮化物或氧化物和氮化物的组合(双层硬掩模)制成。
在图6A中,在衬底110上方并且沿着栅极堆叠件150和硬掩模层156的侧面形成一对介电层160。在一些实施例中,介电层160可以包括氧化硅、氮化硅、氮氧化硅或其它合适的材料。介电层160可以包括单层或多层结构。可以通过CVD、PVD、ALD或其它合适的技术形成介电层160的毯状层。之后,对毯状层实施各向异性蚀刻以在栅极堆叠件150的两侧上形成一对介电层160。在一些实施例中,介电层160用于偏移随后形成的诸如源极/漏极区域的掺杂的区域。介电层160可以进一步用于设计或修改源极/漏极区域(结点)的轮廓。
参照图7,沿着半导体鳍102形成多个侧壁间隔件170。侧壁间隔件170可以包括诸如氧化硅的介电材料。可选地,侧壁间隔件170可以包括氮化硅、SiC、SiON或它们的组合。用于侧壁间隔件170的形成方法包括在半导体鳍102上方沉积介电材料,并且之后,各向异性回蚀刻介电材料。回蚀刻工艺可以包括多步骤蚀刻以获得蚀刻选择性、灵活性和期望的过蚀刻控制。
参照图8,去除(或凹进)由栅极堆叠件150和介电层160暴露的部分半导体鳍102以形成凹进的沟槽172。在一些实施例中,形成的凹进的沟槽172用侧壁间隔件170作为它们的上部。在一些实施例中,凹进的沟槽172的侧壁基本彼此竖直平行。在一些其它实施中,凹进的沟槽172形成为具有非竖直平行的轮廓。
凹进工艺可以包括干蚀刻工艺、湿蚀刻工艺和/或它们的组合。凹进工艺也可以包括选择性湿蚀刻或选择性干蚀刻。湿蚀刻溶液包括四甲基氢氧化铵(TMAH)、HF/HNO3/CH3COOH溶液或其它合适的溶液。干蚀刻工艺和湿蚀刻工艺具有可以调节的蚀刻参数,诸如使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻压力、源功率、RF偏置电压、RF偏置功率、蚀刻流率或其它合适的参数。例如,湿蚀刻溶液可以包括NH4OH、KOH(氢氧化钾)、HF(氢氟酸)、TMAH(四甲基氢氧化铵)、其它合适的湿蚀刻溶液或它们的组合。干蚀刻工艺包括使用氯基化学物的偏置等离子体蚀刻工艺。其它干蚀刻气体包括CF4、NF3、SF6和He。也可以使用诸如DRIE(深反应离子蚀刻)的机制各向异性地实施干蚀刻。
参照图9A至图9C,其中,图9B是一些实施例的沿着图9A的线B-B截取的截面图,以及图9C是一些实施例的沿着图9A的线C-C截取的截面图。在凹进的沟槽172(见图8)之上形成(或生长)多个外延结构180。通过外延生长半导体材料形成外延结构180。半导体材料包括诸如锗(Ge)或硅(Si)的单元素半导体材料;或诸如砷化镓(GaAs)、砷化铝镓(AlGaAs)的化合物半导体材料;或诸如硅锗(SiGe)、磷砷化镓(GaAsP)的半导体合金。外延结构180具有合适的晶向(例如,(100)、(110)或(111)晶向)。在一些实施例中,外延结构180包括源极/漏极外延结构。在一些实施例中,其中,当期望的是PFET器件时,外延结构180可以包括外延生长的硅锗(SiGe)。外延工艺包括CVD沉积技术(例如,汽相外延(VPE)和/或超高真空CVD(UHV-CVD)),分子束外延和/或其它合适的工艺。
在一些实施例中,半导体器件是PFET器件,并且外延结构180具有小平面,每个小平面均具有(111)晶向。至少一个外延结构180具有多个部分(即,第一部分182、第二部分184和第三部分186),每个部分均具有不同的浓度。例如,如果外延结构180由SiGe制成,则第一部分182的Ge浓度范围为从约10%至约35%,第二部分184的Ge浓度范围为从约30%至约55%,以及第三部分186的Ge浓度范围为从约15%至约30%,并且要求保护的范围不限于这个方面。
图10A是根据本发明的一些实施例的半导体器件的立体图,图10B是一些实施例的沿着图10A的线B-B截取的截面图,以及图10C是一些实施例的沿着图10A的线C-C截取的截面图。图10A和图9A的半导体器件之间的不同在于外延结构。在图10A中,半导体器件是N-型FET(FET)器件,并且外延结构190具有圆形表面。当期望的是N-型FET(NFET)时,外延结构190可以包括外延生长的硅磷(SiP)。此外,至少一个外延结构190具有多个部分(即,第一部分192、第二部分194和第三部分196),每个部分均具有不同的浓度。例如,如果外延结构190由SiGe制成,第一部分192的P浓度范围为从约7E20至约1E21,第二部分194的P浓度范围为从约1E21至约3.5E21,并且第三部分196的P浓度范围为从约7E20至约3E21。由于图10A至图10C的半导体器件的其它结构细节类似于图9A至图9C,并且因此,不再重复它们的描述。
根据上述实施例,由于在干清洗工艺之后,烘烤衬底的顶面,因此减小了顶面中的缺陷的数量。由于顶面中的这种较低缺陷水平,当在衬底上采取外延生长时,可以形成高质量的外延层而没有扩展缺陷的成核。
根据一些实施例,用于制造半导体器件的有源区域的方法包括在衬底中形成注入区域。该注入区域邻近衬底的顶面。对衬底的顶面实施清洗处理。烘烤衬底的顶面。在衬底的顶面上形成外延层。
在上述方法中,其中,在750℃至900℃的范围内的温度下实施所述烘烤。
在上述方法中,其中,所述烘烤是氢烘烤工艺。
在上述方法中,其中,所述注入区域包括硼(B)、磷(P)或它们的组合。
在上述方法中,其中,所述清洗处理包括湿清洗工艺。
在上述方法中,其中,所述清洗处理包括干清洗工艺。
在上述方法中,其中,所述清洗处理包括干清洗工艺,所述干清洗工艺是Siconi蚀刻工艺。
在上述方法中,其中,烘烤工艺是原位烘烤工艺。
在上述方法中,其中,所述外延层的形成工艺是原位形成工艺。
根据一些实施例,用于制造半导体器件的鳍结构的方法包括在衬底中形成注入区域。在包括含氢气体的环境中对衬底的顶面实施热处理。外延层沉积在衬底的顶面上。在外延层和衬底中形成至少一个沟槽以在衬底上形成至少一个鳍。
在上述方法中,其中,在750℃至900℃范围内的温度下实施所述热处理。
在上述方法中,还包括:在实施所述热处理之前,清洗所述衬底的所述顶面。
在上述方法中,其中,所述热处理包括降低所述衬底的所述顶面处的氧浓度。
在上述方法中,还包括:在所述沟槽中形成隔离层。
在上述方法中,还包括:在所述沟槽中形成隔离层,去除部分所述隔离层以在所述沟槽中形成隔离结构。
根据一些实施例,半导体器件的鳍结构包括衬底和外延鳍部分。该衬底中具有注入区域和多个沟槽。该沟槽限定了包括至少部分注入区域的至少一个底部鳍部分。外延鳍部分设置在衬底的底部鳍部分上。底部鳍部分和外延鳍部分的界面的氧浓度低于约1.E+19原子/立方厘米。
在上述鳍结构中,其中,所述注入区域包括硼(B)、磷(P)或它们的组合。
在上述鳍结构中,还包括:隔离结构,设置在至少一个所述沟槽中。
在上述鳍结构中,还包括:隔离结构,设置在至少一个所述沟槽中,其中,所述外延鳍部分高于所述隔离结构。
在上述鳍结构中,还包括:隔离结构,设置在至少一个所述沟槽中,其中,所述底部鳍部分和所述外延鳍部分的所述界面低于所述隔离结构。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (20)
1.一种用于制造半导体器件的有源区域的方法,包括:
在衬底中形成注入区域,其中,所述注入区域邻近所述衬底的顶面;
对所述衬底的所述顶面实施清洗处理;
烘烤所述衬底的所述顶面;
在所述衬底的所述顶面上形成外延层;以及
在所述外延层和所述衬底中形成至少一个沟槽以在所述衬底上形成至少一个鳍,其中,所述注入区域包括形成所述至少一个鳍的底部鳍部分的上部和位于所述衬底中的下部,所述外延层位于所述底部鳍部分上方的部分构成所述鳍的外延鳍部分,
在所述有源区域的源/漏极外延结构处,所述外延鳍部分位于所述底部鳍部分与所述源/漏极外延结构之间,
所述源/漏极外延结构具有多个子部分,每个子部分中组分的浓度不同。
2.根据权利要求1所述的方法,其中,在750℃至900℃的范围内的温度下实施所述烘烤。
3.根据权利要求1所述的方法,其中,所述烘烤是氢烘烤工艺。
4.根据权利要求1所述的方法,其中,所述注入区域包括硼(B)、磷(P)或它们的组合。
5.根据权利要求1所述的方法,其中,所述清洗处理包括湿清洗工艺。
6.根据权利要求1所述的方法,其中,所述清洗处理包括干清洗工艺。
7.根据权利要求6所述的方法,其中,所述干清洗工艺是Siconi蚀刻工艺。
8.根据权利要求1所述的方法,其中,烘烤工艺是原位烘烤工艺。
9.根据权利要求1所述的方法,其中,所述外延层的形成工艺是原位形成工艺。
10.一种用于制造半导体器件的鳍结构的方法,包括:
在衬底中形成注入区域;
在包括含氢气体的环境中对所述衬底的顶面实施热处理;
在所述衬底的所述顶面上沉积外延层;以及
在所述外延层和所述衬底中形成至少一个沟槽以在所述衬底上形成至少一个鳍,其中,所述注入区域包括形成所述鳍的底部鳍部分的上部和位于所述衬底中的下部,所述外延层位于所述底部鳍部分上方的部分构成所述鳍的外延鳍部分,
在所述鳍上的源/漏极外延结构处,所述外延鳍部分位于所述底部鳍部分与所述源/漏极外延结构之间,
所述源/漏极外延结构具有多个子部分,每个子部分中组分的浓度不同。
11.根据权利要求10所述的方法,其中,在750℃至900℃范围内的温度下实施所述热处理。
12.根据权利要求10所述的方法,还包括:在实施所述热处理之前,清洗所述衬底的所述顶面。
13.根据权利要求10所述的方法,其中,所述热处理包括降低所述衬底的所述顶面处的氧浓度。
14.根据权利要求10所述的方法,还包括:
在所述沟槽中形成隔离层。
15.根据权利要求14所述的方法,还包括:
去除部分所述隔离层以在所述沟槽中形成隔离结构。
16.一种半导体器件的鳍结构,包括:
衬底,在所述衬底中具有注入区域和多个沟槽,其中,所述沟槽限定至少一个底部鳍部分,其中,所述注入区域包括形成鳍的底部鳍部分的上部和位于所述衬底中的下部;以及
外延鳍部分,设置在所述底部鳍部分上,其中,所述底部鳍部分和所述外延鳍部分的界面包括氧并且氧浓度低于1.E+19原子/立方厘米,
在所述鳍上的源/漏极外延结构处,所述外延鳍部分位于所述底部鳍部分与所述源/漏极外延结构之间,
所述源/漏极外延结构具有多个子部分,每个子部分中组分的浓度不同。
17.根据权利要求16所述的鳍结构,其中,所述注入区域包括硼(B)、磷(P)或它们的组合。
18.根据权利要求16所述的鳍结构,还包括:
隔离结构,设置在至少一个所述沟槽中。
19.根据权利要求18所述的鳍结构,其中,所述外延鳍部分高于所述隔离结构。
20.根据权利要求18所述的鳍结构,其中,所述底部鳍部分和所述外延鳍部分的所述界面低于所述隔离结构。
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US10026843B2 (en) | 2018-07-17 |
US20180342621A1 (en) | 2018-11-29 |
TWI590314B (zh) | 2017-07-01 |
KR20170119315A (ko) | 2017-10-26 |
US10811537B2 (en) | 2020-10-20 |
DE102016100087A1 (de) | 2017-06-01 |
US11749756B2 (en) | 2023-09-05 |
KR20170077753A (ko) | 2017-07-06 |
US20210050451A1 (en) | 2021-02-18 |
DE102016100087B4 (de) | 2024-07-18 |
US20230378361A1 (en) | 2023-11-23 |
KR101849499B1 (ko) | 2018-05-28 |
CN106816382A (zh) | 2017-06-09 |
US20170154996A1 (en) | 2017-06-01 |
TW201719731A (zh) | 2017-06-01 |
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