CN106575628A - 功率模块 - Google Patents

功率模块 Download PDF

Info

Publication number
CN106575628A
CN106575628A CN201580043705.4A CN201580043705A CN106575628A CN 106575628 A CN106575628 A CN 106575628A CN 201580043705 A CN201580043705 A CN 201580043705A CN 106575628 A CN106575628 A CN 106575628A
Authority
CN
China
Prior art keywords
copper
aluminum
electrode
metal plate
power model
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201580043705.4A
Other languages
English (en)
Other versions
CN106575628B (zh
Inventor
藤野纯司
内田祥久
小川翔平
坂元创
坂元创一
柳本辰则
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN106575628A publication Critical patent/CN106575628A/zh
Application granted granted Critical
Publication of CN106575628B publication Critical patent/CN106575628B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29123Magnesium [Mg] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754Coating
    • H01L2224/37599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/43Manufacturing methods
    • H01L2224/438Post-treatment of the connector
    • H01L2224/43848Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45014Ribbon connectors, e.g. rectangular cross-section
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48475Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48491Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49433Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85053Bonding environment
    • H01L2224/85054Composition of the atmosphere
    • H01L2224/85075Composition of the atmosphere being inert
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Abstract

关于使铝与铜重叠而进行压焊而成的包层材料,通过利用超声波接合等将包层材料的铝侧接合于功率半导体元件的电极表面并在包层材料的铜侧进行线接合,而形成电路。进而预先在比功率半导体元件的动作温度高的温度下对包层材料进行热处理,从而在接合处理后在铝以及铜的各个界面充分地形成金属间化合物,以避免膜厚生长。

Description

功率模块
技术领域
本发明涉及在从发电或者输电至有效的能量的利用或者再生为止的所有情况下利用的功率模块。
背景技术
在从产业设备至家电或者信息终端的所有产品中,功率模块正在普及,且关于搭载于家电的模块,要求小型轻量化,并且要求能够应对多种类的高的生产率和高的可靠性。另外,在动作温度高、效率优良这点,也同时要求是能够应用于成为今后的主流的可能性高的SiC半导体的封装形态。
专利文献1:日本特开平10-261664号公报
专利文献2:日本特开2012-28674号公报
非专利文献1:謝、他2名、“アルミニウム/銅クラッド材接合界面における金属間化合物の形成”、日本金属学会誌、公益社団法人日本金属学会、2011年3月、第75巻、第3号、pp.166-172(谢,其他2名,“铝/铜包层(clad)材料接合界面处的金属间化合物的形成”,日本金属学会杂志,公益社团法人日本金属学会,2011年3月,第75卷,第3号,pp.166-172)
发明内容
功率模块具有处理100V以上的高压且100A以上的大电流的半导体这样的特征,为了形成100A以上的大电流电路,一般针对功率半导体元件表面的电极,对多根粗至φ0.5mm的铝等的接合线进行布线,从而形成电路。从近年的全球变暖对策、节省资源或者能量等环境问题出发,在将功率模块应用于各种各样的产品的过程中,为了应对100A以上的大电流并且实现与以往相比更加小型化,使用与铝线相比耐热性高、电流容量大的铜制的线的线接合的必要性正逐渐变高。但是,铜线比铝线硬而难以变形,所以担心在线接合时,发生功率半导体元件的表面电极的剪切破坏等损坏。另外,即使在克服了元件的损坏的问题的情况下,也存在如下问题:在如SiC制功率半导体元件那样动作温度高达250℃以上等的情况下,接合部界面处的热应力随着动作温度而变大,从而难以确保抗温度循环性等可靠性。
在专利文献1中,提出了如下方法:想要通过将铝箔放置在功率半导体元件表面并从其上进行铜线接合,减轻对功率半导体元件的损坏。在该方法中有可能能够解决损坏的问题,但如果铝自身暴露于175℃以上的高温,则担心由于再结晶所致的结晶的粗大化而晶界表面化,成为裂纹的起点以至于破裂。
在专利文献2中,提出了如下方法:通过将膨胀系数(α1)接近功率半导体元件(Si)的缓冲板A和膨胀系数(α2)接近线的缓冲板B配置在功率半导体元件与线之间,减轻线接合时的膨胀系数的不同所致的歪斜产生等损坏,同时降低在接合部产生的热应力,在高温动作时确保可靠性。在该方法中,由于通过焊接来层叠缓冲板,所以担心抗温度循环性等、在长的期间中焊接部的耐热性不足。
本发明的功率模块具备:
基板;
功率半导体元件,配置于该基板;
电极,形成在该功率半导体元件的表面;
层叠金属板,与该电极接合;以及
线,连接该层叠金属板和所述基板,
所述功率模块的特征在于,
所述层叠金属板构成为与所述电极对置的部件的主要材质与所述电极相同,与所述线对置的部件的主要材质与所述线相同,并且
在所述层叠金属板之间以5μm以上且100μm以下的厚度形成有金属间化合物层。
根据本发明,通过将使铝与铜重叠而进行压焊而成的包层材料作为缓冲板发挥作用,能够降低铜线接合时的对功率半导体元件的损坏。与铜相比再结晶温度低、耐热性低的铝不在表面(与密封树脂相接的面)露出,所以即使保持为比以往的Si功率半导体元件的动作温度高的温度,也不易出现结晶的粗大化所致的脆化的影响。另外,包层材料的铝侧与功率半导体元件的铝电极接合,在包层材料的铜侧进行铜线接合,避免异种金属接合,从而能够在装配后的半导体动作时抑制金属间化合物的生成所致的脆化,抑制热应力所致的裂纹发生等。另外,关于包层材料自身的接合部处的金属间化合物的生成所致的脆化等,另行确认了没有问题(参照非专利文献1)。
附图说明
图1是示出本发明的实施方式1的功率模块的剖面的概念图。
图2是示出本发明的实施方式1的功率模块的基于切割器的铝铜包层带的切断状态的剖面的概念图。
图3是示出将本发明的实施方式1的功率半导体元件的主电极和基板的导体层用线电连接的状态的一个例子的功率模块的剖面的概念图。
图4是图3的平面图。
图5是图3的A部放大图。
图6是金属间化合物的生长不均匀的情况下的模型图。
图7是示出将图4的线代替为带的情况下的一个例子的图。
图8是示出本发明的实施方式2的功率模块的剖面的概念图。
图9是示出本发明的实施方式2的功率模块的基于切割器的铝铜包层带的切断状态的剖面的概念图。
图10是示出将本发明的实施方式2的功率半导体元件的主电极和基板的导体层用线电连接的状态的一个例子的功率模块的剖面的概念图。
图11是图10的平面图。
符号说明
1:功率半导体元件;2:陶瓷基板;3:铝铜包层带;4:超声波接合工具;5:焊料;6:铜线;11:主电极;21:氧化铝基材;22、23:导体层;31:铜箔;32:铝箔;33:接合部;34:金属间化合物层;40:切割器;41:接合痕;61:铜带。
具体实施方式
实施方式1.
图1~图5、图7是实施方式1的功率模块的概念图。如图1所示,通过焊料5将功率半导体元件1接合于陶瓷基板2(厚度为0.635mm的氧化铝基材21)的导体层22(铜制,厚度为0.4mm。不是图1的构成陶瓷基板2的下侧的导体层23,而是上侧的导体层)上。使用作为层叠金属板的铝铜包层带3(铜箔31(厚度为0.05mm)与铝箔32(厚度为0.2mm)重叠而成的带,宽度为10mm),在功率半导体元件(Si制二极管12mm×12mm×0.3mm)的主电极(铝制,11mm×11mm×0.01mm)11上被定位,通过超声波接合工具4(前端2mm×2mm×20mm)施加超声波而形成接合部33。即,使用使铝与铜重叠而进行压焊而成的包层材料,通过超声波接合等将该包层材料的铝侧接合于功率半导体元件的电极表面,在包层材料的铜侧进行线接合,从而形成电路。
接下来,如图2所示,使用切割器40(包括机械式的切割器)仅将铜箔31完全切断,在铝箔32的厚度方向中途停止而切开,在功率半导体元件上将铝铜包层带3切断。
最后,如图3所示,使用铜线(φ0.4mm)进行线接合,最终将功率半导体元件的主电极与陶瓷基板的导体层电连接。
图4是图3的俯视图,通过利用超声波接合工具将铝铜包层带的9个部位接合,从而形成有9个部位的由工具前端的网纹(用于增大摩擦的纵横的凹陷)转印的接合痕41,通过使用之间的平坦的部分进行铜线的线接合,能够抑制接合痕的凹凸对接合质量的影响。
图5是图3的铝铜包层带的A部放大图,预先在惰性环境下在温度400℃的条件下加热3小时,在铝与铜之间形成铝与铜的金属间化合物层34。虽然根据功率模块的动作温度或者质量保证期间而不同,但根据非专利文献1(参照例如图10),只要通过400℃、3小时的加热来生成金属间化合物,则成为与在200℃下保持了3000小时的金属间化合物同等的金属间化合物厚度,之后,即使保持为200℃,由于化合物的生长与时间的平方根成比例(根据阿累尼乌斯曲线(Arrhenius plot),每隔40℃而金属间化合物的生成速度(厚度)变小至50%,所以认为如果在400℃与200℃下差200℃,则变薄至1/32。为了生长到32倍的厚度需要32倍的平方的时间,所以需要约1000倍的时间),所以仍变得极稳定(参照例如非专利文献1的第170页的说明)。
热处理通过烘箱或者连续炉等实施,如果考虑为在比铝的熔点低的温度下进行,则上限为600℃。通过10秒的加热,铝与铜之间的金属间化合物变为5μm的厚度,但如果是该厚度,则相当于200℃下的0.32年的热经历,如果考虑功率模块的放置的环境和产品寿命,则可以说是充分的。
另外,通常使用的线接合用的最大直径的铝线是0.5mm,在电流容量方面置换其所需的铝铜包层带的厚度为0.2mm。被认为如果存在超过厚度的1/2的金属间化合物,则变脆,从而在环路形成时发生破裂等。
即,在通过超声波接合等将包层材料的铝侧接合于功率半导体元件的电极表面之后,进而在比功率模块的动作温度高的温度下预先对包层材料进行热处理,从而在接合处理后在铝以及铜的各个界面充分地形成金属间化合物,以避免膜厚进一步生长。
另外,在上述金属间化合物层34原本没有或者不充分的情况下,在铝铜包层带与主电极之间的接合部33和未接合部,在半导体动作时产生温度分布,所以例如如图6所示,在铜和铝之间的金属间化合物的生长速度中产生差值,金属间化合物进行不均匀的厚度方向的生长(参照在图6的厚度方向进行了不均匀的生长的金属间化合物35),所以存在对表面的铜线接合接合部产生影响的可能性。即,存在在由图6的虚线包围的部分B处铜线6剥离的担心。
此处使用了上述所示的厚度为0.25mm的铝与铜的包层带,但即使是具有与铝同等的柔软性的其它金属(镁、锡、铟)与铜的组合也能够得到抑制线接合损坏的效果。
另外,关于厚度,如果铝为0.05mm以上,则能够进行切割器的半切割等、不损伤半导体的电极的切断(使用的带的最薄的部分的厚度为0.05mm,能够利用装置进行半切割),如果达到1mm左右的厚度,则能够进行良好的超声波接合和切断。
关于另一方的铜,另行确认了如果厚度为0.05mm以上,则能够针对通常的铜线接合进行不使变形传递到下层的铝的切断。同样地,如果为0.2mm以下,则能够进行超声波接合和半导体元件上的切断。关于铝与铜的厚度的比率,认为相比于1:1,在铜更薄的情况下超声波接合更容易。但是,无需限定于此。
此处,使用了铝铜包层带,但即使使用预先以各边比半导体元件的表面电极各小1mm的尺寸切断而成的单片状的包层材料,也能够得到同样的效果。另外,此处使用了氧化铝陶瓷基板,但即使是氮化铝或者氮化硅等陶瓷基板也能够得到同样的效果。另外,使用了铜作为导体层,但即使使用铝导体层的陶瓷基板也能够得到同样的效果。另外,针对引线框架,即使进行功率半导体元件的片接合或者线接合也能够得到同样的效果。
另外,此处,使用了二极管作为功率半导体元件,但对于IGBT(Insulated GateBipolar Transistor,绝缘栅双极晶体管)也能够以同样的结构编入。另外,此处,使用了铜制的电极板,但即使使用铝制或者CIC(铜铟包层材料,copper-Inver-copper)制板材也能够得到同样的效果。
另外,此处,采用通过切割器将铜完全切断而使铝分离的工序,但即使切断至铜的板厚的中途,也能够在之后的工序中分离,所以能够同样地进行带的切断,能够减轻对功率半导体元件的损坏。另外,通过在带处形成V槽,能够易于切断,能够不对半导体元件造成损坏地实施芯片上的带切断。
另外,此处,分别将比功率半导体元件的表面电极(11mm见方,厚度为0.01mm)小的前端形状(2mm见方,长度为20mm)的(未图示)超声波接合工具抵接于多个部位,制作出多个接合部,但即使通过使用在工具表面部分地形成有网纹的(分散地形成9个部位)超声波接合工具而将整个面一次接合,也能够得到同样的效果。该方法在削减工时上是更有利的。
另外,此处使用铜线接合进行电路形成,但即使如图7所示使用铜带61(宽度为2mm、厚度为0.2mm),也能够得到同样的效果。在该情况下,与铜线相比,铜带的剖面面积变大,所以电流容量增加,焦耳热减少,能够提高可靠性。
另外,此处,通过对铝铜包层带进行超声波接合而接合于功率半导体元件上,但通过基于加热加压压焊、真空接合或者导电性粘接剂的接合等也能够得到同样的效果。
另外,通过在层叠金属板的金属界面预先通过热处理来形成金属间化合物层,从而使半导体装置的基于使用环境的金属间化合物的生成变稳定,由此能够减小特性的变化,确保可靠性。
进而,构成层叠金属板的两层的部件中的、与半导体元件的表面相接的第一部件是与半导体元件的表面电极大致相同的组成,与铜线相接的第二部件是与铜线大致相同的组成,所以能够抑制接合处理或者比半导体的动作温度高的温度的动作时的金属扩散所伴随的脆的金属间化合物层的生成。另外,不使耐热性低的第一部件在线接合界面附近的表面(与密封树脂相接的面)露出,能够抑制由于因结晶的粗大化所致的脆化而产生裂纹的起点。
实施方式2.
图8~图11是实施方式2的功率模块的概念图。如图8所示,通过焊料5将功率半导体元件1接合于陶瓷基板2(厚度为0.657mm的氧化铝基材21)的导体层22(铜制厚度为0.4mm)上。使用铝铜包层带3(在铝箔32(厚度为0.2mm、宽度为2mm)上重叠宽度为2mm、狭缝为3mm的条状的铜箔31而成的宽度为10mm的带),在功率半导体元件(Si制二极管12mm×12mm×0.3mm)的主电极(铝制,11mm×11mm×0.01mm)11上被定位,通过超声波接合工具4(前端2mm×2mm×20mm)施加超声波,在没有铜图案的部分形成接合部33。
接下来,如图9所示,使用切割器40(包括机械式的切割器)仅将铜箔31完全切断,在铝箔32的中途停止而切开,与图2同样地,在功率半导体元件上切断铝铜包层带3。
最后,如图10那样,使用铜线(φ0.4mm)进行线接合,将功率半导体元件的主电极与陶瓷基板的导体层电连接。图11是图10的俯视图,通过利用超声波接合工具接合包层带的铝部分的9个部位,从而形成有9个部位的由工具前端的网纹(用于增大摩擦的纵横的凹陷)转印的接合痕41,通过使用之间的铜图案部分进行铜线的线接合,能够使带接合的载荷或者接合时间等超声波接合条件变稳定(较小载荷、短时间接合的条件),降低对功率半导体元件的损坏,抑制接合痕的凹凸所致的接合面积的增减等对接合质量的影响。
铝铜包层带预先在惰性环境下在温度为400℃的条件下被加热3小时,在铝与铜之间形成金属间化合物层34。虽然根据功率模块的动作温度或者质量保证期间而不同,但成为与在200℃下保持3000小时的金属间化合物同等的金属间化合物厚度,之后,即使保持为200℃,由于化合物的生长与时间的平方根成比例(参照非专利文献1),所以仍变得极稳定。
此处使用了规定的厚度为0.25mm的铝与铜的包层带,但即使是具有与铝同等的柔软性的其它金属(镁、锡、铟)与铜的组合,也能够得到抑制线接合损坏的效果。
另外,关于厚度,如果铝为0.05mm以上,则能够进行切割器的半切割切断等、不损伤半导体的电极的切断,如果达到1mm左右的厚度,则一般能够进行良好的超声波接合和切断。
另一方面,关于铜,一般如果为0.05mm以上,则能够针对通常的铜线接合,不使变形传递到下层的铝,关于铝与铜的厚度的比率,认为相比于1:1,在铜更薄的情况下,由于容易变形的铝的厚度比铜大,所以超声波接合更容易,但无需限定于此。
此处,使用了铝铜包层带,但即使使用预先以规定的大小即各边比半导体元件的表面电极各小1mm的尺寸切断而成的单片状的包层材料,也能够得到同样的效果。另外,此处使用了氧化铝陶瓷基板,但即使是氮化铝或者氮化硅等陶瓷基板也能够得到同样的效果。进而,使用铜作为导体层,但即使使用铝导体层的陶瓷基板也能够得到同样的效果。
此处使用了二极管作为功率半导体元件,但对于以IGBT(Insulated GateBipolar Transistor绝缘栅双极型晶体管)为首的晶体管元件也能够以同样的结构编入。
另外,此处,采用通过切割器将铜完全切断而使铝分离的工序,但即使切断至铜的板厚的中途也能够同样地进行带的切断,能够减轻对功率半导体元件的损坏。
另外,此处,将比功率半导体元件的表面电极(11mm见方,厚度为0.01mm)小的前端形状(2mm见方,长度为20mm)的超声波接合工具抵接于多个部位,制作出多个接合部,但即使通过使用在工具表面部分地形成有网纹的超声波接合工具而将整个面一次接合,也能够得到同样的效果。
进而,此处将铜图案做成条状,但即使做成水珠花样或者格子旗状也能够得到同样的效果。另外,此处,铜图案是通过利用蚀刻等从铝铜包层带的状态除去不需要的部分而制作的,但即使使用预先图案化的铜来进行轧制、包层化,也能够得到同样的效果。在该情况下,成为没有表面的凹凸的(铜图案埋没于铝)状态,但不影响到接合性,所以不会特别成为问题。另外,本发明能够在其发明的范围内将各实施方式自由地组合,或者能够适当地对各实施方式进行变形、省略。

Claims (6)

1.一种功率模块,具备:
基板;
功率半导体元件,配置于该基板;
电极,形成在该功率半导体元件的表面;
层叠金属板,与该电极接合;以及
线,连接该层叠金属板和所述基板,
所述功率模块的特征在于,
所述层叠金属板构成为与所述电极对置的部件的主要材质与所述电极相同,与所述线对置的部件的主要材质与所述线相同,并且
在所述层叠金属板之间以5μm以上且100μm以下的厚度形成有金属间化合物层。
2.根据权利要求1所述的功率模块,其特征在于,
所述层叠金属板在与所述电极接合之前,预先在比所述功率模块的动作温度高的温度下被热处理。
3.根据权利要求1或者2所述的功率模块,其特征在于,
所述层叠金属板的与所述线对置的部件部分地层叠于与所述电极对置的部件。
4.根据权利要求1至3中的任意一项所述的功率模块,其特征在于,
所述线是宽度与所述功率半导体元件的电极同等的带形状或者宽度比所述功率半导体元件的电极小的薄板状。
5.根据权利要求1至4中的任意一项所述的功率模块,其特征在于,
所述层叠金属板的与所述电极对置的部件是以铝为主的组成,与所述线对置的部件是以铜为主的组成。
6.根据权利要求1至5中的任意一项所述的功率模块,其特征在于,
所述层叠金属板的与所述电极对置的部件的材质是镁、锡、铟中的任意的材质。
CN201580043705.4A 2014-10-20 2015-10-09 功率模块 Active CN106575628B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014-213377 2014-10-20
JP2014213377 2014-10-20
PCT/JP2015/078719 WO2016063744A1 (ja) 2014-10-20 2015-10-09 パワーモジュール

Publications (2)

Publication Number Publication Date
CN106575628A true CN106575628A (zh) 2017-04-19
CN106575628B CN106575628B (zh) 2019-02-15

Family

ID=55760788

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580043705.4A Active CN106575628B (zh) 2014-10-20 2015-10-09 功率模块

Country Status (5)

Country Link
US (1) US9818716B2 (zh)
JP (1) JP6320556B2 (zh)
CN (1) CN106575628B (zh)
DE (1) DE112015004770B4 (zh)
WO (1) WO2016063744A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109244057A (zh) * 2018-07-13 2019-01-18 北京大学深圳研究生院 一种封装基板及基于该基板形成的共源共栅氮化镓器件
CN112002645A (zh) * 2020-06-24 2020-11-27 西安理工大学 一种提高SiC功率芯片键合线功率循环能力的方法
CN112201628A (zh) * 2020-08-24 2021-01-08 株洲中车时代半导体有限公司 一种功率模块封装结构及其制备方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107615464B (zh) * 2015-06-11 2020-03-17 三菱电机株式会社 电力用半导体装置的制造方法以及电力用半导体装置
US10052713B2 (en) * 2015-08-20 2018-08-21 Ultex Corporation Bonding method and bonded structure
JP6931869B2 (ja) * 2016-10-21 2021-09-08 国立研究開発法人産業技術総合研究所 半導体装置
US10804236B2 (en) 2018-10-25 2020-10-13 Toyota Motor Engineering & Manufacturing North America, Inc. Power electronic assemblies with high purity aluminum plated substrates
JP7383881B2 (ja) * 2019-01-16 2023-11-21 富士電機株式会社 半導体装置および半導体装置の製造方法
US11139272B2 (en) 2019-07-26 2021-10-05 Sandisk Technologies Llc Bonded assembly containing oxidation barriers and/or adhesion enhancers and methods of forming the same
US11393780B2 (en) 2019-07-26 2022-07-19 Sandisk Technologies Llc Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same
US11515273B2 (en) 2019-07-26 2022-11-29 Sandisk Technologies Llc Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same
US11545460B2 (en) 2020-01-10 2023-01-03 Fuji Electric Co., Ltd. Semiconductor device and method for manufacturing semiconductor device having first and second wires in different diameter
JP7335610B2 (ja) * 2020-01-29 2023-08-30 株式会社アルテクス めっき金属接合方法
JP6952824B2 (ja) * 2020-04-06 2021-10-27 三菱電機株式会社 パワーモジュール及びこれを用いた電力用半導体装置
CN117461138A (zh) * 2021-06-14 2024-01-26 三菱电机株式会社 半导体装置以及电力变换装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012028674A (ja) * 2010-07-27 2012-02-09 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
JP2013118310A (ja) * 2011-12-05 2013-06-13 Jjtech Co Ltd 半導体装置
CN103703560A (zh) * 2011-08-04 2014-04-02 三菱电机株式会社 半导体装置及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10261664A (ja) * 1997-01-17 1998-09-29 Furukawa Electric Co Ltd:The 半導体素子、突起電極の形成方法およびワイヤボンディング方法
DE102005054872B4 (de) * 2005-11-15 2012-04-19 Infineon Technologies Ag Vertikales Leistungshalbleiterbauelement, Halbleiterbauteil und Verfahren zu deren Herstellung
US8110931B2 (en) * 2008-07-11 2012-02-07 Advanced Semiconductor Engineering, Inc. Wafer and semiconductor package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012028674A (ja) * 2010-07-27 2012-02-09 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
CN103703560A (zh) * 2011-08-04 2014-04-02 三菱电机株式会社 半导体装置及其制造方法
JP2013118310A (ja) * 2011-12-05 2013-06-13 Jjtech Co Ltd 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109244057A (zh) * 2018-07-13 2019-01-18 北京大学深圳研究生院 一种封装基板及基于该基板形成的共源共栅氮化镓器件
CN112002645A (zh) * 2020-06-24 2020-11-27 西安理工大学 一种提高SiC功率芯片键合线功率循环能力的方法
CN112201628A (zh) * 2020-08-24 2021-01-08 株洲中车时代半导体有限公司 一种功率模块封装结构及其制备方法

Also Published As

Publication number Publication date
US20170200691A1 (en) 2017-07-13
DE112015004770B4 (de) 2021-01-14
JPWO2016063744A1 (ja) 2017-04-27
DE112015004770T5 (de) 2017-09-28
US9818716B2 (en) 2017-11-14
CN106575628B (zh) 2019-02-15
JP6320556B2 (ja) 2018-05-09
WO2016063744A1 (ja) 2016-04-28

Similar Documents

Publication Publication Date Title
CN106575628A (zh) 功率模块
JP6041469B2 (ja) 高融点半田層の形成方法
CN107615464B (zh) 电力用半导体装置的制造方法以及电力用半导体装置
US10522482B2 (en) Semiconductor device manufacturing method comprising bonding an electrode terminal to a conductive pattern on an insulating substrate using ultrasonic bonding
EP2541593A2 (en) Laminated high melting point soldering layer and fabrication method for the same, and semiconductor device
JP2006024829A (ja) 半導体装置及びその製造方法
CN109075159B (zh) 半导体装置及其制造方法
JP6129090B2 (ja) パワーモジュール及びパワーモジュールの製造方法
JP6116452B2 (ja) 電力用半導体装置の製造方法、電力用半導体装置および電力変換装置
JP6091443B2 (ja) 半導体モジュール
JP4917375B2 (ja) パワー半導体モジュールの製造方法
JP2014032985A (ja) 半導体装置およびその製造方法
JP6006966B2 (ja) 半導体装置およびその製造方法
JP2007150342A (ja) 半導体装置およびその製造方法
JP4795471B2 (ja) 電力用半導体素子
JP2017069366A (ja) 半導体装置およびその製造方法
JP5180802B2 (ja) 積層電極形成方法とその積層電極を備える半導体装置
JP2013038188A (ja) パッケージ封止用の蓋体
JPWO2016171122A1 (ja) 半導体装置及びその製造方法
JP6354954B2 (ja) 半導体装置の製造方法及び半導体装置
JP2009302579A (ja) 半導体装置およびその製造方法
JP2016122799A (ja) 半導体装置
KR20230017184A (ko) 구리/세라믹스 접합체, 및, 절연 회로 기판
JP2016122798A (ja) 半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant