CN106252406B - 具有埋层的半导体装置 - Google Patents

具有埋层的半导体装置 Download PDF

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CN106252406B
CN106252406B CN201510458067.4A CN201510458067A CN106252406B CN 106252406 B CN106252406 B CN 106252406B CN 201510458067 A CN201510458067 A CN 201510458067A CN 106252406 B CN106252406 B CN 106252406B
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high voltage
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substrate
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CN106252406A (zh
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张宇瑞
林正基
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Macronix International Co Ltd
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Abstract

本发明公开了一种具有埋层的半导体装置，该半导体装置，包括一基板、一高电压阱、一源极区域、一漏极区域以及一埋层，基板具有一第一导电类型，高电压阱具有一第二导电类型，并设置于基板之中，源极区域设置于高电压阱之中，漏极区域设置于高电压阱之中，且沿着一第一方向与源极区域间隔开，埋层具有第二导电类型，并设置于源极区域与漏极区域之间的一区域之下。

Description

具有埋层的半导体装置
技术领域
本发明是有关于一种半导体装置，更特别地，是有关于一种具有一埋层的半导体装置。
背景技术
超高电压半导体装置在显示设备、便携设备及许多其它应用中被广泛地使用。超高电压半导体装置的设计目标包括高崩溃电压、低特定导通电阻，以及在室温与高温环境中的高可靠度。然而，当超高电压半导体装置的尺寸缩小，要达成这些目标变得具有挑战性。
发明内容
根据本发明的一实施例，一种半导体装置包括一基板、一高电压阱、一源极区域、一漏极区域以及一埋层，基板具有一第一导电类型，高电压阱具有一第二导电类型，并设置于基板之中，源极区域设置于高电压阱之中，漏极区域设置于高电压阱之中，且沿着一第一方向与源极区域间隔开，埋层具有第二导电类型，并设置于源极区域与漏极区域之间的一区域之下。
根据本发明的另一实施例，一种半导体装置包括一基板、一高电压阱、一源极区域、一漏极区域以及多个离散的埋区域，基板具有一第一导电类型，高电压阱具有一第二导电类型，并设置于基板之中，源极区域设置于高电压阱之中，漏极区域设置于高电压阱之中，且沿着一第一方向与源极区域间隔开，数个离散的埋区域具有第二导电类型，并设置于源极区域与漏极区域之间的一区域之下。
根据本发明又另一实施例，一种半导体装置包括一基板、一高电压阱、一源极区域、一漏极区域以及一埋层，基板具有一第一导电类型，高电压阱具有一第二导电类型，并设置于基板之中，源极区域设置于高电压阱之中，漏极区域设置于高电压阱之中，且沿着一第一方向与源极区域间隔开，埋层具有第二导电类型，并设置于基板之中，且连接至高电压阱的一底部分，底部分是在源极区域与漏极区域之间的一区域之下。
为了对本发明的上述及其他方面有更佳的了解，下文特举较佳实施例，并配合所附图式，作详细说明如下：
附图说明
图1是根据本发明一实施例的具有超高电压金属氧化物半导体(UHV MOS)装置的一集成电路的上视图。
图2A是根据一示范实施例的一UHV MOS装置的上视放大图。
图2B是图2A的UHV MOS装置的区域A的进一步的上视放大图。
图2C是图2A的UHV MOS装置沿着图2B的切线C-C’的剖面图。
图2D是图2A的UHV MOS装置沿着图2B的切线D-D’的剖面图。
图3是绘示比较范例的一装置的漏极至源极的电流-电压特性之图。
图4是根据一示范实施例，绘示图2A的UHV MOS装置的漏极至源极的电流-电压特性之图。
图5A是根据一示范实施例，绘示一UHV MOS装置的第一剖面。
图5B是根据示范实施例，绘示图5A的UHV MOS装置的第二剖面。
图6A是根据一示范实施例，绘示一半导体装置的第一剖面。
图6B是根据示范实施例，绘示图6A的半导体装置的第二剖面。
图7A是根据一示范实施例，绘示一UHV MOS装置的第一剖面。
图7B是根据示范实施例，绘示图7A的UHV MOS装置的第二剖面。
图8A是根据一示范实施例，绘示一UHV MOS装置的第一剖面。
图8B是根据示范实施例，绘示图8A的UHV MOS装置的第二剖面。
图9A是根据一示范实施例，绘示一UHV MOS装置的第一剖面。
图9B是根据示范实施例，绘示图9A的UHV MOS装置的第二剖面。
图10是根据一示范实施例，绘示一绝缘栅双极晶体管的剖面图。
图11是根据一示范实施例，绘示一高电压二极管的剖面图。
图12是根据一示范实施例，绘示一结场效晶体管的剖面图。
【符号说明】
100：集成电路
110、120、500、600、700、800、900：超高电压金属氧化物半导体(UHV MOS)装置
130：寄生二极管
140：高电压(HV)区域
150：低电压(LV)区域
200、1210：基板
205、1215：第一高电压N型阱(HVNW)
206、1216：第二高电压N型阱
210、1220：第一P型阱(PW)
211、1221：第二P型阱
212、1222：第三P型阱
213：第四P型阱
215：第一N型埋层(NBL)
216：第二N型埋层
217：第三N型埋层
220、1230：漂移区域
220a、920a：第一区段
220b、920b：第二区段
221、1231：P型顶层
222、1232：N型渐变层
225、525、625、725、825、1235：离散的N+型埋区域
230：绝缘层
231～235、1241～1245：场氧化物部分
240：栅极氧化层
245：栅极层
250：间隔物
255、1255：第一N+区域
256、1256：第二N+区域
257、1257：第三N+区域
260、1260：第一P+区域
261、1261：第二P+区域
265、1265：层间介电(ILD)层
270、1270：第一金属(M1)层
275、1275：内金属介电(IMD)层
280、1110、1280：第二金属(M2)层
310、410：横坐标
320、420：纵坐标
330、430、350、450：虚线
341～344、441～444：曲线
921：离散的P型顶层
922：离散的N型渐变层
1000：绝缘栅双极晶体管(IGBT)
1010：P+区域
1100：高电压(HV)二极管
1112：第一M2部分
1114：第二M2部分
1200：结场效晶体管(JFET)
1225：N型埋层
1240：场氧化物层
A：区域
C-C’、D-D’：切线
具体实施方式
现将参照本实施例的详细描述部分，其范例是绘示于所附的图式中。将尽可能地，相同的参考标号在所有图式中代表相同或相似的部分。
图1是根据一示范实施例的具有超高电压金属氧化物半导体(Ultra-HighVoltage Metal-Oxide-Semiconductor，UHV MOS)装置的一集成电路(IntegratedCircuit，IC)100的上视图。如图1所示，集成电路100包括二个UHV MOS装置110及120，以及一寄生二极管130。一高电压(High Voltage，HV)区域140是设置于UHV MOS装置110及120、以及寄生二极管130所围绕的一区域的内部。一低电压(Low Voltage，LV)区域150是设置于HV区域140的左侧及下侧，如图1所示。UHV MOS装置110及120具有类似的结构，但具有不同的操作电压，例如栅极电压、源极电压、漏极电压、以及体电压(bulk voltage)。UHV MOS装置110及120皆具有相对高的崩溃电压(高于500伏特)。半导体装置，例如是低电压金属氧化物半导体(Low-Voltage Metal-Oxide-Semiconductor，LVMOS)装置、双极型结晶体管(Bipolar Junction Transistors，BJTs)、电容、电阻等，可形成于HV区域140之中。举例而言，以高于500伏特的高电压操作来说，形成于HV区域140之中的半导体装置被连接至高于500伏特的参考接地电压。相似地，例如是LVMOS装置、BJTs、电容、电阻等半导体装置可形成于LV区域150之中。举例而言，以约为5伏特或15伏特的低电压操作来说，形成于LV区域150之中的半导体装置被连接至约为0伏特的接地电压。
图2A是根据一示范实施例的UHV MOS装置110的上视放大图。图2B是图2A的UHVMOS装置110的区域A的进一步的上视放大图。图2C是图2A的UHV MOS装置110沿着图2B的切线C-C’的剖面图。图2D是图2A的UHV MOS装置110沿着图2B的切线D-D’的剖面图。由于UHVMOS装置120的结构是类似于UHV MOS装置110的结构，便不提供UHV MOS装置120的结构另外的描述。
参考图2A至图2D，UHV MOS装置110是提供于一P型基板(P-sub)200上方。基板200可由一P型主体硅材料、一P型外延层、或一P型绝缘体上硅(Silicon-On-Insulator，SOI)材料所形成。一第一高电压N型阱(High-Voltage N-Well，HVNW)205及一第二高电压N型阱206是设置在基板200之中。第一高电压N型阱205是与第二高电压N型阱206间隔开且电性隔离。
一第一P型阱(P-Well，PW)210是设置在第一高电压N型阱205之中，并延伸至第一高电压N型阱205的底部。一第二P型阱211与一第三P型阱212是设置在基板200之中，并位于第一高电压N型阱205与第二高电压N型阱206之间。一第四P型阱213是设置在基板200中，并与第一高电压N型阱205的左侧邻接，第一高电压N型阱205的左侧是与右侧相对，右侧为靠近第二高电压N型阱206的一侧。第二P型阱211是与第一高电压N型阱205的右侧邻接，第三P型阱212是与第二高电压N型阱206的左侧邻接。第二P型阱211与第三P型阱212是间隔于彼此，以电性隔离第一高电压N型阱205与第二高电压N型阱206。
虽然绘示于图2A至图2D中的UHV MOS装置110只包括第二P型阱211与第三P型阱212，以电性隔离第一高电压N型阱205与第二高电压N型阱206，然UHV MOS装置110可包括多于二个的P型阱设置在第一高电压N型阱205与第二高电压N型阱206之间，以电性隔离第一高电压N型阱205与第二高电压N型阱206。
一第一N型埋层(N-type Buried Layer，NBL)215是形成于基板200之中，并垂直交叠(沿着如图2A至图2D中所示的Z方向)与连接至第一P型阱210的底部分。一第二N型埋层216是形成于基板200之中，并垂直交叠与连接至第一高电压N型阱205的右侧底部分，如图2C及图2D中所示。一第三N型埋层217是形成于基板200之中，并垂直交叠与连接至第二高电压N型阱206的底部分。
一漂移区域220是设置于第一高电压N型阱205之中，并与第一P型阱210间隔开。漂移区域220包括多个交替排列(沿着如图2A至图2D中所示的Y方向)的第一区段220a及第二区段220b。各个第一区段220a包括一P型顶层221及一N型渐变层222，N型渐变层222形成于P型顶层221的顶部上方。各个第二区段220b并不包括任何的P型顶层与N型渐变层。
如图2A、图2B及图2D所示，多个离散的N+型埋区域225是形成于基板200之中，且在漂移区域220下方的一区域中。这些离散的N+型埋区域225是沿着Y方向与X方向间隔于彼此。这些离散的N+型埋区域225被连接至第一高电压N型阱205的底部分。这些离散的N+型埋区域225是垂直交叠于漂移区域220的第二区段220b。N+型埋区域225的尺寸，以及相邻的N+型埋区域225之间的间隔是由各种设计考虑所决定的变量。举例来说，但非用以限制本发明，在一示范实施例中，每个N+型埋区域225具有约为1微米的直径，且在相邻的区域225之间具有约4微米的间隔。N+型埋区域225的掺杂浓度是基于N+型埋区域225的尺寸及间隔、第一高电压N型阱205的掺杂浓度、以及UHV MOS装置110的目标崩溃电压所决定。举例来说，N+型埋区域225可以约为1016至1017atoms/cm3的浓度掺杂一N型掺杂物(例如砷或锑)。
一绝缘层230是设置在基板200之上。绝缘层230可由场氧化物(FOX)所形成。在下文中，绝缘层230以场氧化物层230称之。场氧化物层230包括第一至第五场氧化物部分231至235。第一场氧化物部分231覆盖第二高电压N型阱206的右侧部分。第二场氧化物部分232覆盖第一高电压N型阱205的右侧边缘部分、第二P型阱211、第三P型阱212、第二P型阱211与第三P型阱212之间的间隔、以及第二高电压N型阱206的左侧边缘部分。第三场氧化物部分233覆盖漂移区域220。第四场氧化物部分234覆盖第一高电压N型阱205的左侧边缘部分、第一P型阱210的左侧边缘部分、以及第四P型阱213的右侧边缘部分。第五场氧化物部分235覆盖第四P型阱213的左侧边缘部分。
一栅极氧化层240是设置在基板200之上，覆盖第一P型阱210的右侧边缘部分以及第一P型阱210与第三场氧化物部分233之间的间隔。由例如是多晶硅(poly)所形成的一栅极层245是设置在基板200之上，覆盖栅极氧化层240以及第三场氧化物部分233的左侧部分。间隔物250是设置于栅极层245的侧壁上方。
一第一N+区域255是设置于第一场氧化物部分231与第二场氧化物部分232之间的第二高电压N型阱206之中。一第二N+区域256是设置于第二场氧化物部分232与第三场氧化物部分233之间的第一高电压N型阱205之中。第二N+区域256构成UHV MOS装置110的一漏极(D)区域。在下文中，第二N+区域256以漏极区域256称之。一第三N+区域257是设置于与栅极氧化层240的左侧边缘部分相邻的第一P型阱210的右侧部分之中。第三N+区域257构成UHVMOS装置110的一源极(S)区域。在下文中，第三N+区域257以源极区域257称之。
一第一P+区域260是设置于第一P型阱210的左侧部分之中，并与第三N+区域257的左侧边缘部分相邻。第一P+区域260构成UHV MOS装置110的一主体(B)区域。在下文中，第一P+区域260以主体区域260称之。一第二P+区域261是设置于第四P型阱213之中，并位于第四场氧化物部分234与第五场氧化物部分235之间。第二P+区域261提供一连接至基板200。在下文中，第二P+区域261以P型基板区域261称之。
一层间介电(InterLayer Dielectric，ILD)层265是设置在基板200之上，并具有穿孔，以提供第一N+区域255、漏极区域256、栅极层245、源极区域257、主体区域260、及P型基板区域261各自的接触点。一第一金属(M1)层270是设置于层间介电层265之上，并包括各别连接至第一N+区域255、漏极区域256、栅极层245、源极区域257、主体区域260、及P型基板区域261的电性隔离部分。
一内金属介电(Inter-Metal Dielectric，IMD)层275是设置在第一金属层270之上，并具有各自对应至第一金属层270的电性隔离部分的穿孔(所谓的「通孔」)。一第二金属(M2)层280是设置于内金属介电层275之上，并包括各自连接至第一金属层270的电性隔离部分的电性隔离部分。
图3是绘示构成比较范例的一UHV MOS装置的漏极至源极的电流-电压特性之图。除了比较范例的装置并不包括数个离散的N+型埋区域225之外，比较范例的装置具有类似于图2A至图2D中所示的UHV MOS装置110的结构。在图3中，横坐标310代表漏极至源极电压Vd(伏特)，亦即施加在装置的漏极区域与源极区域之间的电压，而纵坐标320代表漏极至源极电流Id(安培)，亦即流经装置的漏极区域与源极区域之间的电流。虚线330代表线性区域和饱和区域之间的边界。也就是说，线性区域是位于线330的左侧，饱和区域是位于线330的右侧。在漏极至源极电流Id的量测期间，漏极至源极电压Vd从0至600伏特间改变。曲线341代表固定栅极至源极电压Vg(亦即施加在装置的栅极层与源极区域之间的电压)为5伏特所量测的漏极至源极电流Id。曲线342代表固定栅极至源极电压Vg为10伏特所量测的漏极至源极电流Id。曲线343代表固定栅极至源极电压Vg为15伏特所量测的漏极至源极电流Id。曲线344代表固定栅极至源极电压Vg为20伏特所量测的漏极至源极电流Id。
图4是根据一示范实施例，绘示构成UHV MOS装置110的漏极至源极的电流-电压特性之图。在图4中，横坐标410代表漏极至源极电压Vd(伏特)，亦即施加在漏极区域256与源极区域257之间的电压，而纵坐标420代表漏极至源极电流Id(安培)，亦即流经漏极区域256与源极区域257之间的电流。虚线430代表线性区域和饱和区域之间的边界。也就是说，线性区域是位于线430的左侧，饱和区域是位于线430的右侧。在漏极至源极电流Id的量测期间，漏极至源极电压Vd从0至600伏特间改变。曲线441代表固定栅极至源极电压Vg为5伏特所量测的漏极至源极电流Id。曲线442代表固定栅极至源极电压Vg为10伏特所量测的漏极至源极电流Id。曲线443代表固定栅极至源极电压Vg为15伏特所量测的漏极至源极电流Id。曲线444代表固定栅极至源极电压Vg为20伏特所量测的漏极至源极电流Id。
根据图3，当比较范例的装置在线性区域中操作时，栅极至源极电压Vg为5伏特的漏极至源极的电流-电压曲线(如虚线350所圈起的区域中的曲线341所示)是平滑的，而栅极至源极电压值Vg为10伏特、15伏特及20伏特的漏极至源极的电流-电压曲线(如虚线350所圈起的区域中的曲线342、343及344所示)是受阻的。也就是说，当漏极至源极电压值Vd低于60伏特时，栅极至源极电压值Vg为10伏特、15伏特及20伏特的漏极至源极电流Id是低于栅极至源极电压值Vg为5伏特的漏极至源极电流Id。相反地，根据图4，当公开的实施例的UHV MOS装置110在线性区域中操作时，栅极至源极电压值Vg为5伏特、10伏特、15伏特及20伏特的漏极至源极的电流-电压曲线(如虚线450所圈起的区域中的曲线441、442、443及444所示)是平滑的。因此，公开的实施例的UHV MOS装置110的漏极至源极的电流-电压特性，相较于比较范例的装置的漏极至源极的电流-电压特性得到了改善。原因在于：在揭露实施例的UHV MOS装置110中，由于数个离散的N+型埋区域225的存在，使漏极区域256与源极区域257之间的电子传递得更为平顺。
下表1归纳了构成比较范例的装置以及根据本发明的一实施例构成的UHV MOS装置110的电性数值。
表1
比较范例 UHV MOS装置110
Vt(V) 1.32 1.33
Idlin(μA) 338 379
BV(V) 820 810
表1中，Vt代表比较范例的装置以及UHV MOS装置110各别的阈值电压。阈值电压Vt 是使用最大转移电导(maximum transconductance，max gm)法来决定。根据最大转移电导 法，装置的阈值电压Vt相当于装置的转移电导对栅极至源极电压(gm-Vg)特性取其最大一 阶导数(斜率)的点线性外推的栅极电压轴截距，转移电导(gm)是将漏极至源极电压Vd维持 固定时，漏极至源极电流Id变量与栅极至源极电压Vg变量的比值，亦即
表1中，Idlin代表比较范例的装置以及UHV MOS装置110各别的线性区域漏极至源极电流(亦即在线性区域的漏极源极电流)。线性区域漏极至源极电流Idlin是当漏极至源极电压Vd为1伏特，且栅极至源极电压Vg为15伏特时所量测的漏极至源极电流Id。
表1中，BV代表比较范例的装置以及UHV MOS装置110各别的截止崩溃电压。截止崩溃电压BV是当漏极至源极电压Vd从0伏特增加，且栅极至源极电压Vg为0伏特时，漏极至源极电流Id达到1微安培的漏极至源极电压Vd的数值。
根据表1，比较范例的装置以及揭露实施例的UHV MOS装置110具有类似的阈值电压Vt以及截止崩溃电压BV。然而，揭露实施例的UHV MOS装置110的线性区域漏极至源极电流Idlin是高于比较范例的装置。因此，UHV MOS装置110的导通电阻是低于比较范例的装置。
虽上述实施例是针对图2A至图2D所示的N型UHV MOS装置110，然所属领域的技术人员现将理解，所揭露的概念同样能应用至P型UHV MOS装置，其中所有的元件具有与N型UHV MOS装置110相反的导电型态。
虽上述实施例的UHV MOS装置110的绝缘层230是由场氧化物所制成，然绝缘层230可由其他合适的介电绝缘结构所制成，例如是一浅沟道隔离(Shallow Trench Isolation，STI)结构。
虽上述实施例的UHV MOS装置110具有二层金属层，亦即第一金属层270及第二金属层280，然所属领域的技术人员现将理解，所揭露的概念同样能应用至只具有一层金属层或多于二层金属层的UHV MOS装置。
虽上述实施例的UHV MOS装置110中的离散的N+型埋区域225垂直交叠于飘移区域220的第二区段220b，然离散的N+型埋区域可垂直交叠于飘移区域220的第一区段220a。
图5A是根据一示范实施例，绘示一UHV MOS装置500的第一剖面。图5B是根据示范实施例，绘示UHV MOS装置500的第二剖面。第一剖面及第二剖面是沿着图5A及图5B所示的Y方向交替地排列。根据图5A及图5B，除了UHV MOS装置500包括垂直交叠于飘移区域220的第一区段220A的多个离散的N+型埋区域525之外，UHV MOS装置500具有类似于UHV MOS装置110的结构。类似于UHV MOS装置110中的离散的N+型埋区域225，UHV MOS装置500中的数个离散的N+型埋区域525是沿着UHV MOS装置500的Y方向与X方向间隔于彼此。这些离散的N+型埋区域525被连接至第一高电压N型阱205的底部分。
虽上述实施例是针对图5A及图5B所示的UHV MOS装置500，然所属领域的技术人员现将理解，所揭露的概念同样能应用至其他半导体装置。
图6A是根据一示范实施例，绘示一半导体装置600的第一剖面。图6B是根据示范实施例，绘示半导体装置600的第二剖面。第一剖面及第二剖面是沿着图6A及图6B所示的Y方向交替地排列。根据图6A及图6B，除了装置600没有包括飘移区域220之外，装置600具有类似于UHV MOS装置110的结构。装置600包括多个离散的N+型埋区域625，离散的N+型埋区域625是沿着Y方向与X方向间隔于彼此。这样，数个离散的N+型埋区域625仅示于图6B，其绘示装置600的第二剖面。这些离散的N+型埋区域625被连接至第一高电压N型阱205的底部分。
虽上述实施例的UHV MOS装置600中的离散的N+型埋区域625是设置在基板200之中，并连接至第一高电压N型阱205的底部分，然离散的N+型埋区域可设置在第一高电压N型阱205之中。
图7A是根据一示范实施例，绘示一UHV MOS装置700的第一剖面。图7B是根据示范实施例，绘示UHV MOS装置700的第二剖面。第一剖面及第二剖面是沿着图7A及图7B所示的Y方向交替地排列。根据图7A及图7B，除了UHV MOS装置700包括多个离散的N+型埋区域725在第一高电压N型阱205中的飘移区域220之下的区域中之外，UHV MOS装置700具有类似于UHVMOS装置110的结构。这些离散的N+型埋区域725垂直交叠于飘移区域220的第二区段220b。
虽上述实施例的UHV MOS装置700中的数个离散的N+型埋区域725是沿着Y方向与X方向间隔于彼此，然离散的N+型埋区域可只沿着Y方向间隔于彼此。
图8A是根据一示范实施例，绘示一UHV MOS装置800的第一剖面。图8B是根据示范实施例，绘示UHV MOS装置800的第二剖面。第一剖面及第二剖面是沿着图8A及图8B所示的Y方向交替地排列。根据图8A及图8B，除了UHV MOS装置800包括沿着Y方向间隔与彼此的多个离散的N+型埋区域825于基板200中之外，UHV MOS装置800具有类似于UHV MOS装置110的结构。每个离散的N+型埋区域825沿着X方向延伸，且垂直交叠于飘移区域220对应的第二区段220b。这些离散的N+型埋区域825是设置在飘移区域220之下的区域中，并连接至第一高电压N型阱205的底部分。
虽上述实施例的UHV MOS装置800中的P型顶层221与N型渐变层222是沿着X方向延伸，然UHV MOS装置可包括沿着X方向间隔与彼此的多个离散的P型顶层与多个离散的N型渐变层。
图9A是根据一示范实施例，绘示一UHV MOS装置900的第一剖面。图9B是根据示范实施例，绘示UHV MOS装置900的第二剖面。第一剖面及第二剖面是沿着图9A及图9B所示的Y方向交替地排列。根据图9A及图9B，除了UHV MOS装置900的飘移区域的各个第一区段920a包括沿着图9A及图9B所示的X方向间隔于彼此的多个离散的P型顶层921、以及设置在对应的离散的P型顶层921的顶部的多个离散的N型渐变层922之外，UHV MOS装置900具有类似于UHV MOS装置110的结构。各个第二区段920b没有包括任何的P型顶层或N型渐变层。
所属领域的技术人员亦将理解，所揭露的概念能应用至其他半导体装置，例如是绝缘栅双极晶体管(Insulated-Gate Bipolar Transistor，IGBT)装置、高电压二极管与结场效晶体管(Junction Field-Effect Transistors，JFET)。
图10是根据一示范实施例，绘示一绝缘栅双极晶体管(IGBT)1000的剖面图。除了UHV MOS装置110的第二N+区域256是由P+区域1010所取代之外，绝缘栅双极晶体管1000具有类似于UHV MOS装置110的结构。在图10中所示的绝缘栅双极晶体管1000中，P+区域1010构成一集极(C)区域，第三N+区域257构成一源极(S)区域，第一P+区域260构成一射极(E)区域。
图11是根据一示范实施例，绘示一高电压(HV)二极管1100的剖面图。除了一第二金属(M2)层1110包括一第一M2部分1112及一第二M2部分1114之外，高电压二极管1100具有类似于UHV MOS装置110的结构，其中第一M2部分1112与第一N+区域255及漏极区域256导电接触，第二M2部分1114与栅极层245、源极区域257、主体区域260及P型基板区域261导电接触。第一M2部分1112构成高电压二极管1100的一N型终端，第二M2部分1114构成高电压二极管1100的一P型终端。
图12是根据一示范实施例，绘示一结场效晶体管(JFET)1200的剖面图。结场效晶体管1200是提供在一P型基板(P-sub)1210上方。一第一高电压N型阱(HVNW)1215与一第二高电压N型阱1216是设置在基板1210之中，并间隔于彼此。
一第一P型阱1220是设置在基板1210中，并与第一高电压N型阱1215的左侧相邻。一第二P型阱1221与一第三P型阱1222是设置在基板1210中，并位于第一高电压N型阱1215与第二高电压N型阱1216之间。第二P型阱1221是与第一高电压N型阱1215的右侧相邻，第三P型阱1222是与第二高电压N型阱1216的左侧相邻。第二P型阱1221与第三P型阱1222是间隔于彼此，以电性隔离第一高电压N型阱1215与第二高电压N型阱1216。
一N型埋层1225是形成于基板1210之中。N型埋层1225垂直交叠并连接至第一高电压N型阱1215的右侧底部分。
一飘移区域1230是设置在第一高电压N型阱1215之中。飘移区域1230包括多个第一区段与第二区段，数个第一区段与第二区段是沿着图12中所示的Y方向交替地排列。每个第一区段包括一P型顶层1231与一N型渐变层1232，N型渐变层1232形成于P型顶层1231的顶部上方。每个第二区段并不包括任何的P型顶层或N型渐变层。虽图12仅绘示一个第一区段的剖面视图，然除了第一高电压N型阱1215在第二区段的剖面视图中形成飘移区域1230的整体之外，第二区段的剖面视图是类似于第一区段。
多个离散的N+型埋区域1235是形成于基板1210之中，并在飘移区域1230下方的区域中。这些离散的N+型埋区域1235是沿着图12所示的Y方向与X方向间隔于彼此。这些离散的N+型埋区域1235被连接至第一高电压N型阱1215的一底部分，并垂直交叠于漂移区域1230的第一区段。
一场氧化物层1240是设置于基板1210之上。场氧化物层1240包括第一至第五场氧化物部分1241至1245。第一场氧化物部分1241覆盖第二高电压N型阱1216的右侧部分。第二场氧化物部分1242覆盖第一高电压N型阱1215的右侧边缘部分、第二P型阱1221、第三P型阱1222、第二P型阱1221与第三P型阱1222之间的间隔、以及第二高电压N型阱1216的左侧边缘部分。第三场氧化物部分1243覆盖漂移区域1230。第四场氧化物部分1244覆盖第一高电压N型阱1215的左侧边缘部分以及第一P型阱1220的右侧边缘部分。第五场氧化物部分1245覆盖第第一P型阱1220的左侧边缘部分。
一第一N+区域1255是设置在第二高电压N型阱1216当中，并位于第一场氧化物部分1241与第二场氧化物部分1242之间。一第二N+区域1256是设置在第一高电压N型阱1215当中，并位于第二场氧化物部分1242与第三场氧化物部分1243之间。第二N+区域1256构成结场效晶体管1200的一漏极(D)区域。在下文中，第二N+区域1256以一漏极区域1256称之。一第三N+区域1257是设置于与第四场氧化物部分1244的右侧边缘部分相邻的第一高电压N型阱1215之中。第三N+区域1257构成结场效晶体管1200的一源极(S)区域。在下文中，第三N+区域1257以一源极区域1257称之。
一第一P+区域1260是设置在第一高电压N型阱1215当中，并位于第三N+区域1257与漂移区域1230之间。第一P+区域1260是与源极1257及漂移区域1230间隔开，并构成结场效晶体管1200的一栅极(G)区域。在下文中，第一P+区域1260以一栅极区域1260称之。一第二P+区域1261是设置于第一P型阱1220当中，并位于第四场氧化物部分1244与第五场氧化物部分1245之间。第二P+区域1261提供一连接至基板1210。在下文中，第二P+区域1261以P型基板区域1261称之。
一层间介电(InterLayer Dielectric，ILD)层1265是设置在基板1210之上，并具有穿孔，以提供第一N+区域1255、漏极区域1256、栅极区域160、源极区域1257及P型基板区域1261各自的接触点。一第一金属(M1)层1270是设置于层间介电层1265之上，并包括各别连接至第一N+区域1255、漏极区域1256、栅极区域160、源极区域1257及P型基板区域1261的电性隔离部分。
一内金属介电(Inter-Metal Dielectric，IMD)层1275是设置在第一金属层1270之上，并具有各自对应至第一金属层1270的电性隔离部分的穿孔(所谓的「通孔」)。一第二金属(M2)层1280是设置于内金属介电层1275之上，并包括各自连接至第一金属层1270的电性隔离部分的电性隔离部分。
上述的实施例中的半导体装置可在各种应用中实施，举例来说，例如是发光二极管(Light Emitting Diode，LED)照明、节能灯具、稳压器应用以及马达驱动应用。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视随附的权利要求范围所界定的为准。

Claims (13)

1.一种半导体装置，包括：
一基板，具有一第一导电类型；
一高电压阱，具有一第二导电类型，并设置于该基板之中；
一源极区域，设置于该高电压阱之中；
一漏极区域，设置于该高电压阱之中，且沿着一第一方向与该源极区域间隔开；以及
一埋层，具有该第二导电类型，并设置于该源极区域与该漏极区域之间的一区域之下；
其中，该埋层包括多个离散的埋区域，这些离散的埋区域沿着该第一方向以及一第二方向间隔于彼此，该第二方向与该第一方向正交。
2.根据权利要求1所述的半导体装置，更包括一漂移区域，该漂移区域设置于该源极区域与该漏极区域之间的该高电压阱之中，
其中该漂移区域包括多个第一区段及多个第二区段，这些第一区段及这些第二区段沿着该第二方向交替地排列，
各该第一区段包括一顶层及一渐变层，该顶层具有该第一导电类型，该渐变层具有该第二导电类型并设置于该顶层之上，以及
各该第二区段并不包括该顶层及该渐变层。
3.根据权利要求2所述的半导体装置，其中这些离散的埋区域垂直地交叠于这些第一区段。
4.根据权利要求2所述的半导体装置，其中这些离散的埋区域垂直地交叠于这些第二区段。
5.根据权利要求2所述的半导体装置，其中
该顶层包括多个离散的顶层，这些离散的顶层沿着该第一方向间隔于彼此；以及
该渐变层包括多个离散的渐变层，这些离散的渐变层沿着该第一方向间隔于彼此，并设置于对应的这些顶层的顶部上方。
6.根据权利要求1所述的半导体装置，其中该埋层是设置于该基板之中，并连接至该高电压阱的一底部分。
7.根据权利要求1所述的半导体装置，其中该埋层是设置于该高电压阱之中。
8.根据权利要求1所述的半导体装置，其中该第一导电类型是P型，该第二导电类型是N型。
9.根据权利要求1所述的半导体装置，其中该第一导电类型是N型，该第二导电类型是P型。
10.根据权利要求1所述的半导体装置，更包括一绝缘层，该绝缘层设置于该基板之上且包括一隔离部分，以隔离该漏极区域与该源极区域。
11.根据权利要求10所述的半导体装置，更包括一栅极氧化层及一栅极层，该栅极氧化层及该栅极层设置于该隔离部分的一边缘与该源极区域之间的该基板之上。
12.根据权利要求10所述的半导体装置，更包括至少一金属层，该至少一金属层设置于该基板与该绝缘层之上。
13.一种半导体装置，包括：
一基板，具有一第一导电类型；
一高电压阱，具有一第二导电类型，并设置于该基板之中；
一源极区域，设置于该高电压阱之中；
一漏极区域，设置于该高电压阱之中，且沿着一第一方向与该源极区域间隔开；以及
一埋层，具有该第二导电类型，并设置于该基板之中，且连接至该高电压阱的一底部分，该底部分是在该源极区域与该漏极区域之间的一区域之下；
其中，该埋层包括多个离散的埋区域，这些离散的埋区域是沿着该第一方向以及一第二方向间隔于彼此，该第二方向与该第一方向正交。
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TWI647788B (zh) * 2017-01-25 2019-01-11 新唐科技股份有限公司 半導體裝置
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