TWI536542B - 包括高電壓二極體之半導體裝置 - Google Patents

包括高電壓二極體之半導體裝置 Download PDF

Info

Publication number
TWI536542B
TWI536542B TW103134698A TW103134698A TWI536542B TW I536542 B TWI536542 B TW I536542B TW 103134698 A TW103134698 A TW 103134698A TW 103134698 A TW103134698 A TW 103134698A TW I536542 B TWI536542 B TW I536542B
Authority
TW
Taiwan
Prior art keywords
type well
high voltage
diode
region
voltage diode
Prior art date
Application number
TW103134698A
Other languages
English (en)
Other versions
TW201606985A (zh
Inventor
張宇瑞
林正基
連士進
Original Assignee
旺宏電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 旺宏電子股份有限公司 filed Critical 旺宏電子股份有限公司
Publication of TW201606985A publication Critical patent/TW201606985A/zh
Application granted granted Critical
Publication of TWI536542B publication Critical patent/TWI536542B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/067—Lateral bipolar transistor in combination with diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Geometry (AREA)

Description

包括高電壓二極體之半導體裝置 【0001】
本公開是有關於一種包括高電壓(high-voltage, HV)二極體之半導體裝置，且特別是有關於一種包括連接寄生PNP裝置之高電壓二極體的半導體裝置。
 【0002】
超高壓半導體裝置被廣泛地使用於顯示裝置、可攜式裝置以及許多其他的應用。通常，積體電路包括超高壓半導體裝置，亦包括可以做為高電壓二極體的的二極體。
 【0003】
依照本公開之一實施例，一種半導體裝置，包括：一基板、配置於基板中的一高電壓N型井(high-voltage N-well, HVNW)、配置於基板中且鄰近HVNW之邊緣的一大塊P型井、配置於HVNW中的一高電壓(high-voltage, HV)二極體，HV二極體包括配置於HVNW中且與HVNW之邊緣分開的一HV二極體P型井以及配置於HVNW中且位於HV二極體P型井與大塊P型井之間的一N型井。N型井的摻雜濃度大於HVNW的摻雜濃度。
【0004】
依照本公開之另一實施例，一種半導體裝置的製造方法包括：於基板中形成高電壓N型井(high-voltage N-well, HVNW)，於基板中形成在HVNW外且鄰近HVNW之邊緣的大塊P型井，於HVNW中形成HV二極體P型井，且HV二極體P型井與HVNW之邊緣分開，以及形成位於HVNW中且位於HV二極體P型井與大塊P型井之間的N型井，包括形成此N型井以具有大於HVNW之摻雜濃度的摻雜濃度。
【0005】
依照本公開之又一實施例，一種積體電路，包括：基板、配置於基板中的高電壓N型井(high-voltage N-well, HVNW)、配置於HVNW外且圍繞HVNW的大塊P型井、配置於HVNW內的高電壓(high-voltage, HV)二極體，並且包括沿著HVNW之邊緣配置且與HVNW之邊緣分開的HV二極體P型井，以及沿著HVNW之邊緣配置且位於HV二極體P型井與HVNW的邊緣之間的N型井。N型井的摻雜濃度大於HVNW的摻雜濃度。
【0006】
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
 【0040】
100、500、1000、1100‧‧‧積體電路
110‧‧‧基板
120、120’‧‧‧大塊P型井
130‧‧‧高電壓N型井
140‧‧‧大塊P+區域
150、150’‧‧‧HV二極體P型井
160‧‧‧HV二極體P+區域
170‧‧‧HV二極體N+區域
180、1010‧‧‧N型井
190‧‧‧漂移區
190a‧‧‧P型頂層
190b‧‧‧N型遞變層
195‧‧‧源極N+區域
200‧‧‧高電壓區塊
210‧‧‧低電壓區塊
220、230‧‧‧超高壓金屬氧化物半導體裝置
250‧‧‧第一N型內埋層
260‧‧‧第二N型內埋層
270‧‧‧絕緣層
280‧‧‧閘極氧化層
290‧‧‧閘極層
300‧‧‧層間介電層
310‧‧‧第一金屬層
320‧‧‧金屬間介電層
330‧‧‧第二金屬層
1020‧‧‧N型內埋層
A‧‧‧區域
A-A’、B-B’‧‧‧連線
【0007】

第1圖繪示依照本公開之一說明實施例之積體電路(integrated circuit, IC)的平面圖。
第2圖繪示依照本公開之一說明實施例，第1圖之IC的區域A的放大平面圖。
第3圖繪示沿著第2圖之A-A’連線的IC剖面圖。
第4圖繪示依照本公開之一說明實施例，沿著第3圖之B-B’連線的淨摻雜分布圖。
第5圖繪示依照一比較例之IC的剖面圖。
第6圖繪示沿著第5圖之C-C’連線，第5圖之IC的淨摻雜分布圖。
第7圖繪示對依照第5圖製造的一裝置進行高溫操作生命(high temperature operating life, HTOL)測試前後所測得的漏電流(Ignd )對正電流(Iboot )的圖表，作為一比較例。
第8圖繪示對依照第3圖製造的一裝置進行第一HTOL測試前後所測得的Ignd 對Iboot 的圖表，作為一範例。
第9圖繪示對依照第3圖製造的一裝置進行第二HTOL測試前後所測得的Ignd 對Iboot 的圖表，作為一範例。
第10圖繪示依照本公開之另一說明實施例之IC的剖面圖。
第11圖繪示依照本公開之又一說明實施例之IC的剖面圖。
 【0008】
以下將詳細地敘述本實施例，本實施例的範例繪示於所附圖式中。只要有可能，圖式中從頭到尾將使用相同的元件符號以代表相同或類似的部分。
【0009】
第1圖繪示依照本公開之一說明實施例之積體電路(integrated circuit, IC)100的平面圖。第2圖繪示依照本公開之一說明實施例，IC 100之區域A的放大平面圖。第3圖繪示沿著第2圖之A-A’連線的IC 100剖面圖。
【0010】
請參照第1圖以及第2圖，於一基板110上提供IC 100，基板110具有圍繞一高電壓N型井(high-voltage N-well, HVNW)130的一大塊P型井120。一大塊P+區域140係配置於大塊P型井120內。一高電壓(high-voltage, HV)二極體係配置於HVNW 130內。高電壓二極體包括沿著HVNW 130之邊緣配置且與HVNW 130之邊緣分開的一HV二極體P型井150、配置於HV二極體P型井150中的HV二極體P+區域160以及沿著HVNW 130之上側邊緣部分、右側邊緣部分與下側邊緣部分的HV二極體N+區域170，如第1圖中所示。配置一N型井180鄰近且沿著HVNW 130的邊緣。配置N型井180鄰近HV二極體P型井150與大塊P型井120兩者，且位於HV二極體P型井150與大塊P型井120之間。漂移區190係配置於由HV二極體P型井150圍繞的區塊內，且漂移區190沿著HV二極體P型井150之邊緣並與HV二極體P型井150之邊緣分開。一源極N+區域195係配置於HV二極體P型井150中，且鄰近HV二極體P+區域160。
【0011】
基板110包括位於HVNW 130內的一高電壓(high voltage, HV)區塊200，以及位於HVNW 130外且位於HVNW 130之左側與下側的一低電壓(low voltage, LV)區塊210，如第1圖中所示。IC 100包括位於HV區塊200與LV區塊210之間的兩個超高壓金屬氧化物半導體(ultra-high voltage metal-oxide-semiconductor, UHV MOS)裝置220以及230。UHV MOS裝置220以及230的結構類似，但是可以具有不同的操作電壓，如閘極電壓、源極電壓、汲極電壓以及體電壓(bulk voltage)。UHV MOS裝置220以及230兩者都具有相對高的崩潰電壓，大於500伏特。雖然第1圖僅繪示兩個UHV MOS裝置220以及230，可於HV區塊200中形成額外的裝置，如低壓金屬氧化物半導體(low voltage metal-oxide-semiconductor, LVMOS)裝置、雙載子接面電晶體(bipolar junction transistors, BJTs)、電容、電阻等。形成於HV區塊200中的裝置係連接至高於500伏特的接地電壓，且具有高的操作電壓(例如大於500伏特)。類似地，可於LV區塊210中形成額外的裝置，如LVMOS裝置、BJTs、電容、電阻等。形成於LV區塊210中的半導體裝置係連接至約0伏特的接地電壓。在此使用的接地電壓指參考電壓。IC 100亦包括圍繞HV區塊200的金屬層。在操作IC 100的步驟中，施加一啟動電壓(boot voltage)VB 至金屬層。
【0012】
以下參照第3圖解釋IC 100之區域A的製造方法，第3圖係沿著第2圖中A-A’連線的IC 100剖面圖。首先，提供基板110。基板110可以係P型基板。HVNW 130係形成於基板110的一部分中。為了維持形成於HV區塊200中之裝置的高操作電壓，在HVNW 130中摻雜約1013 至1015 原子/立方公分(atoms/cm3 )之低濃度的N型摻雜物(例如磷或砷)。形成大塊P型井120鄰近HVNW 130的右側邊緣。HV二極體P型井150係形成於HVNW 130中，且與HVNW 130的右側邊緣分開，如第3圖中所示。在大塊P型井120與HV二極體P型井150中摻雜約1016 至1017 原子/立方公分之濃度的P型摻雜物(例如硼)。HVNW 130的深度大於6微米。HV二極體P型井150的深度與HVNW 130的深度相同。一第一N型內埋層(N-type buried layer, NBL)250係形成於HVNW 130的右側底部。第一NBL 250係垂直地(亦即沿著Z方向)覆蓋HV二極體P型井150，且連接至HV二極體P型井150的底部。一第二NBL 260係形成於HVNW 130的左側底部，如第3圖中所示。在第一NBL 250以及第二NBL 260中摻雜約1016
至1017 原子/立方公分之濃度的N型摻雜物(例如砷或銻)。
【0013】
N型井180係形成於HVNW 130中，N型井180位於大塊P型井120與HV二極體P型井150之間，且鄰近大塊P型井120與HV二極體P型井150。N型井180的右側邊緣鄰近大塊P型井120的左側邊緣，N型井180的左側邊緣鄰近HV二極體P型井150的右側邊緣。在N型井180中摻雜濃度大於HVNW 130之摻雜濃度的N型摻雜物(例如磷或砷)。舉例來說，N型井180的摻雜濃度約為1016 至1017 原子/立方公分。
【0014】
大塊P+區域140係形成於大塊P型井120中。HV二極體P+區域160係形成於HV二極體P型井150中，且與HV二極體P型井150的右側邊緣分開。在大塊P+區域140與HV二極體P+區域160中摻雜約1018
至1020 原子/立方公分之濃度的P型摻雜物(例如硼)。HV二極體N+區域170係形成於HVNW 130中，位於HV二極體P型井150的左側且與HV二極體P型井150分開。源極N+區域195係形成於HV二極體P型井150中，位於HV二極體P+區域160的左側且鄰近HV二極體P+區域160。在HV二極體N+區域170與源極N+區域195中摻雜約1018 至1020 原子/立方公分之濃度的N型摻雜物(例如磷或砷)。HV二極體P+區域160以及HV二極體N+區域170組成HV二極體。
【0015】
漂移區190係形成於HVNW 130中，漂移區190位於HV二極體P型井150與HV二極體N+區域170之間，且與HV二極體P型井150與HV二極體N+區域170分開。漂移區190包括沿著UHV MOS裝置220之通道寬度方向(亦即第2圖中繪示的Y方向)交替地排列的多個第一部分與第二部分。各個第一部分包括一P型頂層190a以及形成於P型頂層190a上的一N型遞變層(grade layer)190b。各個第二部分並不包括任何P-頂層或N-遞變層。在P型頂層190a中摻雜約1013 至1016 原子/立方公分之濃度的P型摻雜物(例如硼)。在N型遞變層190b中摻雜約1013 至1016 原子/立方公分之濃度的N型摻雜物(例如磷或砷)。
【0016】
絕緣層270係形成於基板110上。絕緣層270可以由場氧化物(field oxide, FOX)所形成。形成多個開口於絕緣層270中，以分別地暴露HV二極體N+區域170、源極N+區域195、大塊P+區域140以及HV二極體P+區域160。一閘極氧化層280係形成於基板110上，覆蓋位於源極N+區域195與覆蓋漂移區190的部分絕緣層270之間的基板110之區域。一閘極層290係形成於基板110上，且覆蓋閘極氧化層280。閘極層290可以由多晶矽形成。
【0017】
一層間介電(interlayer dielectric, ILD)層300係形成於基板110上。為了形成觸點(contacts)，蝕刻ILD層300以形成貫孔，貫孔分別對應至HV二極體N+區域170、源極N+區域195、大塊P+區域140以及HV二極體P+區域160。一第一金屬(M1)層310係形成於ILD層300上。圖案化M1層310以形成電性以及實體上分離的部分，這些部分透過形成於ILD層300中的貫孔分別地覆蓋並連接至HV二極體N+區域170、閘極層290、源極N+區域195、大塊P+區域140以及HV二極體P+區域160。一金屬間介電(inter-metal dielectric, IMD)層320係形成於M1層310上且具有作為通孔的貫孔，這些貫孔分別對應到M1層310之分離的部分。一第二金屬(M2)層330係形成於IMD層320上，且包括電性以及實體上分離的部分，這些部分藉由通孔分別地覆蓋並連接至M1層310之分離的部分。
【0018】
第4圖係依照本公開之一說明實施例，沿著第3圖之B-B’連線的IC 100的淨摻雜分布圖。自電腦模擬獲得淨摻雜分布圖。請參照第4圖，N型井180在摻雜濃度約為2×1016 原子/立方公分時具有一峰值，大塊P型井120與HV二極體P型井150兩者在摻雜濃度約為3×1016 原子/立方公分時具有一峰值。第4圖之圖表中的橫坐標刻度代表沿著X方向，與位於HV二極體P型井150左側之給定的一點的距離。
【0019】
第5圖係依照一比較例之IC 500的剖面圖。第6圖係沿著第5圖之C-C’連線之IC 500的淨摻雜分布圖。IC 500的結構與IC 100的結構類似，除了在大塊P型井120與HV二極體P型井150之間沒有形成N型井。請參照第6圖，HVNW 130在摻雜濃度約為4×1015 原子/立方公分時具有一峰值，大塊P型井120與HV二極體P型井150兩者在摻雜濃度約為3×1016 原子/立方公分時具有一峰值。
【0020】
IC 500包括由大塊P型井120(P)、位於大塊P型井120與HV二極體P型井150之間的HVNW 130(N)的一部份以及HV二極體P型井150(P)所組成的一寄生PNP電晶體。大塊P型井120作為寄生PNP電晶體的集極。部分的HVNW 130作為寄生PNP電晶體的基極。HV二極體P型井150作為寄生PNP電晶體的射極。因為寄生PNP電晶體之基極(亦即部分的HVNW 130)的摻雜濃度係相對低的，這是為了維持形成於HV區塊200中之裝置的高操作電壓。當施加相對於HVNW 130約為8.5伏特之正向偏壓至HV二極體P型井150時，以及當少量電流(亦即基極電流)流進HV二極體N+區域170時，寄生PNP電晶體的電流增益(亦即集極與基極電流的比例)係相對大的。因此，自基極流至PNP電晶體之集極的電流(亦即漏電流)量係大的。
【0021】
另一方面，IC 100包括由大塊P型井120(P)、N型井180 (N)以及HV二極體P型井150(P)所組成的一寄生PNP電晶體。因為寄生PNP電晶體之基極(亦即部分的HVNW 130)的摻雜濃度係相對高的，當施加相對於HVNW 130約為8.5伏特之正向偏壓至HV二極體P型井150時，以及當少量電流(亦即基極電流)流進HV二極體N+區域170時，寄生PNP電晶體的電流增益係相對小的。因此，自基極流至PNP電晶體之集極的電流(亦即漏電流)量係相對小的。
【0022】
請參照下列實驗，進一步解釋藉由IC 100中N型井180提供的優點。於實驗中，作為一範例，製造第一裝置以具有如第1-3圖所示之結構。控制第一裝置的摻雜以具有如第4圖所示之淨摻雜分布圖。作為一比較例，製造第二裝置以具有如第5圖所示之結構。控制第二裝置的摻雜以具有如第6圖所示之淨摻雜分布圖。
【0023】
於第一裝置與第二裝置上進行第一高溫操作生命(high temperature operating life, HTOL)測試，第一裝置為範例，第二裝置為比較例。第一HTOL測試評估這些裝置在高溫條件下度過延長的時間周期的可靠度。第一HTOL測試的步驟中，第一裝置與第二裝置在140o C的溫度下正向偏壓持續20小時。也就是說，在140o C的溫度下，各個第一裝置與第二裝置中，大塊P+區域140係連接至接地，並施加8.5伏特的定電壓至HV二極體P+區域160持續20小時。在第一HTOL測試之前以及之後，8.5伏特的定電壓係被施加至HV二極體P+區域160，施加具有各種數值的正電流(positive electrical current)Iboot 至HV二極體N+區域170，以使HV二極體P+區域160相對於NW 180與HVNW 130係正向偏壓，並測量大塊P+區域140的漏電流Ignd 。電流Iboot 自HV二極體N+區域170經過HVNW 130以及NBL 250流至NW 180。如同先前解釋過的，PNP電晶體係由大塊P型井120(P型集極)、位於大塊P型井120與HV二極體P型井150之間的HVNW 130(N)的一部份(N型基極)以及HV二極體P型井150(P型射極)所組成。電流Iboot 係PNP電晶體的基極電流，而電流Ignd 係PNP電晶體的集極電流。理想中的電流Ignd 係要盡可能的低。換句話說，理想中PNP電晶體的電流增益(集極與基極電流的比例)係要盡可能的低。電流增益係受到周圍溫度的影響，使得溫度越高，電流增益就越大。
【0024】
表1總結對於範例以及比較例之第一HTOL測試的結果。表1中，Hfe表示漏電流Ignd 的增益，由Ignd /(Ignd -Ignd,initial )計算得來，其中Ignd,initial 係當Iboot 為0微安培(μA)時測量的起始漏電流Ignd 。
【0025】
表1
 
【0026】
第7圖繪示對比較例之第二裝置進行第一HTOL測試前後所測得
的Ignd 對Iboot 的圖表。第8圖繪示對範例之第一裝置進行第一HTOL測試前後所測得的Ignd 對Iboot 的圖表。
【0027】
依照表1以及第7圖與第8圖，在140o C的溫度下正向偏壓持續20小時之後，比較例之第二裝置的漏電流Ignd 變得較大。另一方面，在140o C的溫度下正向偏壓持續20小時之後，範例之第一裝置的漏電流Ignd 幾乎維持不變。
【0028】
於依照第1-3圖繪示之結構製造的第三裝置上進行第二高溫操作生命(high temperature operating life, HTOL)測試，做為公開實施例的範例。第二HTOL測試的步驟中，第三裝置係在140o C的溫度下正向偏壓持續100小時。第二HTOL測試的偏壓狀態與第一HTOL測試的偏壓狀態相同。在第二HTOL測試前後，施加8.5伏特的定電壓至HV二極體P+區域160，施加具有各種數值的正電
流Iboot 至HV二極體N+區域170，並測量大塊P+區域140的漏電
流Ignd 。
【0029】
表2總結對於範例之第二HTOL測試的結果。
【0030】
表2
 
【0031】
第9圖繪示對範例之第三裝置進行第二HTOL測試前後所測得的Ignd 對Iboot 的圖表。依照表2以及第9圖，第三裝置在140o C的溫度下正向偏壓持續100小時之後，範例之第三裝置的漏電流Ignd
幾乎維持不變。
【0032】
第10圖係依照本公開之另一實施例之IC 1000的剖面圖。IC 1000的結構與IC 100的結構類似，除了形成於N型井180之頂部上的額外的N型井1010，N型井1010位於大塊P型井120與HV二極體P型井150之間。在形成N型井180之後，可以藉由佈植形成N型井1010。此外，相較於IC 100中的第一NBL 250，NBL 1020更延伸至基板110的右側，垂直地(亦即沿著Z方向)覆蓋HV二極體P型井150、N型井180以及大塊P型井120。因為電流幾乎在N型井180的表面流動，為了進一步自大塊P型井120分離HV二極體P型井150，N型井1010的摻雜濃度大於N型井180的摻雜濃度。
【0033】
第11圖係依照本公開之另一實施例之IC 1100的剖面圖。IC 1100的結構與IC 100的結構類似，除了大塊P型井120’以及HV二極體P型井150’的深度小於HVNW 130的深度。因為淺的大塊P型井120’以及淺的HV二極體P型井150’，IC 1100不包括任何NBL。
【0034】
雖然上述實施例中的IC 100係被提供於P型半導體基板上，本發明所屬技術領域具有通常知識者將明瞭此公開的概念也適用被提供於其他適合之基板上的ICs，如絕緣底半導體(semiconductor on insulator, SOI)基板。
【0035】
雖然上述實施例中IC 100的絕緣層270係由場氧化物製成，絕緣層270可以由其他適合的介電絕緣材料製成，如淺溝槽隔離(shallow trench isolation, STI)結構。
【0036】
雖然上述實施例中的IC 100包括兩層金屬層，亦即M1層310與M2層330，本發明所屬技術領域具有通常知識者將明瞭此公開的概念也適用於包括任何數目之金屬層的ICs，例如單一金屬層，或三或更多層金屬層。
【0037】
雖然上述實施例中的IC 100包括漂移區190，漂移區190包括P型頂層190a與N型遞變層190b，本發明所屬技術領域具有通常知識者將明瞭此公開的概念也適用於包括漂移區的ICs，其中漂移區不包括P型頂層與N型遞變層。
【0038】
上述實施例中的ICs 100、1000、1100可以被應用做為用於各種應用的高電壓開關，舉例來說，發光二極體(light emitting diode, LED)、省電燈、鎮流器應用(ballast applications)以及馬達驅動器應用。
【0039】
經由在此揭露本發明之說明書以及實施，所屬技術領域中具有通常知識者將能明瞭本發明的其他實施例。意指說明書以及範例僅被認為是範例性的，本發明之真實的保護範圍與精神當視後附之申請專利範圍所界定者為準。
100‧‧‧積體電路
110‧‧‧基板
120‧‧‧大塊P型井
130‧‧‧高電壓N型井
140‧‧‧大塊P+區域
150‧‧‧HV二極體P型井
160‧‧‧HV二極體P+區域
170‧‧‧HV二極體N+區域
180‧‧‧N型井
190‧‧‧漂移區
190a‧‧‧P型頂層
190b‧‧‧N型遞變層
195‧‧‧源極N+區域
250‧‧‧第一N型內埋層
260‧‧‧第二N型內埋層
270‧‧‧絕緣層
280‧‧‧閘極氧化層
290‧‧‧閘極層
300‧‧‧層間介電層
310‧‧‧第一金屬層
320‧‧‧金屬間介電層
330‧‧‧第二金屬層
B-B’‧‧‧連線

Claims (20)

  1. 【第1項】
    一種半導體裝置，包括：
    一基板；
    一高電壓N型井，配置於該基板中；
    一大塊P型井，配置於該基板中且鄰近該高電壓N型井之一邊緣；
    一高電壓二極體，配置於該高電壓N型井中，該高電壓二極體包括一高電壓二極體P型井，該高電壓二極體P型井配置於該高電壓N型井中，且與該高電壓N型井的該邊緣分開；以及
    一N型井，配置於該高電壓N型井中，且位於該高電壓二極體P型井與該大塊P型井之間；
    其中該N型井的摻雜濃度大於該高電壓N型井的摻雜濃度。
  2. 【第2項】
    如申請專利範圍第1項所述之半導體裝置，更包括一大塊P+區域，配置於該大塊P型井中。
  3. 【第3項】
    如申請專利範圍第2項所述之半導體裝置，其中該高電壓二極體更包括：
    一高電壓二極體P+區域，配置於該高電壓二極體P型井中；及
    一高電壓二極體N+區域，配置於該高電壓N型井中，且與該高電壓二極體P型井分開；
    該高電壓二極體P型井係配置於該高電壓二極體N+區域與該高電壓N型井之該邊緣之間。
  4. 【第4項】
    如申請專利範圍第3項所述之半導體裝置，更包括：
    一絕緣層，配置於該基板上，且包括複數個開口，該些開口分別暴露該高電壓二極體N+區域、該高電壓二極體P+區域以及該大塊P+區域；及
    一金屬層，配置於該絕緣層上，且包括複數個分離部分，該些分離部分分別連接至該高電壓二極體N+區域、該高電壓二極體P+區域以及該大塊P+區域。
  5. 【第5項】
    如申請專利範圍第4項所述之半導體裝置，其中該絕緣層係一第一絕緣層，該金屬層係一第一金屬層，該半導體裝置更包括：
    一額外的絕緣層，配置於該第一金屬層上；及
    一額外的金屬層，配置於該額外的絕緣層上。
  6. 【第6項】
    如申請專利範圍第1項所述之半導體裝置，其中該N型井係一第一N型井，該半導體裝置包括：
    一第二N型井，配置於該第一N型井之頂部上；
    該第一N型井的摻雜濃度大於該第二N型井的摻雜濃度。
  7. 【第7項】
    如申請專利範圍第3項所述之半導體裝置，更包括一漂移區，配置於該高電壓二極體N+區域與該高電壓二極體P型井之間。
  8. 【第8項】
    如申請專利範圍第1項所述之半導體裝置，其中該高電壓二極體P型井之深度與該高電壓N型井之深度相同；且
    該半導體裝置更包括一N型內埋層，垂直地覆蓋且連接至該高電壓二極體P型井之底部。
  9. 【第9項】
    如申請專利範圍第1項所述之半導體裝置，其中該高電壓二極體P型井之深度小於該高電壓N型井之深度。
  10. 【第10項】
    一種半導體裝置的製造方法，包括：
    形成一高電壓N型井於一基板中；
    形成一大塊P型井於該基板中，該大塊P型井位於該高電壓N型井外，且鄰近該高電壓N型井之一邊緣；
    形成一高電壓二極體P型井於該高電壓N型井中，且該高電壓二極體P型井與該高電壓N型井之該邊緣分開；以及
    形成一N型井於該高電壓N型井中，且該N型井位於該高電壓二極體P型井與該大塊P型井之間，該N型井之摻雜濃度大於該高電壓N型井之摻雜濃度。
  11. 【第11項】
    如申請專利範圍第10項所述之方法，包括：
    形成一大塊P+區域於該大塊P型井中；
    形成一高電壓二極體P+區域於該高電壓二極體P型井中；及
    形成一高電壓二極體N+區域於該高電壓N型井中，且該高電壓二極體N+區域與該高電壓二極體P型井分開，使該高電壓二極體P型井係配置於該高電壓二極體N+區域與該高電壓N型井之該邊緣之間。
  12. 【第12項】
    如申請專利範圍第11項所述之方法，更包括：
    形成一絕緣層於該基板上，該絕緣層包括複數個開口，該些開口分別暴露該高電壓二極體N+區域、該高電壓二極體P+區域與該大塊P+區域；
    形成一金屬層於該絕緣層上，該金屬層包括複數個分離部分，該些分離部分分別連接至該高電壓二極體N+區域、該高電壓二極體P+區域以及該大塊P+區域。
  13. 【第13項】
    如申請專利範圍第12項所述之方法，其中該絕緣層係一第一絕緣層，該金屬層係一第一金屬層，且該方法更包括：
    形成一額外的絕緣層於該第一金屬層上；及
    形成一額外的金屬層於該額外的絕緣層上。
  14. 【第14項】
    如申請專利範圍第10項所述之方法，其中該N型井係一第一N型井，該方法更包括：
    形成一第二N型井於該第一N型井之頂部上，該第一N型井的摻雜濃度大於該第二N型井的摻雜濃度。
  15. 【第15項】
    如申請專利範圍第11項所述之方法，更包括：
    形成一漂移區於該高電壓二極體N+區域與該高電壓二極體P型井之間。
  16. 【第16項】
    如申請專利範圍第10項所述之方法，其中該高電壓二極體P型井的深度大於該高電壓N型井的深度，且該方法更包括：
    形成一N型內埋層，該N型內埋層垂直地覆蓋且連接至該高電壓二極體P型井之底部。
  17. 【第17項】
    如申請專利範圍第10項所述之方法，其中該高電壓二極體P型井之深度係小於該高電壓N型井之深度。
  18. 【第18項】
    一種積體電路，包括：
    一基板；
    一高電壓N型井，配置於該基板中；
    一大塊P型井，配置於該高電壓N型井外且圍繞該高電壓N型井；
    一高電壓二極體，配置於該高電壓N型井內，該高電壓二極體包括一高電壓二極體P型井，該高電壓二極體P型井係沿著該高電壓N型井之一邊緣配置，且與該高電壓N型井的該邊緣分開；以及
    一N型井，沿著該高電壓N型井之該邊緣配置，且位於該高電壓二極體P型井與該高電壓N型井之該邊緣之間；
    其中該N型井之摻雜濃度大於該高電壓N型井之摻雜濃度。
  19. 【第19項】
    如申請專利範圍第18項所述之積體電路，其中該高電壓二極體更包括：
    一高電壓二極體P+區域，配置於該高電壓二極體P型井中；
    一高電壓二極體N+區域，配置於該高電壓N型井中且與該高電壓二極體P型井分開。
  20. 【第20項】
    如申請專利範圍第18項所述之積體電路，其中該基板包括一高電壓區塊及一低電壓區塊，該高電壓區塊配置於該高電壓N型井內，該低電壓區塊配置於該高電壓N型井外。
TW103134698A 2014-08-07 2014-10-06 包括高電壓二極體之半導體裝置 TWI536542B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/454,153 US9443754B2 (en) 2014-08-07 2014-08-07 Semiconductor device including high-voltage diode

Publications (2)

Publication Number Publication Date
TW201606985A TW201606985A (zh) 2016-02-16
TWI536542B true TWI536542B (zh) 2016-06-01

Family

ID=55268030

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103134698A TWI536542B (zh) 2014-08-07 2014-10-06 包括高電壓二極體之半導體裝置

Country Status (3)

Country Link
US (1) US9443754B2 (zh)
CN (1) CN105590927A (zh)
TW (1) TWI536542B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI597847B (zh) * 2016-09-05 2017-09-01 新唐科技股份有限公司 高壓半導體裝置
US10096722B2 (en) * 2016-10-04 2018-10-09 Macronix International Co., Ltd. Semiconductor device and method of forming the same
TWI629785B (zh) * 2016-12-29 2018-07-11 新唐科技股份有限公司 高電壓積體電路的高電壓終端結構
TWI609487B (zh) * 2016-12-30 2017-12-21 新唐科技股份有限公司 半導體裝置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7868387B2 (en) * 2008-06-13 2011-01-11 Analog Devices, Inc. Low leakage protection device
US8749016B2 (en) * 2010-10-06 2014-06-10 Macronix International Co., Ltd. High voltage MOS device and method for making the same
US8610209B2 (en) * 2011-03-24 2013-12-17 Macronix International Co., Ltd. Ultra-high voltage N-type-metal-oxide-semiconductor (UHV NMOS) device and methods of manufacturing the same
US9030855B2 (en) * 2011-07-14 2015-05-12 Macronix International Co., Ltd. Semiconductor device, start-up circuit having first and second circuits and a single voltage output terminal coupled to a second node between the semiconductor unit and the first circuit, and operating method for the same
US20130265102A1 (en) * 2012-04-09 2013-10-10 Macronix International Co., Ltd. Semiconductor structure and method for manufacturing the same
KR101450437B1 (ko) * 2013-03-12 2014-10-14 주식회사 동부하이텍 Ldmos 소자와 그 제조 방법
US9147677B2 (en) * 2013-05-16 2015-09-29 Analog Devices Global Dual-tub junction-isolated voltage clamp devices for protecting low voltage circuitry connected between high voltage interface pins and methods of forming the same
US9171832B2 (en) * 2013-05-24 2015-10-27 Analog Devices, Inc. Analog switch with high bipolar blocking voltage in low voltage CMOS process

Also Published As

Publication number Publication date
US20160043180A1 (en) 2016-02-11
US9443754B2 (en) 2016-09-13
CN105590927A (zh) 2016-05-18
TW201606985A (zh) 2016-02-16

Similar Documents

Publication Publication Date Title
US10211196B2 (en) Electrostatic discharge protection device and electronic device having the same
TWI580034B (zh) 具有埋層之半導體裝置
KR101847227B1 (ko) Esd 트랜지스터
US9349732B2 (en) High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region
US20140065781A1 (en) Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same
US9059281B2 (en) Dual L-shaped drift regions in an LDMOS device and method of making the same
US10262997B2 (en) High-voltage LDMOSFET devices having polysilicon trench-type guard rings
TWI536542B (zh) 包括高電壓二極體之半導體裝置
TWI531070B (zh) 具有金屬層於漂移區之上的半導體元件
TWI440183B (zh) 超高電壓ｎ型金屬氧化物半導體元件及其製造方法
JP6381067B2 (ja) 半導体装置および半導体装置の製造方法
CN107078059B (zh) 改进bcd技术中的横向bjt特性
US10505037B2 (en) P-channel DEMOS device
US7667295B2 (en) Semiconductor device
US9087708B2 (en) IC with floating buried layer ring for isolation of embedded islands
US20150048452A1 (en) Ultra-high voltage semiconductor having an isolated structure for high side operation and method of manufacture
TW201539745A (zh) 高壓半導體元件及其製造方法
US6995453B2 (en) High voltage integrated circuit including bipolar transistor within high voltage island area
TW201730971A (zh) 高壓半導體裝置及其製造方法
US8698194B2 (en) Semiconductor integrated circuit with high withstand voltage element forming trench isolation on substrate
US9035381B2 (en) Semiconductor device and method of fabricating the same
JP6188205B2 (ja) 高降伏電圧を有するバイポーラトランジスタ
CN107146814A (zh) 高压半导体装置及其制造方法
US9608109B1 (en) N-channel demos device
US20120248542A1 (en) Transistor with adjustable supply and/or threshold voltage