CN105590927A - 包括高电压二极管的半导体装置及其制造方法 - Google Patents

包括高电压二极管的半导体装置及其制造方法 Download PDF

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CN105590927A
CN105590927A CN201410565917.6A CN201410565917A CN105590927A CN 105590927 A CN105590927 A CN 105590927A CN 201410565917 A CN201410565917 A CN 201410565917A CN 105590927 A CN105590927 A CN 105590927A
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high voltage
type
type trap
region
diode
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张宇瑞
林正基
连士进
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Macronix International Co Ltd
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Macronix International Co Ltd
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Abstract

本发明公开了一种包括高电压二极管的半导体装置及其制造方法，该半导体装置包括：一基板、配置于基板中的一高电压N型阱(high-voltage？N-well，HVNW)、配置于基板中且邻近HVNW是边缘的一大块P型阱、配置于HVNW中的一高电压(high-voltage，HV)二极管，HV二极管包括配置于HVNW中且与HVNW是边缘分开的一HV二极管P型阱以及配置于HVNW中且位于HV二极管P型阱与大块P型阱之间的一N型阱。N型阱的掺杂浓度大于HVNW的掺杂浓度。

Description

包括高电压二极管的半导体装置及其制造方法
技术领域
本公开是有关于一种包括高电压(high-voltage，HV)二极管的半导体装置，且特别是有关于一种包括连接寄生PNP装置的高电压二极管的半导体装置及其制造方法。
背景技术
超高压半导体装置被广泛地使用于显示设备、便携设备以及许多其他的应用。通常，集成电路包括超高压半导体装置，亦包括可以做为高电压二极管的的二极管。
发明内容
依照本发明的一实施例，一种半导体装置，包括：一基板、配置于基板中的一高电压N型阱(high-voltageN-well，HVNW)、配置于基板中且邻近HVNW是边缘的一大块P型阱、配置于HVNW中的一高电压(high-voltage，HV)二极管，HV二极管包括配置于HVNW中且与HVNW是边缘分开的一HV二极管P型阱以及配置于HVNW中且位于HV二极管P型阱与大块P型阱之间的一N型阱。N型阱的掺杂浓度大于HVNW的掺杂浓度。
依照本发明的另一实施例，一种半导体装置的制造方法包括：于基板中形成高电压N型阱(high-voltageN-well，HVNW)，于基板中形成在HVNW外且邻近HVNW是边缘的大块P型阱，于HVNW中形成HV二极管P型阱，且HV二极管P型阱与HVNW是边缘分开，以及形成位于HVNW中且位于HV二极管P型阱与大块P型阱之间的N型阱，包括形成此N型阱以具有大于HVNW的掺杂浓度的掺杂浓度。
依照本发明的又一实施例，一种集成电路，包括：基板、配置于基板中的高电压N型阱(high-voltageN-well，HVNW)、配置于HVNW外且围绕HVNW的大块P型阱、配置于HVNW内的高电压(high-voltage，HV)二极管，并且包括沿着HVNW是边缘配置且与HVNW是边缘分开的HV二极管P型阱，以及沿着HVNW是边缘配置且位于HV二极管P型阱与HVNW的边缘之间的N型阱。N型阱的掺杂浓度大于HVNW的掺杂浓度。
为了对本发明的上述及其他方面有更佳的了解，下文特举较佳实施例，并配合所附图式，作详细说明如下：
附图说明
图1绘示依照本发明的一说明实施例的集成电路(integratedcircuit，IC)的平面图。
图2绘示依照本发明的一说明实施例，图1的IC的区域A的放大平面图。
图3绘示沿着图2的A-A’联机的IC剖面图。
图4绘示依照本发明的一说明实施例，沿着图3的B-B’联机的净掺杂分布图。
图5绘示依照一比较例的IC的剖面图。
图6绘示沿着图5的C-C’联机，图5的IC的净掺杂分布图。
图7绘示对依照图5制造的一装置进行高温操作生命(hightemperatureoperatinglife，HTOL)测试前后所测得的漏电流(Ignd)对正电流(Iboot)的图表，作为一比较例。
图8绘示对依照图3制造的一装置进行第一HTOL测试前后所测得的Ignd对Iboot的图表，作为一范例。
图9绘示对依照图3制造的一装置进行第二HTOL测试前后所测得的Ignd对Iboot的图表，作为一范例。
图10绘示依照本发明的另一说明实施例的IC的剖面图。
图11绘示依照本发明的又一说明实施例的IC的剖面图。
【符号说明】
100、500、1000、1100：集成电路
110：基板
120、120’：大块P型阱
130：高电压N型阱
140：大块P+区域
150、150’：HV二极管P型阱
160：HV二极管P+区域
170：HV二极管N+区域
180、1010：N型阱
190：漂移区
190a：P型顶层
190b：N型递变层
195：源极N+区域
200：高电压区块
210：低电压区块
220、230：超高压金属氧化物半导体装置
250：第一N型内埋层
260：第二N型内埋层
270：绝缘层
280：栅极氧化层
290：栅极层
300：层间介电层
310：第一金属层
320：金属间介电层
330：第二金属层
1020：N型内埋层
A：区域
A-A’、B-B’：联机
具体实施方式
以下将详细地叙述本实施例，本实施例的范例绘示于所附图式中。只要有可能，图式中从头到尾将使用相同的组件符号以代表相同或类似的部分。
图1绘示依照本发明的一说明实施例的集成电路(integratedcircuit，IC)100的平面图。图2绘示依照本发明的一说明实施例，IC100的区域A的放大平面图。图3绘示沿着图2的A-A’联机的IC100剖面图。
请参照图1以及图2，于一基板110上提供IC100，基板110具有围绕一高电压N型阱(high-voltageN-well，HVNW)130的一大块P型阱120。一大块P+区域140是配置于大块P型阱120内。一高电压(high-voltage，HV)二极管是配置于HVNW130内。高电压二极管包括沿着HVNW130是边缘配置且与HVNW130是边缘分开的一HV二极管P型阱150、配置于HV二极管P型阱150中的HV二极管P+区域160以及沿着HVNW130的上侧边缘部分、右侧边缘部分与下侧边缘部分的HV二极管N+区域170，如图1中所示。配置一N型阱180邻近且沿着HVNW130的边缘。配置N型阱180邻近HV二极管P型阱150与大块P型阱120两者，且位于HV二极管P型阱150与大块P型阱120之间。漂移区190是配置于由HV二极管P型阱150围绕的区块内，且漂移区190沿着HV二极管P型阱150是边缘并与HV二极管P型阱150是边缘分开。一源极N+区域195是配置于HV二极管P型阱150中，且邻近HV二极管P+区域160。
基板110包括位于HVNW130内的一高电压(highvoltage，HV)区块200，以及位于HVNW130外且位于HVNW130的左侧与下侧的一低电压(lowvoltage，LV)区块210，如图1中所示。IC100包括位于HV区块200与LV区块210之间的两个超高压金属氧化物半导体(ultra-highvoltagemetal-oxide-semiconductor，UHVMOS)装置220以及230。UHVMOS装置220以及230的结构类似，但是可以具有不同的操作电压，如栅极电压、源极电压、漏极电压以及体电压(bulkvoltage)。UHVMOS装置220以及230两者都具有相对高的崩溃电压，大于500伏特。虽然图1仅绘示两个UHVMOS装置220以及230，可于HV区块200中形成额外的装置，如低压金属氧化物半导体(lowvoltagemetal-oxide-semiconductor，LVMOS)装置、双载子结晶体管(bipolarjunctiontransistors，BJTs)、电容、电阻等。形成于HV区块200中的装置被连接至高于500伏特的接地电压，且具有高的操作电压(例如大于500伏特)。类似地，可于LV区块210中形成额外的装置，如LVMOS装置、BJTs、电容、电阻等。形成于LV区块210中的半导体装置被连接至约0伏特的接地电压。在此使用的接地电压指参考电压。IC100亦包括围绕HV区块200的金属层。在操作IC100的步骤中，施加一启动电压(bootvoltage)VB至金属层。
以下参照图3解释IC100的区域A的制造方法，图3是沿着图2中A-A’联机的IC100剖面图。首先，提供基板110。基板110可以是P型基板。HVNW130是形成于基板110的一部分中。为了维持形成于HV区块200中的装置的高操作电压，在HVNW130中掺杂约1013至1015原子/立方厘米(atoms/cm3)的低浓度的N型掺杂物(例如磷或砷)。形成大块P型阱120邻近HVNW130的右侧边缘。HV二极管P型阱150是形成于HVNW130中，且与HVNW130的右侧边缘分开，如图3中所示。在大块P型阱120与HV二极管P型阱150中掺杂约1016至1017原子/立方厘米的浓度的P型掺杂物(例如硼)。HVNW130的深度大于6微米。HV二极管P型阱150的深度与HVNW130的深度相同。一第一N型内埋层(N-typeburiedlayer，NBL)250是形成于HVNW130的右侧底部。第一NBL250是垂直地(亦即沿着Z方向)覆盖HV二极管P型阱150，且连接至HV二极管P型阱150的底部。一第二NBL260是形成于HVNW130的左侧底部，如图3中所示。在第一NBL250以及第二NBL260中掺杂约1016至1017原子/立方厘米的浓度的N型掺杂物(例如砷或锑)。
N型阱180是形成于HVNW130中，N型阱180位于大块P型阱120与HV二极管P型阱150之间，且邻近大块P型阱120与HV二极管P型阱150。N型阱180的右侧边缘邻近大块P型阱120的左侧边缘，N型阱180的左侧边缘邻近HV二极管P型阱150的右侧边缘。在N型阱180中掺杂浓度大于HVNW130的掺杂浓度的N型掺杂物(例如磷或砷)。举例来说，N型阱180的掺杂浓度约为1016至1017原子/立方厘米。
大块P+区域140是形成于大块P型阱120中。HV二极管P+区域160是形成于HV二极管P型阱150中，且与HV二极管P型阱150的右侧边缘分开。在大块P+区域140与HV二极管P+区域160中掺杂约1018至1020原子/立方厘米的浓度的P型掺杂物(例如硼)。HV二极管N+区域170是形成于HVNW130中，位于HV二极管P型阱150的左侧且与HV二极管P型阱150分开。源极N+区域195是形成于HV二极管P型阱150中，位于HV二极管P+区域160的左侧且邻近HV二极管P+区域160。在HV二极管N+区域170与源极N+区域195中掺杂约1018至1020原子/立方厘米的浓度的N型掺杂物(例如磷或砷)。HV二极管P+区域160以及HV二极管N+区域170组成HV二极管。
漂移区190是形成于HVNW130中，漂移区190位于HV二极管P型阱150与HV二极管N+区域170之间，且与HV二极管P型阱150与HV二极管N+区域170分开。漂移区190包括沿着UHVMOS装置220的通道宽度方向(亦即图2中绘示的Y方向)交替地排列的多个第一部分与第二部分。各个第一部分包括一P型顶层190a以及形成于P型顶层190a上的一N型递变层(gradelayer)190b。各个第二部分并不包括任何P-顶层或N-递变层。在P型顶层190a中掺杂约1013至1016原子/立方厘米的浓度的P型掺杂物(例如硼)。在N型递变层190b中掺杂约1013至1016原子/立方厘米的浓度的N型掺杂物(例如磷或砷)。
绝缘层270是形成于基板110上。绝缘层270可以由场氧化物(fieldoxide，FOX)所形成。形成多个开口于绝缘层270中，以分别地暴露HV二极管N+区域170、源极N+区域195、大块P+区域140以及HV二极管P+区域160。一栅极氧化层280是形成于基板110上，覆盖位于源极N+区域195与覆盖漂移区190的部分绝缘层270之间的基板110的区域。一栅极层290是形成于基板110上，且覆盖栅极氧化层280。栅极层290可以由多晶硅形成。
一层间介电(interlayerdielectric，ILD)层300是形成于基板110上。为了形成触点(contacts)，蚀刻ILD层300以形成贯孔，贯孔分别对应至HV二极管N+区域170、源极N+区域195、大块P+区域140以及HV二极管P+区域160。一第一金属(M1)层310是形成于ILD层300上。图案化M1层310以形成电性以及实体上分离的部分，这些部分透过形成于ILD层300中的贯孔分别地覆盖并连接至HV二极管N+区域170、栅极层290、源极N+区域195、大块P+区域140以及HV二极管P+区域160。一金属间介电(inter-metaldielectric，IMD)层320是形成于M1层310上且具有作为通孔的贯孔，这些贯孔分别对应到M1层310的分离的部分。一第二金属(M2)层330是形成于IMD层320上，且包括电性以及实体上分离的部分，这些部分通过通孔分别地覆盖并连接至M1层310的分离的部分。
图4是依照本发明的一说明实施例，沿着图3的B-B’联机的IC100的净掺杂分布图。自计算机仿真获得净掺杂分布图。请参照图4，N型阱180在掺杂浓度约为2×1016原子/立方厘米时具有一峰值，大块P型阱120与HV二极管P型阱150两者在掺杂浓度约为3×1016原子/立方厘米时具有一峰值。图4的图表中的横坐标刻度代表沿着X方向，与位于HV二极管P型阱150左侧的给定的一点的距离。
图5是依照一比较例的IC500的剖面图。图6是沿着图5的C-C’联机的IC500的净掺杂分布图。IC500的结构与IC100的结构类似，除了在大块P型阱120与HV二极管P型阱150之间没有形成N型阱。请参照图6，HVNW130在掺杂浓度约为4×1015原子/立方厘米时具有一峰值，大块P型阱120与HV二极管P型阱150两者在掺杂浓度约为3×1016原子/立方厘米时具有一峰值。
IC500包括由大块P型阱120(P)、位于大块P型阱120与HV二极管P型阱150之间的HVNW130(N)的一部份以及HV二极管P型阱150(P)所组成的一寄生PNP晶体管。大块P型阱120作为寄生PNP晶体管的集极。部分的HVNW130作为寄生PNP晶体管的基极。HV二极管P型阱150作为寄生PNP晶体管的射极。因为寄生PNP晶体管的基极(亦即部分的HVNW130)的掺杂浓度是相对低的，这是为了维持形成于HV区块200中的装置的高操作电压。当施加相对于HVNW130约为8.5伏特的正向偏压至HV二极管P型阱150时，以及当少量电流(亦即基极电流)流进HV二极管N+区域170时，寄生PNP晶体管的电流增益(亦即集极与基极电流的比例)是相对大的。因此，自基极流至PNP晶体管的集极的电流(亦即漏电流)量是大的。
另一方面，IC100包括由大块P型阱120(P)、N型阱180(N)以及HV二极管P型阱150(P)所组成的一寄生PNP晶体管。因为寄生PNP晶体管的基极(亦即部分的HVNW130)的掺杂浓度是相对高的，当施加相对于HVNW130约为8.5伏特的正向偏压至HV二极管P型阱150时，以及当少量电流(亦即基极电流)流进HV二极管N+区域170时，寄生PNP晶体管的电流增益是相对小的。因此，自基极流至PNP晶体管的集极的电流(亦即漏电流)量是相对小的。
请参照下列实验，进一步解释通过IC100中N型阱180提供的优点。于实验中，作为一范例，制造第一装置以具有如图1-图3所示的结构。控制第一装置的掺杂以具有如图4所示的净掺杂分布图。作为一比较例，制造第二装置以具有如图5所示的结构。控制第二装置的掺杂以具有如图6所示的净掺杂分布图。
于第一装置与第二装置上进行第一高温操作生命(hightemperatureoperatinglife，HTOL)测试，第一装置为范例，第二装置为比较例。第一HTOL测试评估这些装置在高温条件下度过延长的时间周期的可靠度。第一HTOL测试的步骤中，第一装置与第二装置在140℃的温度下正向偏压持续20小时。也就是说，在140℃的温度下，各个第一装置与第二装置中，大块P+区域140被连接至接地，并施加8.5伏特的定电压至HV二极管P+区域160持续20小时。在第一HTOL测试之前以及之后，8.5伏特的定电压是被施加至HV二极管P+区域160，施加具有各种数值的正电流(positiveelectricalcurrent)Iboot至HV二极管N+区域170，以使HV二极管P+区域160相对于NW180与HVNW130是正向偏压，并测量大块P+区域140的漏电流Ignd。电流Iboot自HV二极管N+区域170经过HVNW130以及NBL250流至NW180。如同先前解释过的，PNP晶体管是由大块P型阱120(P型集极)、位于大块P型阱120与HV二极管P型阱150之间的HVNW130(N)的一部份(N型基极)以及HV二极管P型阱150(P型射极)所组成。电流Iboot是PNP晶体管的基极电流，而电流Ignd是PNP晶体管的集极电流。理想中的电流Ignd是要尽可能的低。换句话说，理想中PNP晶体管的电流增益(集极与基极电流的比例)是要尽可能的低。电流增益是受到周围温度的影响，使得温度越高，电流增益就越大。
表1总结对于范例以及比较例的第一HTOL测试的结果。表1中，Hfe表示漏电流Ignd的增益，由Ignd/(Ignd-Ignd，initial)计算得来，其中Ignd，initial是当Iboot为0微安培(μA)时测量的起始漏电流Ignd。
表1
图7绘示对比较例的第二装置进行第一HTOL测试前后所测得的Ignd对Iboot的图表。图8绘示对范例的第一装置进行第一HTOL测试前后所测得的Ignd对Iboot的图表。
依照表1以及图7与图8，在140℃的温度下正向偏压持续20小时之后，比较例的第二装置的漏电流Ignd变得较大。另一方面，在140℃的温度下正向偏压持续20小时之后，范例的第一装置的漏电流Ignd几乎维持不变。
于依照图1-图3绘示的结构制造的第三装置上进行第二高温操作生命(hightemperatureoperatinglife，HTOL)测试，做为公开实施例的范例。第二HTOL测试的步骤中，第三装置是在140℃的温度下正向偏压持续100小时。第二HTOL测试的偏压状态与第一HTOL测试的偏压状态相同。在第二HTOL测试前后，施加8.5伏特的定电压至HV二极管P+区域160，施加具有各种数值的正电流Iboot至HV二极管N+区域170，并测量大块P+区域140的漏电流Ignd。
表2总结对于范例的第二HTOL测试的结果。
表2
图9绘示对范例的第三装置进行第二HTOL测试前后所测得的Ignd对Iboot的图表。依照表2以及图9，第三装置在140℃的温度下正向偏压持续100小时之后，范例的第三装置的漏电流Ignd几乎维持不变。
图10是依照本发明的另一实施例的IC1000的剖面图。IC1000的结构与IC100的结构类似，除了形成于N型阱180的顶部上的额外的N型阱1010，N型阱1010位于大块P型阱120与HV二极管P型阱150之间。在形成N型阱180之后，可以通过注入形成N型阱1010。此外，相较于IC100中的第一NBL250，NBL1020更延伸至基板110的右侧，垂直地(亦即沿着Z方向)覆盖HV二极管P型阱150、N型阱180以及大块P型阱120。因为电流几乎在N型阱180的表面流动，为了进一步自大块P型阱120分离HV二极管P型阱150，N型阱1010的掺杂浓度大于N型阱180的掺杂浓度。
图11是依照本发明的另一实施例的IC1100的剖面图。IC1100的结构与IC100的结构类似，除了大块P型阱120’以及HV二极管P型阱150’的深度小于HVNW130的深度。因为浅的大块P型阱120’以及浅的HV二极管P型阱150’，IC1100不包括任何NBL。
虽然上述实施例中的IC100是被提供于P型半导体基板上，本发明所属技术领域具有通常知识者将明了此公开的概念也适用被提供于其他适合的基板上的ICs，如绝缘底半导体(semiconductoroninsulator，SOI)基板。
虽然上述实施例中IC100的绝缘层270是由场氧化物制成，绝缘层270可以由其他适合的介电绝缘材料制成，如浅沟道隔离(shallowtrenchisolation，STI)结构。
虽然上述实施例中的IC100包括两层金属层，亦即M1层310与M2层330，本发明所属技术领域具有通常知识者将明了此公开的概念也适用于包括任何数目的金属层的ICs，例如单一金属层，或三或更多层金属层。
虽然上述实施例中的IC100包括漂移区190，漂移区190包括P型顶层190a与N型递变层190b，本发明所属技术领域具有通常知识者将明了此公开的概念也适用于包括漂移区的ICs，其中漂移区不包括P型顶层与N型递变层。
上述实施例中的ICs100、1000、1100可以被应用做为用于各种应用的高电压开关，举例来说，发光二极管(lightemittingdiode，LED)、省电灯、镇流器应用(ballastapplications)以及马达驱动器应用。
经由在此揭露本发明的说明书以及实施，所属技术领域中具有通常知识者将能明了本发明的其他实施例。意指说明书以及范例仅被认为是范例性的，本发明的真实的保护范围与精神当视随附的权利要求范围所界定的为准。

Claims (20)

1.一种半导体装置，包括：
一基板；
一高电压N型阱，配置于该基板中；
一大块P型阱，配置于该基板中且邻近该高电压N型阱的一边缘；
一高电压二极管，配置于该高电压N型阱中，该高电压二极管包括一高电压二极管P型阱，该高电压二极管P型阱配置于该高电压N型阱中，且与该高电压N型阱的该边缘分开；以及
一N型阱，配置于该高电压N型阱中，且位于该高电压二极管P型阱与该大块P型阱之间；
其中该N型阱的掺杂浓度大于该高电压N型阱的掺杂浓度。
2.根据权利要求1所述的半导体装置，更包括一大块P+区域，配置于该大块P型阱中。
3.根据权利要求2所述的半导体装置，其中该高电压二极管更包括：
一高电压二极管P+区域，配置于该高电压二极管P型阱中；及
一高电压二极管N+区域，配置于该高电压N型阱中，且与该高电压二极管P型阱分开；
该高电压二极管P型阱是配置于该高电压二极管N+区域与该高电压N型阱的该边缘之间。
4.根据权利要求3所述的半导体装置，更包括：
一绝缘层，配置于该基板上，且包括多个开口，这些开口分别暴露该高电压二极管N+区域、该高电压二极管P+区域以及该大块P+区域；及
一金属层，配置于该绝缘层上，且包括多个分离部分，这些分离部分分别连接至该高电压二极管N+区域、该高电压二极管P+区域以及该大块P+区域。
5.根据权利要求4所述的半导体装置，其中该绝缘层是一第一绝缘层，该金属层是一第一金属层，该半导体装置更包括：
一额外的绝缘层，配置于该第一金属层上；及
一额外的金属层，配置于该额外的绝缘层上。
6.根据权利要求1所述的半导体装置，其中该N型阱是一第一N型阱，该半导体装置包括：
一第二N型阱，配置于该第一N型阱的顶部上；
该第一N型阱的掺杂浓度大于该第二N型阱的掺杂浓度。
7.根据权利要求3所述的半导体装置，更包括一漂移区，配置于该高电压二极管N+区域与该高电压二极管P型阱之间。
8.根据权利要求1所述的半导体装置，其中该高电压二极管P型阱的深度与该高电压N型阱的深度相同；且
该半导体装置更包括一N型内埋层，垂直地覆盖且连接至该高电压二极管P型阱的底部。
9.根据权利要求1所述的半导体装置，其中该高电压二极管P型阱的深度小于该高电压N型阱的深度。
10.一种半导体装置的制造方法，包括：
形成一高电压N型阱于一基板中；
形成一大块P型阱于该基板中，该大块P型阱位于该高电压N型阱外，且邻近该高电压N型阱的一边缘；
形成一高电压二极管P型阱于该高电压N型阱中，且该高电压二极管P型阱与该高电压N型阱的该边缘分开；以及
形成一N型阱于该高电压N型阱中，且该N型阱位于该高电压二极管P型阱与该大块P型阱之间，该N型阱的掺杂浓度大于该高电压N型阱的掺杂浓度。
11.根据权利要求10所述的方法，包括：
形成一大块P+区域于该大块P型阱中；
形成一高电压二极管P+区域于该高电压二极管P型阱中；及
形成一高电压二极管N+区域于该高电压N型阱中，且该高电压二极管N+区域与该高电压二极管P型阱分开，使该高电压二极管P型阱是配置于该高电压二极管N+区域与该高电压N型阱的该边缘之间。
12.根据权利要求11所述的方法，更包括：
形成一绝缘层于该基板上，该绝缘层包括多个开口，这些开口分别暴露该高电压二极管N+区域、该高电压二极管P+区域与该大块P+区域；
形成一金属层于该绝缘层上，该金属层包括多个分离部分，这些分离部分分别连接至该高电压二极管N+区域、该高电压二极管P+区域以及该大块P+区域。
13.根据权利要求12所述的方法，其中该绝缘层是一第一绝缘层，该金属层是一第一金属层，且该方法更包括：
形成一额外的绝缘层于该第一金属层上；及
形成一额外的金属层于该额外的绝缘层上。
14.根据权利要求10所述的方法，其中该N型阱是一第一N型阱，该方法更包括：
形成一第二N型阱于该第一N型阱的顶部上，该第一N型阱的掺杂浓度大于该第二N型阱的掺杂浓度。
15.根据权利要求11所述的方法，更包括：
形成一漂移区于该高电压二极管N+区域与该高电压二极管P型阱之间。
16.根据权利要求10所述的方法，其中该高电压二极管P型阱的深度大于该高电压N型阱的深度，且该方法更包括：
形成一N型内埋层，该N型内埋层垂直地覆盖且连接至该高电压二极管P型阱的底部。
17.根据权利要求10所述的方法，其中该高电压二极管P型阱的深度是小于该高电压N型阱的深度。
18.一种集成电路，包括：
一基板；
一高电压N型阱，配置于该基板中；
一大块P型阱，配置于该高电压N型阱外且围绕该高电压N型阱；
一高电压二极管，配置于该高电压N型阱内，该高电压二极管包括一高电压二极管P型阱，该高电压二极管P型阱是沿着该高电压N型阱的一边缘配置，且与该高电压N型阱的该边缘分开；以及
一N型阱，沿着该高电压N型阱的该边缘配置，且位于该高电压二极管P型阱与该高电压N型阱的该边缘之间；
其中该N型阱的掺杂浓度大于该高电压N型阱的掺杂浓度。
19.根据权利要求18所述的集成电路，其中该高电压二极管更包括：
一高电压二极管P+区域，配置于该高电压二极管P型阱中；
一高电压二极管N+区域，配置于该高电压N型阱中且与该高电压二极管P型阱分开。
20.根据权利要求18所述的集成电路，其中该基板包括一高电压区块及一低电压区块，该高电压区块配置于该高电压N型阱内，该低电压区块配置于该高电压N型阱外。
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