CN106169445B - 用以制造具有多层模制导电基板和结构半导体封装的方法 - Google Patents

用以制造具有多层模制导电基板和结构半导体封装的方法 Download PDF

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CN106169445B
CN106169445B CN201610342189.1A CN201610342189A CN106169445B CN 106169445 B CN106169445 B CN 106169445B CN 201610342189 A CN201610342189 A CN 201610342189A CN 106169445 B CN106169445 B CN 106169445B
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conductive
encapsulant
conductive pattern
pillar
pattern
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CN106169445A (zh
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班文贝
元秋亨
郑季洋
金本吉
金即俊
李钟炫
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Anrely Technology Singapore Holdings Pte Ltd
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Amkor Technology Inc
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Abstract

用以制造具有多层模制导电基板和结构的半导体封装的方法。在一个实施例中，一种用于制造一半导体封装的方法包括提供一多层模制导电结构。该多层模制导电结构包括：一第一导电结构，其设置在一载板的一表面上；和一第一囊封剂，其覆盖该第一导电结构的至少部分，而其它部分暴露于该第一囊封剂中。一第二导电结构设置在该第一囊封剂上，并且电气连接到该第一导电结构。一第二囊封剂覆盖该第二导电结构的一第一部分，而该第二导电结构的一第二部分暴露到外部，并且该第二导电结构的一第三部分暴露于设置在该第二囊封剂中的一接收空间中。该方法包括：将一半导体晶粒电气连接至该第二导电结构，并在一些实施例中，移除该载板。

Description

用以制造具有多层模制导电基板和结构半导体封装的方法
技术领域
本申请案主张在美国专利局于2016年4月19日所提交的美国专利申请案的优先权，其案号为15/133,081，发明名称为“用以制造具有多层模制导电基板和结构之半导体封装的方法”，以及在韩国知识产权局于2015年5月22日所提交的韩国专利申请案的优先权，其案号为10-2015-0071718，并且上述专利申请案所获取的所有权益是其根据35U.S.C.§119，本文以引用的方式将其内容完整并入。
本发明一般是关于电子电路，并且更特定而言是关于半导体封装及其结构，以及形成半导体封装的方法。
背景技术
根据近来对于电子装置的小型化和高性能的需求，已研究和开发了各种制程以用于提供高性能的半导体封装。提供高性能的半导体封装的之一种制程为增加一内存芯片的容量，也就是，达成高积体化的内存芯片。高积体化的内存芯片的达成可借由在一半导体晶粒的有限空间中尽可能地填充许多单元。
然而，高积体化的内存芯片需要高度复杂的技术，包括了像是需要达成精确、精细的线路宽度、和长时间的显影。替代性地，已经提出一种半导体晶粒的堆栈技术，以提供高容量的半导体模块。也已经提出了以一晶圆级来制造一封装的技术，在该晶圆上形成有复数个半导体晶粒。除了需要昂贵和复杂的制造技术之外，这些技术中的每一者都缺少在电路图案的重新设计上的灵活性。
因此，希望能具有可以解决先前所述以及其他问题的形成封装半导体装置的结构及方法。还希望这些结构和方法可以很容易地并入到制造流程，并具有成本效益。
发明内容
本发明的叙述包括，特别是以下特征，一种多层模制导电基板或多层模制导电结构包括至少两层的囊封或模制导电互连结构。在一些实施例中，一载板附接到该多层模制导电结构的一表面以作为一临时支撑结构。在其他实施例中，该载板可以被配置为一散热板或散热器结构。电子构件，例如半导体装置及/或被动组件，可以被附接到该多层模制导电结构，其包括凹部部分内的附接件。在该多层载板中的上层导电图案及/或连接结构可以在制造制程中重新设计，以允许弹性、节省时间、和成本效益的制造能力。
更特定而言，在一个实施例中，一种用于制造一半导体封装，其包括：提供一多层模制导电结构，其包括：一第一导电结构，其设置在一载板的一第一表面上；一第一囊封剂，其囊封该第一导电结构的至少部分，而该第一导电结构的其它部分暴露于该第一囊封剂中；一第二导电结构，其设置在该第一囊封剂上，并且电气耦合到该第一导电结构；以及一第二囊封剂，其囊封该第二导电结构的一第一部分，而该第二导电结构的一第二部分暴露于该第二囊封剂中的一接收空间。该方法包括：将一第一半导体晶粒电气连接到该第二导电结构在该接收空间中的第三部分。
在另一个实施例中，一种半导体封装包括一第一导电结构。一第一囊封剂囊封该第一导电结构的至少部分，而该第一导电结构的其它部分暴露于该第一囊封剂中。一第二导电结构设置在该第一囊封剂上，并且电气耦合到该第一导电结构。一第二囊封剂囊封该第二导电结构的一第一部分，而该第二导电结构的一第二部分暴露于该第二囊封剂中。一第一半导体晶粒电气耦合到该第二导电结构。
在进一步的实施例中，一种半导体封装包括一第一导电图案和一第一导电支柱，其电气连接到该第一导电图案。一第一囊封剂囊封该第一导电图案和该第一导电支柱。一第二导电图案电气连接到该第一导电支柱，其暴露于该第一囊封剂的外部。一第二导电支柱电气连接到该第二导电图案的一部分。一第二囊封剂囊封该第二导电图案的一第一部分和该第二导电支柱的一部分。一接收空间设置于该第二囊封剂中，以暴露该第二导电图案的至少一第二部分。一第一半导体晶粒放置在该接收空间，并电气连接到该第二导电图案的该第二部分。
附图说明
本说明书的上述和其它特征将参考随附的图式，借由范例性实施例进行细节描述，而变得更加明了，其中：
图1至图11是部分剖面图，其依序例示了根据本发明的一个实施例来制造半导体封装的方法；
图12是部分剖面图，其例示了根据本发明的另一个实施例的半导体封装；
图13是部分剖面图，其例示了根据本发明的又另一个实施例的半导体封装；
图14是部分剖面图，其例示了根据本发明的又另一个实施例的半导体封装；以及
图15是部分剖面图，其例示了根据本发明的又另一个实施例的半导体封装。
为了简化和清楚地说明，图中的组件不一定按比例绘制，并且在不同图式中，相同的组件符号表示相同的组件。此外，已知的步骤及组件的描述和细节予以省略以求描述的简化。本文所使用的用语「及/或」包括一个或更多相关所列的项目的任意组合和所有组合。此外，这里使用的用语的目的仅是用于描述特定实施例，并不旨在限制本揭示。本文中所使用的单数形式也意图包括复数形式，除非上下文另外明确指出。应进一步理解的是，用语「包括、及/或包含」，在本说明书中使用时，是用以指定所陈述的特征、数字、步骤、操作、组件、及/或构件的存在，而不是用以排除一个或更多其它特征、数字、步骤、操作、组件、构件、及/或上述组合的增加或存在。应理解的是，尽管用语「第一、第二…等」在本文中可用于描述各种部件、组件、区域、层及/或区块，但是这些构件、组件、区域、层、及/或区块不应受到这些用语的限制。这些用语仅用于将构件、组件、区域、层及/或区块与其他的构件、组件、区域、层及/或区块作出区分。因此，举例来说，一第一部件、一第一组件、一第一区域、一第一层、及/或下面讨论的一第一区块可以被称为一第二部件、一第二组件、一第二区域、一第二层、及/或一第二区块，而不脱离本揭示的教导。参考「一个实施例」或「一实施例」意味着与该实施例相关所描述的特定特征、结构、或特性被包括在本发明的至少一个实施例中。因此，「在一个实施例中」或「在一实施例中」的词语在本说明书全文所出现的不同场合不一定都指相同的实施例，但在某些情况下，其可能为真。此外，在一个或更多实施例中，特定特征、结构、或特性可以用任何合适的方式进行组合，其对于本领域具有通常知识的人士将是显而易见的。另外，用语「当…之时」指的是至少在开始的动作的持续时间的至少部分发生了某些动作。词语「大约」或「约」的使用实质上指的是，组件的量值预期将接近一状态值或位置。然而，如在本领域中所众所周知的是，总是会有些微的差异，使得量值或位置与所陈述的量值有所差异。除非另有说明，本文所使用的「上」或「上方」用语包括方位、位置、或关系，其中所指定的组件可直接或间接实体接触。应进一步理解的是，下文所例示和描述的这些实施例可以具有实施例、及/或可以在缺少本文所没有特定揭示的组件下所实行。
具体实施方式
参考图1至图11，一种用于根据第一实施例而制造半导体封装的方法、以及一种使用该方法来制造的半导体封装1000将进行描述。图1至图11例示了一种根据第一实施例而制造半导体封装的方法的部分剖面图。
首先，如图1所示，一第一导电图案110形成于一载板10的一第一表面11上。在此，包括该第一表面11的该载板10进一步包括对置于该第一表面11的第二表面12。在一个实施例中，该载板10所具有的厚度的范围从大约3微米到300微米。在一些实施例中，该载板10可以由金属、硅、玻璃、环氧树脂、或如本领域技术人士所知晓的其他材料中的一者或更多者来形成。至少该第一表面11已准备并已清洗，用于接收该第一导电图案110。
在一个实施例中，该第一导电图案110可以由导电材料制成，包括铜(Cu)、金(Au)、银(Ag)、铝(Al)或如本领域技术人士所知晓的其它材料。另外，该第一导电图案110可借由物理气相沉积(PVD)、化学气相沉积(CVD)、金属溅镀、金属蒸镀、电解或无电电镀、或如本领域技术人士所知晓的其它形成技术来形成。在一个实施例中，该第一导电图案110所具有的厚度的范围从大约3微米到50微米。在沉积之后，该导电材料可以借由物理蚀刻或化学蚀刻，或如本领域技术人士所知晓的其它技术来进行图案化。在其他实施例中，一屏蔽层(未图示)可以首先沉积在该第一主要表面(第一表面)11上，并且随后沉积该导电材料。在形成该导电图案后，该屏蔽层可移除或可不移除，取决于其应用。
接着，参考图2，电气连接到该第一导电图案110的一个或更多第一导电支柱120被形成。该第一导电支柱120被形成以延伸远离该第一导电图案110和该载板10的第一表面11，或是从该第一导电图案110和该载板10的第一表面11向外延伸。在一个实施例中，该第一导电支柱120较佳地以具有良好的导电、导热的材料来形成，如铜(Cu)、铜合金、或其类似物，但是该第一导电支柱120的形状和材料都没有受到本文所揭示内容的限制。在一个实施例中，该第一导电支柱120所具有的厚度的范围从大约30微米到300微米。此外，该第一导电支柱120可使用PVD、CVD、金属溅镀、金属蒸镀、电解、或无电电镀或如本领域技术人士所知晓的其它形成技术来形成。在一个实施例中，电解或无电电镀技术搭配使用一屏蔽层，该屏蔽层设置于该第一主要表面11上方，且具有一预选图案，以用于在希望的位置中形成该第一导电支柱120。在一个实施例中，该第一导电支柱120具有与该第一导电图案110不同的宽度。在一个实施例中，一第一导电结构121可包括该第一导电图案110和该第一导电支柱120、及/或额外的导电结构中的一者或更多者。
接着，参考图3，该载板10的第一表面11的顶部部分，亦即，该第一导电图案110和该第一导电支柱120的每一者的外表面借由一第一囊封剂130或第一模制囊封剂加以囊封。
在一个实施例中，该第一囊封剂130完全囊封并覆盖该第一导电图案110和该第一导电支柱120，以保护该第一导电图案110和该第一导电支柱120，使其不会受到像是外部冲击或氧化的损害。在一个实施例中，该第一囊封剂130被形成以具有比该第一导电支柱120更高的厚度。在其他实施例中，该第一囊封剂可形成以与该第一导电支柱120的远程齐平。在此，该第一囊封剂130可以是聚合物复合材料，例如像是用于透过模制制程而执行囊封的环氧模制化合物、用于透过一分配器而执行囊封的液体囊封构件、或其上述的类似物，但是本实施例的方面不限于此。
接着，参考图4，使用一移除制程以移除该第一囊封剂130的部分。在一个实施例中，使用一研磨制程以在该第一囊封剂130的一表面上移除一预定厚度的材料，使得该第一导电支柱120暴露于该第一囊封剂130的外部。在此，研磨可以使用像是一钻石研磨机或其等效物来执行，但本发明的方面不限于此。在其他实施例中，屏蔽和蚀刻技术，以及研磨技术或上述组合可以用于移除该第一囊封剂130的部分。在一个实施例中，图4的结构可称为一模制载板次组件100或第一模制载板100，其包括该载板10、该第一导电图案110、一个或更多的该第一导电支柱120、以及该第一囊封剂130。在大多数实施例中，该模制载板次组件100包括暴露于该第一囊封剂130的外部的一个或更多的第一导电支柱120，如大致上由图4所示。在一个实施例中，该模制载板次组件100可以被预先制造并在按照预期的设计修改而被实施在一第二导电图案140和一第二导电支柱150中，如下文所描述。按照本实施例，此提供了增强的设计灵活性，并节省制造成本和周期时间。
接着，参考图5，电气连接到该第一导电支柱120且暴露于该第一囊封剂130的外部上的第二导电图案140被形成。在此，如同本领域技术人士所知晓，该第二导电图案140可以由导电材料制成，包括铜(Cu)、金(Au)、银(Ag)、铝(Al)或其它材料。另外，该第二导电图案140可借由物理气相沉积(PVD)、化学气相沉积(CVD)、金属溅镀、金属蒸镀、电解或无电电镀、或如本领域技术人士所知晓的其它形成技术来形成。在一个实施例中，该第二导电图案140所具有的厚度的范围从大约3微米到50微米。选择用于该第二导电图案140上的导电材料与选择用于该第一导电图案110上的导电材料可以是相同的或不同的。
根据本实施方式，由于该第二导电图案140与该第一导电图案110可以具有不同的图案，例如，位置和形状方面，可根据一第一半导体晶粒、或将在后面描述的其他电气构件或电子装置而轻易地重新设计或修改电路图案。
接着，参考图6，电气连接到该第二导电图案140的一个或更多第二导电支柱150被形成。在此，该第二导电支柱150可被选择性地连接到该第二导电图案140的一部分。该第二导电支柱150被形成为从该第二导电图案140向上延伸而远离或向外延伸，并且较佳地以良好的导电、导热性的材料制成，如铜(Cu)、铜合金、或其类似物，但该第二导电支柱150的形状和材料不限于在本文所揭示的内容。在一个实施例中，该第二导电支柱150所具有的厚度的范围从大约30微米到300微米。此外，该第二导电支柱150可借由物理气相沉积(PVD)、化学气相沉积(CVD)、金属溅镀、金属蒸镀、电解或无电电镀、或如本领域技术人士所知晓的其它形成技术来形成。在一个实施例中，电解或无电电镀技术搭配使用一屏蔽层，该屏蔽层设置于该第一囊封剂130的表面上方，且具有一预选图案，以用于在希望的位置中形成该第二导电支柱150。在一个实施例中，该第二导电支柱150具有与该第二导电图案140不同的宽度，并且可以进一步具有与该第一导电支柱120不同的宽度和形状。在一个实施例中，一第二导电结构221可包括该第二导电图案140和该第二导电支柱150、及/或其它导电结构中的一个或更多个。
接着，参考图7，该第一囊封剂130的顶部部分，也就是，该第二导电图案140和该第二导电支柱150的每一者的外表面借由一第二囊封剂160加以囊封。在一个实施例中，该第二囊封剂160进一步包括一接收空间161，其被形成以防止该第二导电支柱150所没有连接到该第二导电图案140的剩余区域免于被囊装。该接收空间161可以使用网版屏蔽或其等效物来形成，但是本发明的方面不限于此。在其他实施例中，该接收空间161可以在该第二囊封剂160形成之后才形成。在其他实施例中，在该接收空间161内的导电图案140的侧壁部分可以被该第二囊封剂160或其它绝缘材料囊封或覆盖。在一个实施例中，该接收空间161被配置为具有大致上如图7所示的倾斜的侧壁，以便更佳地促进制造并避免在该第二囊封剂160的尖角。
该第二囊封剂160完全囊封并覆盖该第二导电图案140和该第二导电支柱150的一部分，以保护该第二导电图案140和该第二导电支柱150，使得其不会受到像是外部冲击或氧化的损害。在一个实施例中，该第二囊封剂160被形成以具有比该第二导电支柱150更高的厚度。或者，该第二囊封剂160可形成以与该第二导电支柱150的远程齐平。在一些实施例中，该第二囊封剂160可以是聚合物复合材料，例如像是用于透过模制制程而执行囊封的环氧模制化合物、用于透过一分配器而执行囊封的液体囊封构件、或其上述的类似物，但是本实施例的方面不限于此。该第二囊封剂160可以是与该第一囊封剂130相同的材料或不同的材料。根据本实施例，该第一囊封剂130和该第二囊封剂160是不同且分开的材料区域。
接着，参考图8，使用一移除制程移除该第二囊封剂160的部分。在一个实施例中，使用一研磨制程以在该第二囊封剂160的一表面上移除一预定厚度的材料，使得该第二导电支柱150暴露于该第二囊封剂160的外部。在一个实施例中，可以使用像是一钻石研磨机或其等效物来执行研磨，但本发明的方面不限于此。在其他实施例中，屏蔽和蚀刻技术，以及研磨技术或上述组合可以用于移除该第二囊封剂160的部分。在一替代性实施例中，可以在该第二囊封剂的部分已被移除之后，形成该接收空间161。在一个实施例中，图8的结构可称为多层模制导电结构201、多层模制导电基板201，模制载板结构201、或第二模制载板201，其包括该模制载板次组件100、该第二导电图案140，一个或更多第二导电支柱150、以及具有一个或更多接收空间161的第二囊封剂160。在大多数实施例中，该多层模制导电结构201包括暴露于该第二囊封剂160的外部的该一个或更多第二导电支柱150。在其他实施例中，多层模制导电结构202或多层模制导电基板202包括该第一导电图案110、该第一囊封剂130、该第二导电图案140、一个或更多第二导电支柱150，以及没有载板10的该第二囊封剂160。
接着，参考图9一第一半导体模块200被置放在该接收空间161，以予以电气连接到该第二导电图案140的剩余部分，并且该第一半导体模块200未被该第二囊封剂160囊封。在一些实施例中，该第一半导体模块200包括一第一半导体晶粒210、一第一接合垫220、一第一导电凸块230、和一第一底层填料240。该第一半导体晶粒210具有一底表面，且电气连接至一主动层(未图示)的该第一接合垫220暴露于该底表面。在一个实施例中，该第一接合垫220包括一导电材料，例如铝、铜、锡、镍、金银、或其它合适的导电材料的一层或更多层。
该第一导电凸块230以电气和实体的方式连接该第一接合垫220和透过一回流制程以连接该第二导电图案140，并且该第一导电凸块230由一个或更多导电材料制成，例如，铅/锡(Pb/Sn)、或无引线锡和类似物、或其它合适的导电材料。在一个实施例中，该第一导电凸块230可以是一焊料凸块、铜支柱、焊料球、或球型凸块。在一个实施例中，该第一底层填料240填充或配置于该第一囊封剂130的一个表面与该第一半导体晶粒210的底表面之间，随后进行固化制程。
根据本实施例，该第一底层填料240保护一凸块接合部分不会受到外部因素的影响，像是在制造半导体封装的过程中所产生的机械冲击或腐蚀。在此，该第一底层填料240可以是聚合物材料，像是环氧树脂、热塑性材料、热固性材料、聚酰亚胺、聚氨酯、聚合物材料、填充的环氧树脂、填充的热塑性材料、填充的热固性材料、填充的聚酰亚胺、填充的聚氨酯、填充的聚合物材料中、助熔的底层填料、或如本领域技术人士所知晓的其他材料中的一者或更多者。在一个实施例中，该第一半导体晶粒210具有主要表面(例如，与第一导电凸块230对置的表面)，该主要表面实质上位于(例如，水平面)与该第二囊封剂160的外表面相同的平面上。在其它实施例中，该第一半导体晶粒210的主要表面位于与该第二囊封剂160的外表面不同的平面(例如，水平面)上。
接着，参考图10和图11，根据本发明另一实施例，该半导体封装1000借由附接一个或更多导电凸块20以电气连接到暴露于该第二囊封剂160的外部的(多个)第二导电支柱150而制成。在一个实施例中，该导电凸块20可以由金属材料制成，例如铅/锡(Pb/Sn)、或无引线锡和类似物、或如本领域技术人士所知晓的其它合适的导电材料。在一个实施例中，该导电凸块20可以是一焊料凸块、铜支柱、焊料球、或球型凸块。根据本实施例，该半导体晶粒210的外部主要表面与该导电凸块20的远程或表面是位于不同的平面，以便在该半导体封装1000被附接于此时，提供该第一半导体晶粒210和下一层级(level)的组件(如，一印刷电路板)之间的间隙。在一个实施例中，该载板10被分离，以提供如图11所示的半导体封装1000，其第一导电图案110暴露于外部，用于进一步互连的功能或散热，在下文中会描述进一步的实施例。
图12是根据另一实施例而例示一半导体封装2000的部分剖面图。在一个实施例中，一散热器13或一散热板13附接到该第一囊封剂130的顶部部分。在一个实施例中，该散热板13也可以分开地附接到该第一囊封剂130。在一个较佳的实施例中，该载板10被配置以使用插入于该载板10和该第一囊封剂层130之间的绝缘层14作为散热板13(例如，包括一导热材料)。在一些实施例中，该散热板13较佳地以具有高热导率和低热膨胀系数的金属来形成。然而，由于该散热板13直接连接到暴露的第一导电图案110，一绝缘层14插入于该散热板13和该第一导电图案110之间，以防止在该散热板13和该第一导电图案110之间发生电气短路。在一些实施例中，该散热板13可以由具有高热导率的材料来形成，例如硅、玻璃或、环氧树脂，并且一金属及/或陶瓷粉末形成于该散热板13内。
图13是根据进一步的实施例而例示一半导体封装3000的部分剖面图。在一个实施例中，在该载板10与该第一囊封剂130分离后，一第二半导体模块300被放置以电气连接到在该第一囊封剂130的顶部部分处的第一导电图案110，并且该第二半导体模块300的外表面是借由在该第一囊封剂130的顶部部分处的第三囊封剂30来囊封的。
在一个实施例中，该第二半导体模块300包括一第二半导体晶粒310、一第二接合垫320、一第二导电凸块330、和一第二底层填料(未图示)。该第二半导体晶粒310具有一底表面，而电气连接到主动层(未图示)的第二接合垫320暴露于该底表面。在一个实施例中，该第二接合垫320包括一导电材料，例如铝、铜、锡、镍、金银、或其它合适的导电材料的一层或更多层。
该第二导电凸块330以电气和实体的方式连接该第二接合垫320和透过一回流制程以连接该第一导电图案110，并且该第二导电凸块330由一个或更多导电材料制成，例如，铅/锡(Pb/Sn)、或无引线锡和类似物、或其它合适的导电材料。在一个实施例中，该第二导电凸块330可以是一焊料凸块、铜支柱、焊料球、或球型凸块。该第三囊封剂30可以用和先前所述的第一囊封剂130的相同的材料来形成。在其他实施例中，可以形成该第三囊封剂30，以暴露该第二半导体模块300或该第二半导体晶粒310到外部，以在使用或不用散热板的情况下提供改良的热散失。
图14是根据又进一步的实施例而例示一半导体封装4000的部分剖面图。在一个实施例中，在该载板10与该第一囊封剂130分离后，一被动组件400被放置以电气连接到在该第一囊封剂130的顶部部分处的第一导电图案110，并且被附接而能够交换信号。此外，该被动组件400的外表面是借由在该第一囊封剂130的顶部部分处的第三囊封剂30来囊封的。在一个实施例中，该被动组件400可形成为一电阻器、一电感器、或一电容器。该第三囊封剂30可以用和先前所述的第一囊封剂130的相同的材料来形成。
图15是根据另一个实施例而例示一半导体封装5000的部分剖面图。在一个实施例中，在该载板10与该第一囊封剂130分离后，该第二半导体模块300和该被动组件400被放置以电气连接到在该第一囊封剂130的顶部部分处的第一导电图案110，并且被附接而能够交换信号。此外，该第二半导体模块300和该被动组件400的外表面是借由在该第一囊封剂130的顶部部分处的第三囊封剂30来囊封的。在一个实施例中，该第二半导体模块300和该被动组件400如前面相关于图13和图14所描述。该第三囊封剂30可以用和先前所述的第一囊封剂130的相同的材料来形成。在替代实施例中，可以形成该第三囊封剂30，以暴露该第二半导体晶粒310的表面，如前所述。
从上述的一切可知，根据另一个实施例，本领域的技术人士能确定的是，一种用于制造半导体封装的方法，其包括形成一第一导电图案于一载板的一第一表面上；形成一第一导电支柱，其被电气连接到该第一导电图案；首先使用一第一囊封剂来囊封该第一导电图案和该第一导电支柱；形成一第二导电图案，其被电气连接到该第一导电支柱，该第一导电支柱暴露于该第一囊封剂的外部；形成一第二导电支柱，其被电气连接到该第二导电图案的一部分；其次使用一第二囊封剂来囊封该第二导电图案和该第二导电支柱的部分，并且一接收空间，该第二导电图案的剩余部分被暴露于该接收空间；以及放置一第一半导体晶粒于该接收空间而予以电气连接到暴露于该第二囊封剂的外部的该第二导电图案。
从上述的一切可知，根据进一步的实施例，本领域的技术人士能确定的是，一种半导体封装，其包括：一第一导电图案；一第一导电支柱，其被电气连接到该第一导电图案；一第一囊封剂，其囊封该第一导电图案和该第一导电支柱；一第二导电图案，其被电气连接到暴露于该第一囊封剂的外部的该第一导电支柱；一第二导电支柱，其被电气连接到该第二导电图案的部分；一第二囊封剂，其形成一接收空间，该第二导电图案的剩余部分被暴露于该接收空间，该第二囊封剂囊封该第二导电图案和该第二导电支柱的一部分；以及一第一半导体晶粒，其被电气连接到暴露于该第二囊封剂的外部的该第二导电图案，并且被放置于该接收空间中。
从上述的一切可知，根据本文所描述的方法的进一步的实施例，本领域的技术人士能确定的是，电气耦合该第一半导体晶粒包括：直接将该第一半导体晶粒连接到第二导电结构在该接收空间中的第三部分。在又进一步的实施例中，电气耦合该第一半导体晶粒可包括电气耦合具有一主要表面的该第一半导体晶粒，该主要表面实质上位于与该第二囊封剂的一外表面相同的一平面上。在另一个实施例中，提供该多层模制导电结构可包括：提供包含金属、硅、玻璃、或环氧树脂的一者或更多者的载板。在进一步的实施例中，提供该多层模制导电结构可包括：提供包括一金属且具有一绝缘层的该载板，该绝缘层设置在该载板的该第一表面和该第一导电结构之间。
从上述的一切可知，根据本文所描述的结构的进一步的实施例，本领域的技术人士能确定的是，该半导体封装可进一步包括导电凸块，其附接到该第二导电结构的第二部分。
从上述的一切可知，根据本文所描述的结构的进一步的实施例，本领域的技术人士能确定的是，一散热板，其可以被配置在该第一囊封剂的对置于该第一半导体晶粒的顶表面附近。
鉴于上述所述，显而易见的是，已揭示一种使用具有弹性的设计能力的多层模制导电结构来制造一半导体封装的方法及结构。其包括，特别是，一第一导电结构和一第二导电结构，该第一导电结构被一第一模制囊封剂囊封，且该第二导电结构设置在该第一模制囊封剂上并电气连接到该第一导电结构。该第二导电结构有助于对该封装基板互连结构的弹性设计变化或重新设计。该第二模制囊封剂囊封该第二导电结构的至少部分，并且一电子装置电气连接到该第二导电图案。在一些实施例中，一个或更多额外的电子装置可电气连接到该第一导电图案。在其他实施方式中，一散热板可以被附接到该半导体封装。
虽然已经特定显示本发明的范例性实施例并进行描述，本领域的技术人士可以了解的是，可对于其形式和细节上进行各种变化而不脱离本发明的精神和范畴的前提下，本发明的精神和范畴如由随附权利要求书所界定。
如权利要求书所反映，本发明的特色可在于比单一个前面所揭示实施例的所有特征还少。因此，以下所表述的权利要求书在此明确地并入附图的详细说明，每一项权利要求本身作为本发明的一个单独实施例。此外，虽然本文所描述的一些实施例包括在其他实施例中的一些特征但不是其它实施例的特征，不同实施例的特征的组合希望落在本发明的范畴内，希望形成本领域的技术人士所能理解地不同的实施例。

Claims (8)

1.一种用于制造半导体封装的方法，其包括：
提供多层模制导电结构，其包括：
第一导电结构，其包括设置在载板的第一表面上的第一导电图案和附接至该第一导电图案的第一导电支柱，其中在该第一导电支柱附接至该第一导电图案处，该第一导电图案比该第一导电支柱宽，以及其中该第一导电图案界定该半导体封装的最上面图案化导电结构；
第一囊封剂，其囊封该第一导电结构，其中：
该第一导电图案具有暴露于该载板的该第一表面附近的该第一囊封剂的第一表面中的外表面；
该第一导电图案具有嵌入于该第一囊封剂内的侧表面；
该第一导电支柱暴露于该第一囊封剂的第二表面中，该第二表面与该第一囊封剂的该第一表面相对；以及
该第一导电图案的该外表面与该第一囊封剂的该第一表面齐平；
第二导电结构，其包括附接至该第一导电结构的第二导电图案和附接至该第二导电图案的第一部分的第二导电支柱；以及
第二囊封剂，其囊封该第二导电结构，其中：
该第二导图案具有暴露于邻接该第一囊封剂的该第二表面的该第二囊封剂的第一表面中的外表面；
该第二导电图案的第二部分暴露于接收空间中，其中该第二部分在该接收空间中没有与任何第一导电支柱和第二导电支柱直接实体接触；以及
该第二导电支柱暴露于与该第二囊封剂的该第一表面相对的该第二囊封剂的第二表面中；
将第一半导体晶粒电气耦合到该第二导电图案在该接收空间中的该第二部分；
移除该载板；
提供第二半导体晶粒和被动组件，其被放置以电气耦合至该第一囊封剂的该第一表面附近的该第一导电图案，其中该第一导电支柱横向插入于该被动组件和该第一半导体晶粒之间，使得该被动组件不与该第一导电支柱重叠；以及
提供第三囊封剂，其囊封该第二半导体晶粒和该被动组件，其中该被动组件和该第一半导体晶粒不横向重叠，以及其中该第二半导体晶粒和该第一半导体晶粒不完全横向重叠。
2.如权利要求1所述的方法，其中：
提供该多层模制导电结构包括：
提供具有嵌入于该第二囊封剂中的侧表面的该第二导电图案；以及
提供与该第二囊封剂齐平的该第二导电图案的该外表面。
3.如权利要求1所述的方法，其中提供该多层模制导电结构包括：
提供具有该第一表面的该载板；
形成该第一导电图案在该载板的该第一表面上；
形成该第一导电支柱以与该第一导电图案电气耦合；
之后，形成该第一囊封剂至该第一导电图案和该第一导电支柱上；
移除该第一囊封剂的部分以在该第一囊封剂的该第二表面暴露该第一导电支柱；
形成该第二导电图案以与该第一导电支柱电气耦合；
形成该第二导电支柱以与该第二导电图案的第一部分电气耦合；以及
之后，形成该第二囊封剂至该第二导电图案和该第二导电支柱上；
移除该第二囊封剂的第一部分以形成暴露该第二导电图案的该第二部分的该接收空间；以及
在移除该第二囊封剂的该第一部分之后，移除该第二囊封剂的第二部分以在该第二囊封剂的该第二部分中暴露该第二导电支柱。
4.一种半导体封装，其包括：
第一导电结构，其包括第一导电图案和附接至该第一导电图案的第一导电支柱，其中在该第一导电支柱附接至该第一导电图案处，该第一导电图案比该第一导电支柱宽，以及其中该第一导电图案界定该半导体封装的最上面图案化导电结构；
第一囊封剂，其囊封该第一导电结构，其中：
该第一导电图案具有暴露于该第一囊封剂的第一表面中的外表面；
该第一导电图案具有嵌入于该第一囊封剂内的侧表面；
该第一导电支柱暴露于该第一囊封剂的第二表面中，该第二表面与该第一囊封剂的该第一表面相对；以及
该第一导电图案的该外表面与该第一囊封剂的该第一表面齐平；
第二导电结构，其包括电气耦合至该第一导电结构的第二导电图案和附接至该第二导电图案的第一部分的第二导电支柱，其中在该第二导电支柱附接至该第二导电图案的该第一部分处，该第二导电图案比该第二导电支柱宽；
第二囊封剂，其囊封该第二导电结构，其中：
该第二导电图案具有暴露于该第二囊封剂的第一表面中的外表面；
该第二导电图案的第二部分没有在该第二囊封剂和在该第二导电支柱提供；以及
该第二导电支柱暴露于与该第二囊封剂的该第一表面相对的该第二囊封剂的第二表面中；
第一半导体晶粒，其电气耦合到该第二导电图案的该第二部分；
接收空间，其设置在该第二囊封剂中，其中该接收空间暴露该第二导电图案的该第二部分，其中：
该第二导电图案的该第二部分在该接收空间中没有与任何第一导电支柱和第二导电支柱直接实体接触；
被动组件，其被放置以电气耦合至该第一囊封剂的该第一表面附近的该第一导电图案，其中：
该第一导电支柱和该第二导电支柱横向插入于该被动组件和该第一半导体晶粒之间，使得该被动组件不与该第一导电支柱重叠以及不与该第二导电支柱重叠；以及
该第一导电支柱和该第二导电支柱电气连接；
第三囊封剂，其囊封该被动组件，其中该被动组件和该第一半导体晶粒不重叠；以及
第二半导体晶粒，其附接至该第一导电图案的该外表面以使得该第二半导体晶粒邻近该第一囊封剂的该第一表面以及该第一半导体晶粒邻近该第一囊封剂的该第二表面，以及其中该第二半导体晶粒和该第一半导体晶粒仅部分重叠，以及其中该第三囊封剂囊封该第二半导体晶粒。
5.如权利要求4所述的半导体封装，其进一步包括：
第一底层填料，其设置在该第一囊封剂的该第二表面和该第一半导体晶粒的表面之间，其中该第一底层填料实体接触该第二导电图案的该第二部分的侧表面。
6.一种半导体封装，其包括：
第一导电结构，其包括第一导电图案和附接至该第一导电图案的第一导电支柱，其中在该第一导电支柱附接至该第一导电图案处，该第一导电图案比该第一导电支柱宽，以及其中该第一导电图案界定该半导体封装的最上面图案化导电结构；
第一囊封剂，其囊封该第一导电结构，其中：
该第一导电图案具有暴露于该第一囊封剂的第一表面中的外表面；
该第一导电图案具有嵌入于该第一囊封剂内的侧表面；
该第一导电支柱暴露于该第一囊封剂的第二表面中，该第二表面与该第一囊封剂的该第一表面相对；以及
该第一导电图案的该外表面与该第一囊封剂的该第一表面齐平；
第二导电结构，其包括电气耦合至该第一导电结构的第二导电图案和附接至该第二导电图案的第一部分的第二导电支柱，其中在该第二导电支柱附接至该第二导电图案的该第一部分处，该第二导电图案比该第二导电支柱宽；
第二囊封剂，其囊封该第二导电结构，其中：
该第二导电图案具有暴露于该第二囊封剂的第一表面中的外表面；
该第二导电图案的第二部分没有在该第二囊封剂和在该第二导电支柱提供；以及
该第二导电支柱暴露于与该第二囊封剂的该第一表面相对的该第二囊封剂的第二表面中；
第一半导体晶粒，其电气耦合到该第二导电图案的该第二部分；
接收空间，其设置在该第二囊封剂中，其中该接收空间暴露该第二导电图案的该第二部分，其中：
该第二导电图案的该第二部分在该接收空间中没有与任何第一导电支柱和第二导电支柱直接实体接触；
该第二囊封剂的侧壁表面界定该接收空间；
该侧壁表面是倾斜的；
该第一半导体晶粒直接连接至在该接收空间中的该第二导电图案的该第二部分；
该第二导电图案具有嵌入该第二囊封剂中的侧表面；以及
该第二导电图案的该外表面与该第二囊封剂齐平。
7.一种半导体封装，其包括：
第一导电图案；
第一导电支柱，其连接到该第一导电图案，其中在该第一导电支柱连接至该第一导电图案处，该第一导电图案比该第一导电支柱宽，以及其中该第一导电图案界定该半导体封装的最上面图案化导电结构；
第一囊封剂，其囊封该第一导电图案和该第一导电支柱，其中：
该第一导电图案具有暴露于该第一囊封剂的第一表面中的外表面；以及
该第一导电支柱暴露于该第一囊封剂的第二表面中，该第二表面与该第一囊封剂的该第一表面相对；
第二导电图案，其电气连接到该第一导电支柱，其中该第一导电支柱暴露于该第一囊封剂的该第二表面中；
第二导电支柱，其连接到该第二导电图案的第一部分；
第二囊封剂，其囊封该第二导电图案的第一部分和该第二导电支柱的一部分，其中：
该第二导电图案具有暴露于邻接该第一囊封剂的该第二表面的该第二囊封剂的第一表面中的外表面；以及
该第二导电支柱暴露于与该第二囊封剂的该第一表面相对的该第二囊封剂的第二表面中；
接收空间，其设置于该第二囊封剂中，以暴露该第二导电图案的至少第二部分；
其中该第二部分在该接收空间中没有与任何第一导电支柱和第二导电支柱直接实体接触；
第一半导体晶粒，其放置在该接收空间，并电气连接到该第二导电图案的该第二部分；
第二半导体晶粒和被动组件，其耦合至该第一囊封剂的该第一表面附近的该第一导电图案，其中该第一导电支柱横向插入于该被动组件和该第一半导体晶粒之间，以使得该被动组件不与该第一导电支柱重叠；以及
第三囊封剂，其囊封该第二半导体晶粒和该被动组件，其中该被动组件和该第一半导体晶粒不重叠，以及其中该第二半导体晶粒和该第一半导体晶粒仅部分重叠。
8.如权利要求7所述的半导体封装，其中：
该第一半导体晶粒直接连接到在该接收空间中的该第二导电图案；
该半导体封装进一步包括至少一导电凸块，其耦合到该第二导电支柱暴露于该第二囊封剂的外部的一部分；
该半导体封装进一步包括第一底层填料，其设置在该第一囊封剂的该第二表面和该第一半导体晶粒的表面之间，其中该第一底层填料实体接触在该接收空间中的该第二导电图案的该第二部分的侧表面；
该第一导电图案具有嵌入该第一囊封剂内的侧表面；
该第一导电图案的该外表面与该第一囊封剂齐平；
在该第二导电支柱连接至该第二导电图案的该第一部分处，该第二导电图案比该第二导电支柱宽；
该第二导电图案具有嵌入该第二囊封剂内的侧表面；以及
该第二导电图案的该外表面与该第二囊封剂齐平。
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