CN105762146A - 用于形成与量子阱晶体管的接触的技术 - Google Patents
用于形成与量子阱晶体管的接触的技术 Download PDFInfo
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- CN105762146A CN105762146A CN201610227774.7A CN201610227774A CN105762146A CN 105762146 A CN105762146 A CN 105762146A CN 201610227774 A CN201610227774 A CN 201610227774A CN 105762146 A CN105762146 A CN 105762146A
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Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
- H01L29/7784—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
公开了用于向在半导体异质结构中形成的器件提供低电阻自对准接触的技术。例如,可以采用所述技术形成与在III?V族和SiGe/Ge材料系中制造的量子阱晶体管的栅极、源极区和漏极区的接触。与在源极/漏极接触和栅极之间导致了相对较大的空间的常规接触工艺流程不同,由文中描述的技术提供的作为产物的源极和漏极接触是自对准的,因为每一接触均与栅极电极对准,并通过间隔体材料与之隔离。
Description
本申请是申请日为2010年12月2日、发明名称为“用于形成与量子阱晶体管的接触的技术”的专利申请201080058274.6的分案申请。
背景技术
在通常采用III-V族或者硅-锗/锗(SiGe/Ge)材料系的外延生长半导体异质结构中形成的量子阱晶体管由于具有低有效质量因而在晶体管沟道中提供了格外高的载流子迁移率,此外由于δ掺杂的原因还提供了降低的杂质散射。此外,这些器件还提供了格外高的驱动电流性能。尽管这样的器件能够显示出高沟道迁移率,但是形成与沟道的具有低接入电阻的源极/漏极接触也是相当困难的,尤其是在SiGe/Ge和III-V族材料系当中。
附图说明
图1示出了根据本发明的一个实施例的能够为其形成低电阻自对准接触的示范性量子阱生长结构。
图2示出了根据本发明的一个实施例的图1的量子阱生长结构上的硬掩模的沉积和构图。
图3示出了根据本发明的一个实施例的图2的量子阱生长结构中的隔离台面的形成。
图4示出了根据本发明的一个实施例的图3的量子阱生长结构的台面上的源极/漏极金属的沉积。
图5示出了根据本发明的一个实施例的图4的量子阱生长结构的源极/漏极金属上的硬掩模的沉积和构图。
图6示出了根据本发明的一个实施例的图5所示的量子阱生长结构中的栅极沟槽的形成。
图7示出了根据本发明的一个实施例的图6所示的量子阱生长结构的栅极沟槽中的间隔体的形成。
图8示出了根据本发明的一个实施例的图7所示的量子阱生长结构的栅极沟槽中的栅极金属的沉积。
图9示出了根据本发明的一个实施例的用于形成量子阱结构的低电阻自对准接触的方法。
具体实施方式
公开了用于向在半导体异质结构中形成的器件提供低电阻自对准接触的技术。例如,可以采用所述技术形成与在III-V族和SiGe/Ge材料系中制造的量子阱晶体管的源极区和漏极区的接触。与在接触和栅极之间导致了相对较大的开放空间的常规接触工艺流程不同,由文中描述的技术提供的作为产物的源极和漏极接触是自对准的,因为每一接触均与栅极电极对准。
一般概述
如前所述,形成与量子阱晶体管器件的沟道的具有低接入电阻的源极/漏极接触是相当困难的,涉及大量的不可忽视的问题。
简言之,半导体工业中采用的常规自对准接触方案在III-V族以及SiGe/Ge量子阱器件中效果很差。例如,植入的源极/漏极区形成了不良接触,从而导致了低载流子激活,并且再生长源极/漏极方案还受到低激活和结质量的影响。量子阱器件通常采用掺杂帽盖层,其有助于改善这一接触电阻。然而,采用这一帽盖层的常规接触流程不是自对准的。因而,极大降低了布局密度。此外,诸如p沟道金属氧化物半导体(PMOS)铟锑(InSb)器件或Ge量子阱器件的具有较低迁移率的器件在所述帽盖层中仍然具有足以引起源极/漏极电阻(有时将其称为外部电阻或Rext,其大体是指器件中所有小于沟道电阻的电阻值的和)显著劣化的电阻率。
可以采用文中提供的技术为量子阱器件形成自对准接触,所述器件包括采用III-V族和SiGe/Ge材料系实现的器件。可以采用任何数量的常规或惯常工艺流程制造量子阱结构本身,并且可以根据需要构造量子阱结构本身,使之适应给定应用的具体情况。例如,所述量子阱结构可以是具有n+掺杂帽盖层的常规铟镓砷(InGaAs)N型量子阱结构。或者,所述量子阱结构可以是常规铟锑(InSb)p型量子阱结构。根据本公开,显然存在很多种其他适当的量子阱结构类型和构造,并非旨在使所要求保护的本发明受限于任何特定的一个或一组。
因而,假定给出了预期的量子阱结构,那么可以根据本发明的实施例形成栅极和源极/漏极电极。因而,根据一个范例实施例,自对准接触的形成可以大体包括在形成栅极和源极/漏极电极之前生长下层量子阱结构(或其任何部分)。一个替代实施例假定预先形成了量子阱结构。
在任何情况下,一旦提供了先于电极的形成的量子阱结构,那么所述方法的这一示范性实施例包括执行台面隔离,其中,所述结构的有源区域受到掩模保护,将未受掩模保护的材料蚀刻掉,由此有效地形成台面。之后,向台面周围的蚀刻区域内沉积诸如二氧化硅(SiO2)的电介质材料,以提供电绝缘。所述示范性方法还包括在有源晶体管器件之上沉积源极/漏极金属并对其构图,以形成扩散层。例如,所述源极/漏极金属可以是镍(Ni)或其他典型接触金属,但是在其它情况下,例如,在对接触扩散层中的空位的容许程度降低的情况下,所述源极/漏极金属可以是(例如)钛(Ti)或其他难熔金属。所述示范性方法还包括进行构图和蚀刻,以形成用于栅极电极的沟槽。一般而言,所述蚀刻可能涉及湿法和/或干法蚀刻,而且可以是具有目标性的,从而在量子阱界面附近停止。之后,沿一个或多个栅极沟槽壁(在文中将其统称为栅极沟槽侧面,不管其是包括多边形沟槽中的若干不同侧面,还是包括圆形构成中的一个连续侧面)沉积诸如氧化物或氮化物的间隔体材料,并将其蚀刻成预期形成和厚度。在一个范例实施例中,还可以向栅极沟槽的栅极沟槽基底沉积任选的高k栅极电介质,从而提供进一步的隔离。一旦形成了间隔体和任选的高k电介质,就可以沉积诸如镍、铝(Al)、钛或钛镍(TiN)的栅极电极金属了。根据本发明的一个实施例,所产生的形成产物包括与晶体管栅极电极自对准的低电阻源极和漏极接触,其中,源极/漏极接触与栅极电极之间的唯一间隔被栅极沟槽侧面上间隔体材料占据。
注意,所述方法可以包括其他处理,例如,平面化、清洁以及其他出于简化的目的没有提及的典型功能。根据本公开显然存在很多种工艺变化,这些变化利用毯式金属化和栅极沟槽间隔体有助于低电阻漏极和源极接触的自对准。还要认识到,所述方法显著改善了外部寄生电阻和布局密度以及工艺成品率。
量子阱结构
图1示出了根据本发明的一个实施例的能够为其形成低电阻自对准接触的示范性量子阱生长结构。例如,所述量子阱生长结构可以是(例如)具有n+掺杂帽盖层的常规InGaAs n型量子阱结构。然而,如前所述,注意根据本公开显然可以采用任何数量的量子阱生长结构,例如,任何数量的n沟道金属氧化物半导体(NMOS)器件或PMOS器件实现根据本发明的实施例形成的低电阻自对准接触。并非旨在使所要求保护的本发明限于任何具体的量子阱生长构造。
从图1的截面图可以看出,所述量子阱生长结构包括衬底,在衬底上形成成核层、缓冲层和梯度缓冲层。所述结构还包括底部势垒层,在所述底部势垒层上形成量子阱层,在所述量子阱层上形成间隔体层,在所述间隔体层上提供掺杂层,在所述掺杂层上提供上部势垒层。在上部势垒层上提供蚀刻停止层,在蚀刻停止层上提供接触层。接着将讨论这些作为例子的层中的每者。其他实施例可以包括更少的层(例如,更少的缓冲层和/或没有蚀刻停止层)或者更多的层(例如,处于量子阱层之下的额外的间隔体层和/或掺杂层和/或处于势垒层的顶部的避免氧化的帽盖层),或者可以包括不同的层(例如,采用不同的半导体材料、配方和/掺杂剂形成的)。可以采用既定的半导体工艺(例如,金属有机化学气相沉积、分子束外延、光刻或其他这样的适当工艺)以任何适当的层厚度以及其他预期层参数实现所述层,并且所述层形成梯度(例如以线性或阶梯的形式),以改善由晶格相异的材料构成的相邻层之间的晶格常数匹配。一般而言,所述结构的具体层和尺寸将取决于预期的器件性能、制造能力以及所采用的半导体材料等因素。例如,所提供的具体层材料和特征只是出于举例的目的,而不是旨在限制所要求保护的本发明,可以结合任何数量的层材料和特征利用所要求保护的本发明。
可以像通常所做那样实现衬底,而且这里可以采用任何数量的适当衬底类型和材料(例如,p型,n型,中性型、硅、镓砷、硅锗、高电阻率或低电阻率、裁切或非裁切、绝缘体上硅等)。在一个范例实施例中,所述衬底为高电阻率n型或p型偏离取向硅衬底。所述衬底可以具有通过从结晶块上切下所述衬底而制备的邻位面,其中,以(例如)处于2°和8°之间的角度切下衬底(例如,4°裁切硅)。可以采用这样的裁切衬底来提供器件隔离,所述衬底还可以减少反相边界内的反相晶畴。然而,注意,在其他实施例中所述衬底未必具有这样的具体特征,可以在各种衬底上实现量子阱生长结构。
在衬底上形成成核层和底部缓冲层,可以像通常所做的那样实现所述层。在一个具体范例实施例中,所述成核层和底部缓冲层由镓砷(GaAs)构成,并且具有大约0.5到2.μm的总厚度(大约25nm到50nm厚的成核层以及大约0.3μm到1μm厚的底部缓冲层)。已知,可以采用成核层和底部缓冲层填充具有由(例如)诸如GaAs材料的III-V族材料构成的双原子层的最低衬底平台(terrace)。可以采用成核层建立无反相晶畴的实际上的极性衬底,可以采用底部缓冲层提供位错过滤缓冲,其能够为量子阱结构提供压缩应变和/或控制衬底和底部势垒层之间的晶格失配。注意,可以在没有成核层和/或底部缓冲层的情况下实现其他能够从本发明的实施例受益的量子阱结构。
在底部缓冲层上形成梯度缓冲层,也可以像通常所做的那样实现所述梯度缓冲层。在一个具体示范性实施例中,采用铟铝砷(InxAl1-xAs)实现所述梯度缓冲层,其中,x处于零到0.52的范围,所述梯度缓冲层具有大约0.7到1.1μm的厚度。已知,通过形成梯度缓冲层,位错可以在其内的相对偏斜的面内滑移,从而有效地控制衬底和底部势垒层之间晶格失配。然而,注意,可以在不采用缓冲层的情况下实现其他实施例,尤其是采用具有类似的晶格常数的材料实现衬底和下部势垒层(例如,诸如InP的高铟含量的衬底和InAlAs势垒层)的那些实施例。显然,可以在所述量子阱结构或叠层的其他位置采用这样的梯度层。
在这一示范性实施例中,在梯度缓冲层上形成底部势垒层,也可以像通常所做的那样实现所述底部势垒层。在一个具体示范性实施例中,采用InAlAs实现底部势垒层(例如,In.52Al.48As或者其他适当的势垒层配方),所述底部势垒层具有处于4nm到120nm的范围内的厚度(例如,100nm+/-20nm)。一般而言,形成所述底部势垒层的材料的能带隙高于形成覆盖量子阱层的材料的能带隙,并且所述底部势垒层所具有的厚度足以提供针对晶体管沟道中的电荷载流子的势垒。可以认识到,底部势垒层的实际构成和厚度将取决于诸如衬底和量子阱层材料的因素。根据本公开将认识到,在这里可以采用很多种这样的势垒材料和构造。
也可以像通常所做那样实现所述量子阱层。在一个具体示范性实施例中,量子阱层的实现采用了形成于铝砷(AlAs)沟道上的铟镓砷(In.7Ga.3As)沟道,所述铝砷(AlAs)沟道形成于n++In.53Ga.47As沟道上,所述n++In.53Ga.47As沟道形成于底部势垒层上,所述沟道分别具有大约13nm、3nm和100nm的厚度(例如,+/-20%)。将认识到这里可以采用各种其他量子阱层构造。一般而言,形成量子阱的材料的能带隙小于下部势垒层的能带隙,所述量子阱可以是掺杂的或者非掺杂的,其厚度足以为给定的应用,例如,为存储单元或逻辑电路的晶体管提供足够的沟道电导。此外,注意可以根据预期的性能材料任何数量的沟道构造。所述量子阱层可能因底部势垒层、上部势垒层或两者而产生应变。
在量子阱层上形成间隔体层,可以像通常所做的那样实现所述间隔体层。在一个具体的示范性实施例中,采用InAlAs(例如In.52Al.48As)实现所述间隔体层,其厚度处于0.2nm到10nm的范围内(例如,5nm)。一般而言,可以将间隔体层配置为向量子阱层提供压缩应变,因为其起着半导体沟道的作用。注意,可以在没有间隔体层的情况下实现其他能够从本发明的实施例受益的量子阱结构。
在这一示范性量子阱生长结构中的间隔体层上形成掺杂层,也可以像通常所做的那样实现所述掺杂层。一般而言,可以(通过对应的掺杂层)对下部势垒层和/或上部势垒层进行掺杂,从而向量子阱层提供载流子。在图1的示范性实施例中,上部势垒层包括掺杂层或者与掺杂层相关,并且在量子阱未受掺杂的位置提供载流子。例如,所述掺杂层可以是δ掺杂的(或者是调制掺杂的)。对于利用InAlAs上部势垒的n型器件而言,可以(例如)采用硅和/或碲杂质实现掺杂,对于p型器件而言,可以(例如)采用铍和/或碳实现所述掺杂层。所述掺杂层的厚度将取决于诸如掺杂类型和所采用的材料的因素。例如,在一个示范性实施例中,所述掺杂层是δ掺杂硅,并且具有大约到的厚度。在另一实施例中,所述掺杂层是调制掺杂的,并且具有大约到的厚度。例如,可以基于(例如)在量子阱层的沟道中有用的表面载流子浓度选择掺杂。在量子阱120的沟道内的掺杂为3.5×1012cm-2时,对于硅掺杂层而言,示范性浓度为6×1012cm-2。根据本公开,要认识到,可以采用具有一个或多个任何类型的掺杂层的量子阱结构实现本发明的实施例。
在这一示范性量子阱生长结构中的掺杂层上形成上部势垒层,也可以像通常所做的那样实现所述上部势垒层。在一个具体示范性实施例中,采用InAlAs(例如In0.52Al0.48As)实现上部势垒层,其厚度处于4nm到12nm之间(例如,8nm)。根据所制造的器件的类型,所述上部势垒层可以是肖特基势垒层,以实现低电压栅极控制。一般而言,上部势垒层材料的能带隙大于量子阱层的能带隙,从而将大部分电荷载流子限制在量子阱层内,以降低器件泄漏。注意,上部势垒层可以由与下部势垒层相同或者不同的材料形成。在一些实施例中,可以将上部势垒层实现为包括间隔体、掺杂层和上部势垒层的复合结构。此外,尽管这一示范性实施例将上部势垒与掺杂层联系起来,但是其他实施例可以额外(或者作为替代)将掺杂层与下部势垒层联系起来,从而向量子阱层提供载流子。在这种情况下,可以按照与和上部势垒层相关联的掺杂层类似的方式实现和底部势垒层相关联的掺杂层,也可以将其实现为包括间隔体层、掺杂层和下部势垒层的复合结构。
在形成大体包括前文所述的从衬底到上部势垒层的器件叠层之后,可以在上部势垒层之上形成蚀刻停止层。在一个具体示范性实施例中,采用铟磷(InP)实现所述蚀刻停止层,其厚度处于2nm到10nm的范围内(例如6nm)。将认识到,可以采用其他能够与给定的具体应用规则相结合的蚀刻停止结构材料。
还可以通过在蚀刻停止层之上形成接触层对所述器件叠层做进一步处理。所述接触层一般容许实现源极和漏极接触结构,可以将其配置成是n+或者n++掺杂的(对于NMOS器件而言),或者可以将其配置成是p+或p++掺杂的(对于PMOS器件而言)。在一个具体示范性实施例中,将所述接触层实现为n++In0.53Ga0.47As,其厚度处于10nm和30nm的范围内(20nm)。在一些情况下,可以按照梯度设置对所述接触层进行掺杂,例如,从采用In0.53Ga0.47As掺杂的硅开始,从x=0.53的InxGa1-xAs继续进行至x=1.0的InxGa1-xAs,从而使所述梯度变化终止于InAs。而且,所提供的具体接触层构造也取决于很多种因素,例如,所采用的半导体材料系以及器件类型和预期器件功能。
自对准接触结构
图2到图8采用截面图示出了根据本发明的实施例的自对准接触结构的形成。应当认识到,可以在图1所示的器件叠层上或者任何数量的其他量子阱生长结构上形成所述接触(例如,源极、漏极和栅极)。注意,在整个形成过程中可以包含诸如平面化处理(例如,化学机械抛光或CMP)和后续清洁处理的中间处理,尽管可能未对这样的处理做出明确讨论。
图2示出了根据本发明的一个实施例的图1的叠层上的硬掩模的沉积和构图。可以采用标准光刻技术执行这一操作,其包括硬掩模材料(例如二氧化硅、氮化硅和/或其他适当的硬掩模材料)的沉积;在硬掩模的部分上构造出抗蚀剂图案,所述部分将暂时保留,从而在接触形成过程中保护器件的有源区;通过蚀刻去除硬掩模的未遮蔽的(即没有抗蚀剂的)部分(例如,采用干法蚀刻或者其他适当的硬掩模去除工艺);之后剥离经构图的抗蚀剂。在图2所示的示范性实施例中,所得到的硬掩模对于器件叠层居中,并且形成在一个位置上,但是在其他实施例中,硬掩模可以偏移至叠层的一侧和/或位于叠层上的多个位置,具体取决于具体的有源器件。
图3示出了根据本发明的一个实施例的图2的量子阱生长结构中的隔离台面的形成。还可以采用标准光刻执行这一操作,其包括通过蚀刻去除所述叠层的未掩蔽的部分(例如,干法蚀刻),以及沉积电介质材料(例如,SiO2或其他适当的电介质材料,例如,掺碳氧化物、氮化硅、诸如八氟环丁烷或聚四氟乙烯的有机聚合物、氟硅酸盐玻璃以及诸如倍半硅氧烷、硅氧烷或有机硅酸盐玻璃的有机硅酸盐)。蚀刻深度可以存在变化,但是在一些示范性实施例中,所述深度处于所述叠层的顶表面下以及沟道下的到的范围内(由此还有效地设置了所沉积的电介质材料的厚度)。一般而言,所述蚀刻应当具有足够的深度,从而使得量子阱沟道受到电隔离(例如,与相邻的元件部分或者其他电势干扰源电隔离)。在形成隔离的台面以及沉积电介质材料之后,可以去除硬掩模(例如,干法或湿法蚀刻),并且可以对所述台面表面和所沉积的电介质材料进行抛光/平面化处理(例如,采用CMP)。注意,在适用并且希望的情况下,可以使这一台面隔离与浅沟槽隔离(STI)氧化物形成步骤结合起来,例如,所述形成步骤是常规硅工艺中通常采用的形成步骤。此外,注意,如果采用仅有台面蚀刻的流程,那么也可以在所述流程中稍后完成所述台面蚀刻步骤,甚至在所述流程的结尾完成所述台面蚀刻步骤。
图4示出了根据本发明的一个实施例的图3的量子阱生长结构的台面上的源极/漏极金属的沉积。可以采用诸如电子束蒸发或反应溅射的标准金属沉积工艺执行这一操作。例如,所述源极/漏极金属可以是镍、金、铂、铝、钛、钯、钛、镍或其他适当的接触金属或合金。可以对所述沉积进行掩模遮蔽、蚀刻、抛光等,以提供预期的金属化层,可以由所述金属化层制作器件源极/漏极接触。
在一个具体的示范性实施例中,假定所述接触层包括锗(Ge)。在一个这样的实例中,源极/漏极金属可以是薄薄地沉积的镍(例如,处于到的范围内,例如,大约)。这样的NiGe接触可以适用于扩散空位不会对器件的功能行使构成障碍的大型器件。然而,对于较小的器件而言,这样的NiGe接触可能受到与扩散空位相关的问题的影响,所述扩散空位是由合金形成过程中Ge向外扩散引起的。在这样的情况下,根据本发明的实施例,所沉积的源极/漏极金属可以是钛(Ti),由此提供形成于Ge扩散层上的TiGe接触合金。简而言之,将Ti和/或其他难熔金属用于Ge扩散上的源极/漏极金属有助于消除或者减少Ge扩散层中的空位以及晶体管扩散区域外的不必要的锗化物的形成。
图5示出了根据本发明的一个实施例的图4的量子阱生长结构的源极/漏极金属上的硬掩模的沉积和构图。一般在蚀刻栅极沟槽时,采用这一硬掩模保护金属接触。可以采用标准光刻技术执行硬掩模的沉积和构图,其包括硬掩模材料(例如二氧化硅、氮化硅和/或其他适当的硬掩模材料)的沉积;在硬掩模的部分上构造出抗蚀剂图案,所述部分将暂时保留,从而在栅极蚀刻过程中保护器件的接触;通过蚀刻去除硬掩模的未遮蔽的(即没有抗蚀剂的)部分(例如,采用干法蚀刻或者其他适当的硬掩模去除工艺);之后剥离经构图的抗蚀剂。在图5所示的示范性实施例中,栅极沟槽位置相对于器件叠层居中,并且形成在一个位置上,但是在其他实施例中,其可以向叠层的一侧偏移,和/或位于叠层上的多个位置上(例如,对于双器件配置而言)。
图6示出了根据本发明的一个实施例的图5所示的量子阱生长结构中的栅极沟槽的形成。例如,可以采用第一干法蚀刻蚀刻栅极区内的金属,采用第二干法蚀刻蚀刻到量子阱结构内,由此实施这一沟槽形成。所述第二干法蚀刻的深度可以是具有目标性的,例如,在量子阱界面附近停止,因而(例如)在势垒层、掺杂层或间隔体层内停止。例如,所述栅极沟槽的深度可以处于所述叠层的顶表面下的到的范围内(沟道之上的某处)。一般而言,所述第二蚀刻应当具有足够的深度,从而实现预期的器件传导。一旦蚀刻了栅极沟槽,之后就将硬掩模剥离下来。或者,如果希望的话,可以使硬掩模保留在原处,直到沉积了栅极金属为止。
图7示出了根据本发明的一个实施例的图6所示的量子阱生长结构的栅极沟槽中的间隔体的形成。可以采用标准沉积和蚀刻工艺对可以是氧化物或氮化物或者其他适当间隔体材料的间隔体层进行沉积和蚀刻,所述间隔体层可以具有(例如)处于到的范围内的厚度(例如,)。一般而言,所述间隔体层应当具有足够的厚度,从而使栅极电极与相邻的源极和漏极接触电隔离。注意,在源极/漏极接触和栅极电极之间不存在开放空间;相反存在将栅极电极与源极/漏极接触分开的间隔体层,从而实现相邻元件之间的自对准。在一个具体实施例中,如果希望的话,还可以在栅极沟槽的基底内沉积任选的高k栅极电介质,从而对栅极做进一步的电绝缘。例如,所述高k栅极电介质可以是厚度处于到的范围内(例如,)的膜,例如,可以采用氧化铪、氧化铝、五氧化钽、氧化锆、铝酸镧、钪酸钆、氧化铪硅、氧化镧、氧化镧铝、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或者其他这样的介电常数大于(例如)二氧化硅的介电常数的材料。在图7和图8中示出了这一任选的高k电介质的例子。
图8示出了根据本发明的一个实施例的图7所示的量子阱生长结构的栅极沟槽中的栅极金属的沉积。可以看出,所得到的栅极电极和源极/漏极接触是自对准的,因为在其间不存在开放的空气隙。相反,附加间隔体层在源极/漏极接触和栅极电极之间提供了电绝缘,而且还提供了栅极形成过程中的结构支持以及自对准。例如,所述栅极金属可以是钛、铂、金、铝、钛、镍、钯或其他适当的栅极金属或者这样的金属的结合。在一个具体的示范性实施例中,所述栅极电极具有从到的厚度(例如,)。
可以采用如图所示的所得到的集成电路器件作为晶体管,可以将其安装在几个微电子器件中的任何一个内,例如,安装在中央处理单元、存储器阵列、芯片上高速缓存或逻辑门内。类似地,很多种系统级应用也可以利用文中描述的集成电路。
工艺方法
图9示出了根据本发明的一个实施例的用于形成量子阱结构的低电阻自对准接触的方法。可以根据预期对所述量子阱结构进行配置,所述量子阱结构大体包括这样的叠层,所述叠层包括衬底、处于上下势垒层之间的量子阱层和接触层。
所述方法包括采用量子阱结构形成901台面。例如,所述形成可以包括:对接触层上的硬掩模进行构图,以保护所述结构的有源区;蚀刻掉未受掩模保护的区域;之后沉积电介质材料,由此隔离台面。所述方法还可以包括抛光和清洁过程,从而使所述结构准备好接受接下来的处理,就像通常在处理分段之间所做的那样。
所述方法继续在所述台面上沉积903源极/漏极金属(例如,镍、钛、镍钛或任何适当的接触金属或者难熔金属)的毯式盖层,以形成漏极和源极接触。按照毯式盖层的样式完成所述沉积,因为所述金属层是单个连续片层,这一点与每一接触的分立的单独金属层形成了对照。所述方法还可以包括对所述金属化片层构图,并且包括进行蚀刻,从而对所述金属化层进一步细化处理。
所述方法继续对源极/漏极金属上的硬掩模构图905,从而在源极接触和漏极接触之间形成栅极沟槽。例如,所述构图可以包括:沉积硬掩模材料;在硬掩模的部分上构造抗蚀剂图案,所述部分将暂时保留,从而在栅极蚀刻过程中保护器件的源极和漏极接触;通过蚀刻去除所述硬掩模的未掩蔽(即没有抗蚀剂的)部分(例如,采用干法蚀刻或者其他适当的硬掩模去除工艺);之后剥离所述经构图的抗蚀剂。注意,穿过所述毯式金属层蚀刻栅极沟槽直接在栅极沟槽的相应侧面处有效地界定了源极和漏极接触,因而在源极/漏极接触和栅极沟槽之间不存在开放空间。
所述方法继续将栅极沟槽蚀刻907到处于所述源极接触和漏极接触之间的台面内。在一种示范性情况下,如前所述,可以采用第一干法蚀刻蚀刻栅极区内的金属,采用第二干法蚀刻蚀刻到量子阱结构内,由此实施这一沟槽形成。可以选择第二干法蚀刻的深度,从而实现预期的器件传导。在蚀刻栅极沟槽之后,所述方法还可以包括将硬掩模从源极/漏极金属上剥离909下来,如果希望,可以在所述过程中的稍后时候完成所述操作。
所述方法继续在栅极沟槽的侧面上沉积911间隔体层,并任选通过蚀刻使其成形(例如,达到处于到的范围内的厚度)。所述间隔体材料可以是任何适当的电介质,从而隔离开将相对于彼此自对准的相邻栅极电极和源极/漏极接触。注意,所述栅极沟槽实质上可以是圆形或多边形的,提及栅极沟槽“侧面”的目的在于提及任何这样的构造,不应将其解释为暗示具有具体几何形状的结构。例如,“侧面”可以指圆形沟槽上的不同位置或者多边形沟槽的各个分立侧面,甚至指多边形沟槽的一个分立侧面上的不同位置。进一步回想,所述方法可以任选包括同时在栅极沟槽的基底内提供高k栅极电介质,以实现对栅极的进一步电绝缘,其形成可以发生于栅极沟槽侧面上的间隔体形成之前或之后。所述方法继续向栅极沟槽内沉积913栅极金属。例如,所述栅极金属可以是镍、钛、钛镍、钯、金、铝或者其他适当的栅极金属或合金。
因而,可以采用各种半导体异质结构(例如III-V或SiGe/Ge系)形成文中描述的接触。所述工艺流程实现了形成与晶体管栅极电极自对准的低电阻源极和漏极接触,并且显著改善了外部寄生电阻和布局密度。所述工艺流程可以利用毯式金属化连同接下来的光刻和蚀刻处理,从而将所述金属构图成隔离的源极区和漏极区,所述工艺流程也可以利用接近工艺流程的末尾实施的沟槽构图栅极工艺。所得到的栅极电极与源极/漏极接触自对准,并且通过间隔体层隔离。相反,常规接触并非是自对准的,因为在源极/漏极接触和栅极电极之间存在明显的缝隙,这还将导致布局密度的损失。此外,Rext随着源极/漏极金属与栅极的间隔的增大而增大。
根据本公开显然存在各种实施例和构造。例如,本发明的一个示范性实施例提供了一种为量子阱结构形成自对准接触的方法。所述方法包括在量子阱结构上沉积金属层以及通过所述金属层蚀刻栅极沟槽,由此直接在栅极沟槽的相应侧面处界定源极和漏极接触。所述方法继续在栅极沟槽的侧面上沉积间隔体层,并将栅极金属沉积到所述栅极沟槽内,以形成栅极电极。所述方法可以包括采用量子阱结构形成台面。在一种这样的情况下,采用量子阱结构形成台面包括在量子阱结构的接触层上构造硬掩模的图案,以保护有源区,蚀刻掉所述量子阱结构的未掩蔽的部分,以及将电介质材料沉积到蚀刻区域内。在另一种这样的情况下,在量子阱结构上沉积金属层之前执行采用量子阱结构形成台面。在另一种这样的情况下,在形成栅极电极、源极接触和漏极接触之后执行采用量子阱结构形成台面。在量子阱结构上沉积金属层可以包括(例如)沉积难熔金属。在量子阱结构上沉积金属层可以包括(例如)沉积钛。穿过所述金属层蚀刻栅极沟槽可以包括(例如)第一干法蚀刻,以蚀刻所述金属层,还可以包括第二干法蚀刻,从而蚀刻到所述量子阱结构内。所述方法可以包括在栅极沟槽的基底内沉积高k栅极电介质。
本发明的另一示范性实施例提供了一种集成电路器件。所述器件包括具有接触层的量子阱结构和沉积在所述接触层上的金属层。所述器件还包括穿过所述金属层的栅极沟槽,由此直接在栅极沟槽的相应侧面处界定源极和漏极接触。所述器件还包括处于栅极沟槽的侧面上的间隔体层以及所述栅极沟槽内的用于栅极电极的栅极金属。在一种具体的情况下,所述源极接触、漏极接触和栅极电极的至少其中之一包括难熔金属。在另一种具体的情况下,所述源极接触、漏极接触和栅极电极的至少其中之一包括钛。在另一种具体的情况下,所述量子阱结构还包括底部势垒层、量子阱层、间隔体层、掺杂层和上部势垒层。在一种这样的情况下,栅极沟槽停止于上部势垒层、掺杂层或间隔体层之一内。在另一种这样的情况下,在栅极电极和量子阱结构之间提供高k栅极电介质。在一种这样的情况下,高k栅极电介质层直接位于所述栅极电极与所述上部势垒层、掺杂层或间隔体层之一之间。
本发明的另一示范性实施例提供了一种集成电路器件。在这一例子中,所述器件包括量子阱结构,所述量子阱结构具有底部势垒层、量子阱层、间隔体层、掺杂层、上部势垒层和接触层。所述器件还包括沉积在所述接触层上的金属层和穿过所述金属层的栅极沟槽,由此直接在所述栅极沟槽的相应侧面处界定源极和漏极接触,其中,所述栅极沟槽停止在所述上部势垒层、掺杂层或间隔体层之一内。所述器件还包括位于栅极沟槽的侧面上的间隔体层、处于栅极沟槽内的用于栅极电极的栅极金属以及处于所述栅极电极和量子阱结构之间的高k栅极电介质层。在一种具体的情况下,所述源极接触、漏极接触和栅极电极的至少其中之一包括难熔金属。在另一种具体的情况下,所述源极接触、漏极接触和栅极电极的至少其中之一包括钛。在另一种具体情况下,所述高k栅极电介质层直接位于所述栅极电极与所述上部势垒层、掺杂层或间隔体层之一之间。
本发明的另一示范性实施例提供了一种集成电路器件。在这一例子中,所述器件包括具有接触层的量子阱结构。所述器件还包括沉积在所述接触层上的源极金属层和漏极金属层以及在所述源极金属层和漏极金属层之间嵌入到量子阱结构内的栅极电极。所述器件还包括形成于所述栅极电极和所述源极金属层之间的第一间隔体层,其中,所述栅极电极与所述第一间隔体层物理接触,所述第一间隔体层与所述源极金属层物理接触。所述器件还包括形成于所述栅极电极和所述漏极金属层之间的第二间隔体层,其中,所述栅极电极与所述第二间隔体层物理接触,所述第二间隔体层与所述漏极金属层物理接触。注意,所述第一和第二间隔体层可以是围绕所述栅极电极的一个连续的间隔体层。在一种具体的情况下,所述量子阱结构还包括底部势垒层、量子阱层、间隔体层、掺杂层和上部势垒层。在另一种具体的情况下,在栅极电极和量子阱结构之间提供高k栅极电介质层,其中,所述高k栅极电介质层直接位于所述栅极电极与所述上部势垒层、掺杂层或间隔体层之一之间。
已经出于例示和说明的目的给出了前述对本发明的示范性实施例的描述。其目的并非在于对本发明进行穷举,或者将本发明限定为所公开的精确形式。根据这一教导,很多修改和变化都是可能的。本发明的范围不受这一详细说明的限制,而是由所附权利要求限定。
Claims (25)
1.一种集成电路器件,包括:
衬底;
位于所述衬底上方的缓冲层;
位于所述缓冲层上方的量子阱沟道层,所述量子阱沟道层包括In、Ga和As;
位于所述量子阱沟道层上方的半导体接触层,所述半导体接触层包括In和As;
直接位于所述半导体接触层上的金属层;
栅极沟槽,其穿过所述金属层并且穿过所述半导体接触层,直接在所述栅极沟槽的相应侧面处界定源极金属接触和漏极金属接触以及半导体源极区和半导体漏极区,所述栅极沟槽具有底部和壁;
电介质间隔体材料,其位于所述栅极沟槽的所述壁上并且延伸至所述栅极沟槽的所述底部,其中所述电介质间隔体材料是氮化物;
位于所述栅极沟槽的所述底部上的栅极电介质层,其中所述栅极电介质层是包括氧化铝的高k电介质层,并且其中所述栅极电介质层位于所述栅极沟槽的所述底部处的所述电介质间隔体材料之间,并且在横向上与所述栅极沟槽的所述底部处的所述电介质间隔体材料相邻;以及
位于所述栅极沟槽中的所述栅极电介质层上用于栅极电极的栅极材料,所述栅极材料包括金属。
2.根据权利要求1所述的集成电路器件,其中所述电介质间隔体材料位于所述栅极材料与所述源极金属接触和漏极金属接触之间。
3.一种半导体器件,包括:
设置在衬底上方的量子阱结构,所述量子阱结构具有位于量子阱层上方的上部势垒层;
沟槽,其穿过被设置在所述量子阱结构中的所述上部势垒层并且位于所述量子阱层的上方,所述沟槽具有侧壁和底部;
源极/漏极金属区,其被设置在所述量子阱结构上并且位于所述沟槽的两侧上;
栅极电极,其被设置在所述沟槽中;以及
电介质材料,其位于所述沟槽的所述侧壁上并且延伸至所述沟槽的所述底部,其中所述电介质材料位于所述栅极电极与所述源极/漏极金属区之间。
4.根据权利要求3所述的半导体器件,其中所述量子阱结构包括:底部势垒层、设置在所述底部势垒层上方的所述量子阱层、位于所述量子阱层上方的半导体间隔体层、位于所述量子阱层上方的掺杂层、位于所述量子阱层上方的上部势垒层、以及位于所述上部势垒层上方的接触层,其中所述源极/漏极金属区设置在所述接触层上。
5.根据权利要求4所述的半导体器件,其中所述沟槽的所述底部位于所述掺杂层中。
6.根据权利要求4所述的半导体器件,其中所述沟槽的所述底部位于所述半导体间隔体层中。
7.根据权利要求3所述的半导体器件,其中所述电介质材料位于所述源极/漏极金属区与所述栅极电极之间。
8.根据权利要求3所述的半导体器件,其中栅极电介质层位于所述沟槽的所述底部上,并且位于所述栅极电极与所述量子阱结构之间。
9.根据权利要求4所述的半导体器件,还包括蚀刻停止层。
10.根据权利要求9所述的半导体器件,其中所述蚀刻停止层是InP。
11.一种半导体器件,包括:
设置在衬底上方的量子阱结构,所述量子阱结构具有位于量子阱层上方的上部势垒层;
沟槽,其穿过被设置在所述量子阱结构中的所述上部势垒层并且位于所述量子阱层的上方,所述沟槽具有侧壁和底部;
源极/漏极金属区,其被设置在所述量子阱结构上并且位于所述沟槽的两侧上;
栅极电极,其被设置在所述沟槽中;
栅极电介质层,其位于所述沟槽的所述底部上并且位于所述栅极电极与所述量子阱结构之间;以及
电介质材料,其位于所述沟槽的所述侧壁上并且延伸至所述沟槽的所述底部,其中所述电介质材料位于所述栅极电极与所述源极/漏极金属区之间,并且位于所述沟槽的所述侧壁与所述栅极电介质层之间。
12.根据权利要求11所述的半导体器件,其中所述栅极电介质层是高k栅极电介质层。
13.根据权利要求11所述的半导体器件,其中所述量子阱结构包括:底部势垒层、设置在所述底部势垒层上方的所述量子阱层、位于所述量子阱层上方的半导体间隔体层、位于所述量子阱层上方的掺杂层、以及位于所述上部势垒层上方的接触层,其中所述源极/漏极金属区设置在所述接触层上。
14.根据权利要求13所述的半导体器件,其中所述沟槽的所述底部位于所述掺杂层中。
15.根据权利要求13所述的半导体器件,其中所述沟槽的所述底部位于所述半导体间隔体层中。
16.根据权利要求13所述的半导体器件,还包括蚀刻停止层。
17.根据权利要求16所述的半导体器件,其中所述蚀刻停止层是InP。
18.一种半导体器件,包括:
设置在衬底上方的量子阱结构,所述量子阱结构具有位于量子阱层上方的上部势垒层;
沟槽,其穿过被设置在所述量子阱结构中的所述上部势垒层并且位于所述量子阱层的上方,所述沟槽具有侧壁和底部;
源极/漏极金属区,其被设置在所述量子阱结构上并且位于所述沟槽的两侧上;
栅极电极,其被设置在所述沟槽中;
栅极电介质层,其位于所述沟槽的所述底部上并且位于所述栅极电极与所述量子阱结构之间;以及
电介质材料,其位于所述沟槽的所述侧壁上并且延伸至所述沟槽的所述底部,其中所述电介质材料位于所述栅极电极与所述源极/漏极金属区之间,其中所述栅极电极在横向上与所述源极/漏极金属区相邻,并且其中所述电介质材料被设置在所述栅极电介质层的一部分上。
19.根据权利要求18所述的半导体器件,其中所述栅极电介质层是高k栅极电介质层。
20.根据权利要求18所述的半导体器件,其中所述量子阱结构包括:底部势垒层、设置在所述底部势垒层上方的所述量子阱层、位于所述量子阱层上方的半导体间隔体层、位于所述量子阱层上方的掺杂层、以及位于所述上部势垒层上方的接触层,其中所述源极/漏极金属区设置在所述接触层上。
21.根据权利要求20所述的半导体器件,其中所述沟槽的所述底部位于所述掺杂层中。
22.根据权利要求20所述的半导体器件,其中所述沟槽的所述底部位于所述半导体间隔体层中。
23.根据权利要求20所述的半导体器件,还包括蚀刻停止层。
24.根据权利要求23所述的半导体器件,其中所述蚀刻停止层是InP。
25.一种集成电路器件,包括:
衬底;
位于所述衬底上方的缓冲层;
位于所述缓冲层上方的量子阱沟道层,所述量子阱沟道层包括In、Ga和As;
位于所述量子阱沟道层上方的半导体接触层,所述半导体接触层包括In和As;
直接位于所述半导体接触层上的金属层;
栅极沟槽,其穿过所述金属层并且穿过所述半导体接触层,直接在所述栅极沟槽的相应侧面处界定源极金属接触和漏极金属接触以及半导体源极区和半导体漏极区,所述栅极沟槽具有底部和壁;
电介质间隔体材料,其位于所述栅极沟槽的所述壁上并且延伸至所述栅极沟槽的所述底部,其中所述电介质间隔体材料是氮化物;
位于所述栅极沟槽的所述底部上的栅极电介质层,其中所述栅极电介质层是包括氧化铝的高k电介质层,并且其中,所述栅极电介质层位于所述栅极沟槽的所述底部处的所述电介质间隔体材料之间,并且在横向上与所述栅极沟槽的所述底部处的所述电介质间隔体材料相邻;以及
位于所述栅极沟槽中的所述栅极电介质层上用于栅极电极的栅极材料,所述栅极材料包括金属。
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WO2011087606A3 (en) | 2011-10-20 |
KR20120089354A (ko) | 2012-08-09 |
TW201137988A (en) | 2011-11-01 |
TWI428991B (zh) | 2014-03-01 |
US10177249B2 (en) | 2019-01-08 |
EP3012868B1 (en) | 2021-03-31 |
US20140326953A1 (en) | 2014-11-06 |
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US9704981B2 (en) | 2017-07-11 |
US20170309735A1 (en) | 2017-10-26 |
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