CN105575818A - Pmos工艺方法 - Google Patents

Pmos工艺方法 Download PDF

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CN105575818A
CN105575818A CN201511026570.9A CN201511026570A CN105575818A CN 105575818 A CN105575818 A CN 105575818A CN 201511026570 A CN201511026570 A CN 201511026570A CN 105575818 A CN105575818 A CN 105575818A
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source
atom
pmos
impurity
drain
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钱文生
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种PMOS工艺方法，是在PMOS晶体管的源、漏注入之后，进行一次大原子杂质的离子注入，在源、漏下方形成大量由间隙原子构成的晶格缺陷。所述的大原子杂质，为硅、锗一类的元素，注入剂量>1E14/cm2，注入能量以杂质分布的峰值位置位于源漏结下方200埃以上。大原子离子注入之后，立即进行快速热退火，促使间隙原子增强硼扩散。本发明利用间隙原子束增强硼扩散的原理，在源漏结下方形成大量的间隙原子束，并快速热退火加大硼的纵向扩散，形成缓变的PMOS源漏结，增强击穿电压和降低结电容，降低器件的热载流子效应，提高器件可靠性。

Description

PMOS工艺方法
技术领域
本发明涉及半导体集成电路制造领域，特别是指一种PMOS工艺方法。
背景技术
短沟道CMOS器件设计中，为了控制短沟道效应，通常尽可能降低轻掺杂源漏(LDD)和源漏(SD)的杂质掺杂浓度和离子注入能量，但会造成很多的负面效应：1、会降低器件的驱动电流；2、降低器件源漏结的击穿电压；3、增加LDD结和SD结的寄生结电容。这些负面效应降低了器件的性能。
另外，CMOS器件都存在较严重的热载流子效应。对PMOS来说，为了增加源漏结击穿电压和降低源漏结电容，通常在源漏制作中采用较高能量的硼离子注入，形成缓变源漏结。但较高能量的硼注入会同时带来较大的横向扩散，对LDD区域进行额外掺杂，这会增加器件的热载流子效应。
发明内容
本发明所要解决的技术问题是提供一种PMOS工艺方法，降低器件的热载流子效应，提高器件的可靠性。
为解决上述问题，本发明所述的PMOS工艺方法，是在PMOS晶体管的源、漏注入之后，进行一次大原子杂质的离子注入，所述大原子杂质是指原子量≥硅的杂质；大原子杂质注入之后，立即进行一次快速热退火。
所述大原子杂质注入，在源、漏下方形成大量由间隙原子构成的晶格缺陷。
所述的大原子杂质，为硅、锗一类的元素，注入剂量>1E14/cm2，注入能量以杂质分布的峰值位置位于源漏结下方200埃以上。
所述大原子离子注入之后，立即进行快速热退火，促使间隙原子增强硼扩散。
本发明所述的PMOS工艺方法，通过增加大原子杂质的注入，在源漏结的下方形成间隙离子束，增加结的击穿电压，降低结电容。同时降低器件的热载流子效应，提高器件可靠性。
附图说明
图1是大原子杂质离子注入示意图。
图2是本发明与传统工艺硼扩散分布示意图。
图3是本发明与传统工艺硼扩散深度与浓度曲线示意图。
图4是本发明与传统工艺横向电场分布对比示意图。
图5是场强与深度分布曲线图。
具体实施方式
本发明所述的PMOS工艺方法，是在PMOS晶体管的源、漏注入之后，进行一次大原子杂质的离子注入，在源、漏下方形成大量由间隙原子构成的晶格缺陷。
所述的大原子杂质，为硅、锗一类的原子量≥硅的元素，注入剂量>1E14/cm2，注入能量以杂质分布的峰值位置位于源漏结下方200埃以上。
所述大原子离子注入之后，立即进行快速热退火，促使间隙原子增强硼扩散。间隙原子指某个晶格间隙中挤进了原子。又称填隙子，是原子脱离其平衡位置进入原子间隙而形成的。晶格原子之间的间隙是很小的，一个原子硬挤进去必然使周围原子偏离平衡位置，造成晶格畸变，因此也是一种点缺陷。
本发明利用间隙原子束([311]或[113]缺陷)增强硼扩散的原理，在PMOS源漏硼注入后，进行大原子杂质的离子注入，在源漏结的下方形成大量的间隙原子束，并在后续的源漏快速热退火中加大硼的纵向扩散，形成缓变PMOS源漏结，有效增加结的击穿电压和降低结电容。由于PLDD部分并未接受大原子杂质的离子注入，该区域间隙原子束浓度有限，不会形成硼的增强扩散，有利于降低器件的热载流子效应，提高器件的可靠性。
由间隙原子构成的晶格缺陷与硼原子结合形成间隙原子束，并在后续的源漏快速退火过程中增强硼的纵向扩散，有利于形成更加缓变的P型源漏结，提高结的击穿电压，降低结的寄生电容。由图2及图3所示的曲线可看出本发明硼的分布更加缓变了，但未进一步减小器件的有效沟道长度。
间隙原子束，并在后续的源漏快速退火过程中增强硼的纵向扩散，如图4所示，有利于形成更加缓变的P型源漏结，使得P型源漏结表面浓度有一定降低，同时没有增加PLDD区域的掺杂浓度，对PMOS器件的热载流子效应的控制有一定效果。图5为传统器件和本发明器件沟道表面的横向电场强度分布，从图中可以看出本发明的峰值横向电场明显降低。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (3)

1.一种PMOS工艺方法，其特征在于：在PMOS晶体管的源、漏注入之后，进行一次大原子杂质的离子注入，所述大原子杂质是指原子量≥硅的杂质；在大原子杂质注入之后，立即进行快速热退火。
2.如权利要求1所述的PMOS工艺方法，其特征在于：所述大原子杂质注入，在源、漏下方形成大量由间隙原子构成的晶格缺陷。
3.如权利要求1所述的PMOS工艺方法，其特征在于：所述的大原子杂质，为硅、锗一类的元素，注入剂量>1E14/cm2，注入能量以杂质分布的峰值位置位于源漏结下方200埃以上。
CN201511026570.9A 2015-12-31 2015-12-31 Pmos工艺方法 Pending CN105575818A (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020040298A (ko) * 2000-11-24 2002-05-30 박종섭 피모스 트랜지스터 제조방법
US20020063294A1 (en) * 2000-03-30 2002-05-30 International Business Machines Reduction of reverse short channel effects by implantation of neutral dopants
CN104425282A (zh) * 2013-09-10 2015-03-18 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020063294A1 (en) * 2000-03-30 2002-05-30 International Business Machines Reduction of reverse short channel effects by implantation of neutral dopants
KR20020040298A (ko) * 2000-11-24 2002-05-30 박종섭 피모스 트랜지스터 제조방법
CN104425282A (zh) * 2013-09-10 2015-03-18 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法

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