CN105489490A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN105489490A
CN105489490A CN201410474214.2A CN201410474214A CN105489490A CN 105489490 A CN105489490 A CN 105489490A CN 201410474214 A CN201410474214 A CN 201410474214A CN 105489490 A CN105489490 A CN 105489490A
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interlayer dielectric
dielectric layer
metal gates
layer
mask layer
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CN105489490B (zh
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林静龄
黄志森
洪庆文
吴家荣
张宗宏
李怡慧
陈意维
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。该半导体元件制作方法包括，首先提供一基底，该基底上设有一金属栅极以及一层间介电层环绕该金属栅极。然后去除部分金属栅极以形成一开口，并形成一掩模层填满开口于层间介电层上并同时形成一孔洞(void)于开口内。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种金属栅极晶体管制作工艺。
背景技术
在现有半导体产业中，多晶硅广泛地应用于半导体元件如金属氧化物半导体(metal-oxide-semiconductor，MOS)晶体管中，作为标准的栅极填充材料选择。然而，随着MOS晶体管尺寸持续地微缩，传统多晶硅栅极因硼穿透(boronpenetration)效应导致元件效能降低，及其难以避免的空乏效应(depletioneffect)等问题，使得等效的栅极介电层厚度增加、栅极电容值下降，进而导致元件驱动能力的衰退等困境。因此，半导体业界更尝试以新的栅极填充材料，例如利用功函数(workfunction)金属来取代传统的多晶硅栅极，用以作为匹配高介电常数(High-K)栅极介电层的控制电极。
在现今金属栅极晶体管制作过程中，特别是在进行自行对准接触插塞(self-alignedcontacts,SAC))制作工艺时通常会先去除部分金属栅极并于金属栅极上填入一保护用的掩模层，然后以平坦化制作工艺例如化学机械研磨去除部分掩模层并使剩余的掩模层表面与层间介电层表面齐平。然而此设计容易使后续所形成的接触插塞过于接近金属栅极并影响整个元件的运作。因此如何改良现行金属栅极制作工艺即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例是公开一种制作半导体元件的方法。首先提供一基底，该基底上设有一金属栅极以及一层间介电层环绕该金属栅极。然后去除部分金属栅极以形成一开口，并形成一掩模层填满开口于层间介电层上并同时形成一孔洞(void)于开口内。
本发明另一实施例是公开一种制作半导体元件的方法。首先提供一基底，该基底上设有一金属栅极以及一层间介电层环绕该金属栅极。然后去除部分金属栅极以形成一开口，沉积一掩模层填满开口于层间介电层上，并进行一平坦化制作工艺去除部分掩模层并使剩余的掩模层上表面高于层间介电层的上表面。
本发明又一实施例是公开一种半导体元件，其包含一基底、一金属栅极设于基底上、一层间介电层环绕金属栅极、一掩模层覆盖金属栅极及层间介电层以及一孔洞(void)位于金属栅极上的遮盖层中。
附图说明
图1至图5为本发明优选实施例制作一半导体元件的方法示意图。
主要元件符号说明
12基底14鳍状结构
18金属栅极24间隙壁
26源极/漏极区域32层间介电层
34功函数金属层36低阻抗金属层
38开口40掩模层
42孔洞44接触洞
46接触插塞
具体实施方式
请参照图1至图5，图1至图5为本发明优选实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上定义有一晶体管区，例如一PMOS晶体管区或一NMOS晶体管区。
基底12上具有至少一鳍状结构14及一绝缘层(图未示)，其中鳍状结构14的底部是被绝缘层，例如氧化硅所包覆而形成浅沟隔离，且部分的鳍状结构14上另分别设有多个金属栅极18。需注意的是，本实施例虽以四个金属栅极为例，但金属栅极的数量并不局限于此，而可视制作工艺需求任意调整。
上述鳍状结构14的形成方式可以包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中。接着，对应三栅极晶体管元件及双栅极鳍状晶体管元件结构特性的不同，而可选择性去除或留下图案化掩模，并利用沉积、化学机械研磨(chemicalmechanicalpolishing,CMP)及回蚀刻制作工艺而形成一环绕鳍状结构14底部的绝缘层。除此之外，鳍状结构14的形成方式另也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出半导体层，此半导体层即可作为相对应的鳍状结构14。同样的，另可以选择性去除或留下图案化硬掩模层，并通过沉积、CMP及回蚀刻制作工艺形成一绝缘层以包覆住鳍状结构14的底部。另外，当基底12为硅覆绝缘(SOI)基板时，则可利用图案化掩模来蚀刻基底上的一半导体层，并停止于此半导体层下方的一底氧化层以形成鳍状结构，故可省略前述制作绝缘层的步骤。
金属栅极18的制作方式可依据制作工艺需求以先栅极(gatefirst)制作工艺、后栅极(gatelast)制作工艺的先栅极介电层(high-kfirst)制作工艺以及后栅极制作工艺的后栅极介电层(high-klast)制作工艺等方式制作完成。以本实施例的先栅极介电层制作工艺为例，可先于鳍状结构14与绝缘层上形成一优选包含高介电常数介电层与多晶硅材料所构成的虚置栅极(图未示)，然后于虚置栅极侧壁形成间隙壁24。接着于间隙壁24两侧的鳍状结构14以及/或基底12中形成一源极/漏极区域26与外延层(图未示)、形成一接触洞蚀刻停止层(图未示)覆盖虚置栅极，并形成一由四乙氧基硅烷(Tetraethylorthosilicate,TEOS)所组成的层间介电层32于接触洞蚀刻停止层上。
之后可进行一金属栅极置换(replacementmetalgate)制作工艺，先平坦化部分的层间介电层32及接触洞蚀刻停止层，并再将虚置栅极转换为一金属栅极。金属栅极置换制作工艺可包括先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammoniumhydroxide,NH4OH)或氢氧化四甲铵(TetramethylammoniumHydroxide,TMAH)等蚀刻溶液来去除虚置栅极中的多晶硅材料以于层间介电层32中形成一凹槽。之后形成一至少包含U型功函数金属层34与低阻抗金属层36的导电层于该凹槽内，并再搭配进行一平坦化制作工艺使U型功函数金属层34与低阻抗金属层36的表面与层间介电层表面齐平。
在本实施例中，功函数金属层34优选用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层34可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层34可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层34与低阻抗金属层36之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层44则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungstenphosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极乃此领域者所熟知技术，在此不另加赘述。
接着以蚀刻方式去除部分金属栅极18，例如去除部分功函数金属层34与低阻抗金属层36，以于各金属栅极18上形成一开口38并位于间隙壁24内。
然后如图2所示，沉积一掩模层40于层间介电层32与金属栅极18上并填入开口38。其中掩模层40优选由氮化硅或碳氮化硅(SiCN)所构成，但不局限于此。依据本发明的优选实施例，将掩模层40覆盖于层间介电层32上并填入开口32的同时优选形成一孔洞(void)42于各开口38内的掩模层40中。换句话说，孔洞42的位置优选位于各金属栅极18上的遮盖层40中且优选低于层间介电层32的上表面。
如图3所示，然后进行一平坦化制作工艺，例如以CMP制作工艺去除部分掩模层40但不将掩模层40研磨至层间介电层32表面，亦即使剩余的掩模层40上表面仍高于层间介电层32的上表面。
接着如图4所示，进行一光刻暨蚀刻制作工艺，利用一图案化光致抗蚀剂(图未示)为掩模进行一蚀刻制作工艺，去除部分掩模层40及层间介电层32，以于各金属栅极18旁形成多个接触洞44暴露出基底12中的源极/漏极区域26。
如图5所示，之后再于接触洞44中填入所需的金属材料，并搭配进行一平坦化制作工艺去除部分金属材料以于各接触洞44中形成接触插塞46。由于制作接触插塞的过程为本技术领域所熟知技术，在此不另加赘述。至此即完成本发明优选实施例制作一半导体元件的方法。
由于本发明在平坦化部分掩模层40时，不会将掩模层40研磨至层间介电层32表面，故剩余的掩模层40上表面高于层间介电层32的上表面。换句话说，各间隙壁24的顶部仍被掩模层40覆盖并保护之，而使该平坦化制作工艺不会伤及间隙壁24的顶部。如图5所示，接触插塞46与层间介电层32上表面的接触点至金属栅极18的距离，便因不受损的间隙壁24而相对较大，使得后续所形成的接触插塞就不会因过于接近金属栅极而影响整个元件的运作。
请再参照图5，其公开一种半导体元件结构。如图中所示，本发明的半导体元件优选包含一基底12、多个金属栅极18设于基底12上、一层间介电层32环绕金属栅极18、一掩模层40覆盖于金属栅极18及层间介电层32上以及一孔洞42位于各金属栅极18上的遮盖层40中。
在本实施例中，孔洞42优选低于层间介电层32的上表面，但不局限于此，又可视掩模层40沉积条件的不同使孔洞42形成于金属栅极18上的掩模层40中且又同时高于层间介电层32上表面，此实施例也属本发明所涵盖的范围。另外本实施例又包含多个接触插塞46设于邻近金属栅极18的掩模层40及层间介电层32中并连接基底12的源极/漏极区域26。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (10)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底上设有一金属栅极以及一层间介电层环绕该金属栅极；
去除部分该金属栅极以形成一开口；以及
形成一掩模层填满该开口及该层间介电层上并同时形成一孔洞(void)于该开口内。
2.如权利要求1所述的方法，其中该掩模层包含氮化硅或碳氮化硅(SiCN)。
3.如权利要求1所述的方法，还包含形成一接触插塞于该掩模层及该层间介电层中。
4.一种制作半导体元件的方法，包含：
提供一基底，该基底上设有一金属栅极以及一层间介电层环绕该金属栅极；
去除部分该金属栅极以形成一开口；
沉积一掩模层填满该开口及该层间介电层上；以及
进行一平坦化制作工艺去除部分该掩模层并使剩余的该掩模层上表面高于该层间介电层的上表面。
5.如权利要求4所述的方法，其中该掩模层包含氮化硅。
6.如权利要求4所述的方法，还包含形成一接触插塞于该掩模层及该层间介电层中。
7.一种半导体元件，包含：
基底；
金属栅极，设于该基底上；
层间介电层，环绕该金属栅极；
掩模层，覆盖该金属栅极及该层间介电层上；以及
孔洞(void)，位于该金属栅极上的该遮盖层中。
8.如权利要求7所述的半导体元件，其中该掩模层包含氮化硅或碳氮化硅(SiCN)。
9.如权利要求7所述的半导体元件，其中该孔洞低于该层间介电层的上表面。
10.如权利要求7所述的半导体元件，还包含接触插塞，设于该掩模层及该层间介电层中。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110729343A (zh) * 2018-07-17 2020-01-24 联华电子股份有限公司 半导体元件及其制作方法
CN110767627A (zh) * 2018-07-27 2020-02-07 联华电子股份有限公司 半导体装置及其制作工艺
CN111477738A (zh) * 2019-01-23 2020-07-31 联华电子股份有限公司 一种制作半导体元件的方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10062762B2 (en) * 2014-12-23 2018-08-28 Stmicroelectronics, Inc. Semiconductor devices having low contact resistance and low current leakage
US10157778B2 (en) * 2016-05-31 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
TWI727068B (zh) 2017-07-03 2021-05-11 聯華電子股份有限公司 半導體裝置以及其製作方法
CN109509721B (zh) * 2017-09-14 2021-05-25 联华电子股份有限公司 半导体元件及其制作方法
US11282920B2 (en) 2019-09-16 2022-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with air gap on gate structure and method for forming the same
DE102020123264B4 (de) * 2020-03-30 2022-11-10 Taiwan Semiconductor Manufacturing Co. Ltd. Halbleitervorrichtung und Verfahren zu dessen Herstellung
US11563001B2 (en) * 2020-03-30 2023-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Air spacer and capping structures in semiconductor devices
CN114256135A (zh) * 2020-09-22 2022-03-29 长鑫存储技术有限公司 开口结构及其形成方法、接触插塞及其形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070099414A1 (en) * 2005-10-31 2007-05-03 Kai Frohberg Semiconductor device comprising a contact structure based on copper and tungsten
US20120139061A1 (en) * 2010-12-02 2012-06-07 International Business Machines Corporation Self-Aligned Contact For Replacement Gate Devices
CN103299428A (zh) * 2011-01-10 2013-09-11 国际商业机器公司 用于高k/金属栅工艺流程的自对准接触
CN103681331A (zh) * 2012-09-10 2014-03-26 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI242797B (en) * 2004-06-01 2005-11-01 Nanya Technology Corp Method for forming self-aligned contact of semiconductor device
US8536040B1 (en) 2012-04-03 2013-09-17 Globalfoundries Inc. Techniques for using material substitution processes to form replacement metal gate electrodes of semiconductor devices with self-aligned contacts
US9130023B2 (en) 2012-06-05 2015-09-08 Kabushiki Kaisha Toshiba Isolated insulating gate structure
US8741717B2 (en) 2012-07-02 2014-06-03 GlobalFoundries, Inc. Methods for fabricating integrated circuits having improved metal gate structures
US9006072B2 (en) * 2013-03-14 2015-04-14 United Microelectronics Corp. Method of forming metal silicide layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070099414A1 (en) * 2005-10-31 2007-05-03 Kai Frohberg Semiconductor device comprising a contact structure based on copper and tungsten
US20120139061A1 (en) * 2010-12-02 2012-06-07 International Business Machines Corporation Self-Aligned Contact For Replacement Gate Devices
CN103299428A (zh) * 2011-01-10 2013-09-11 国际商业机器公司 用于高k/金属栅工艺流程的自对准接触
CN103681331A (zh) * 2012-09-10 2014-03-26 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110729343A (zh) * 2018-07-17 2020-01-24 联华电子股份有限公司 半导体元件及其制作方法
CN110729343B (zh) * 2018-07-17 2023-04-07 联华电子股份有限公司 半导体元件及其制作方法
CN110767627A (zh) * 2018-07-27 2020-02-07 联华电子股份有限公司 半导体装置及其制作工艺
US11145546B2 (en) 2018-07-27 2021-10-12 United Microelectronics Corp. Method of forming semiconductor device
CN110767627B (zh) * 2018-07-27 2022-03-22 联华电子股份有限公司 半导体装置及其制作工艺
CN111477738A (zh) * 2019-01-23 2020-07-31 联华电子股份有限公司 一种制作半导体元件的方法
CN111477738B (zh) * 2019-01-23 2023-05-12 联华电子股份有限公司 一种制作半导体元件的方法

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