CN110729343A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN110729343A
CN110729343A CN201810784990.0A CN201810784990A CN110729343A CN 110729343 A CN110729343 A CN 110729343A CN 201810784990 A CN201810784990 A CN 201810784990A CN 110729343 A CN110729343 A CN 110729343A
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semiconductor
dielectric layer
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insulating layer
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马瑞吉
苏治维
温哲民
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法，该制作半导体元件的方法为，首先提供一基底，该基底包含一第一半导体层、一绝缘层设于第一半导体层上以及一第二半导体层设于绝缘层上，然后形成一金属氧化物半导体晶体管于基底上，形成一层间介电层于金属氧化物半导体晶体管上，去除部分层间介电层以形成一第一开口暴露出绝缘层，再进行一湿蚀刻制作工艺经由该第一开口去除部分绝缘层以形成一第一气孔于金属氧化物半导体晶体管下方。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于主动元件(有源元件)底部形成气孔并由此降低元件电容值的方法。
背景技术
在无线射频(radio frequency,RF)集成电路应用中，例如RF选频装置(RFswitchdevice)或功率放大器(power amplifier device)，其性能经常受到寄生表面电荷(parasitic surface charge)问题的影响。因为寄生表面电荷而产生谐波效应(harmoniceffect)，进而影响装置效能。有数种晶片制作工艺技术用以解决此问题，例如使用绝缘层上覆盖半导体层(semiconductor-on-insulator,SOI)的晶片将电荷与高电阻晶片基板互相隔离。然而现今采用SOI晶片的设计通常过于昂贵，因此如何在更低成本的情况下改良现有制作工艺提升元件整体效能并提供更有竞争力的产品即为现今一重要课题。
发明内容
本发明揭露一种制作半导体元件的方法。首先提供一基底，该基底包含一第一半导体层、一绝缘层设于第一半导体层上以及一第二半导体层设于绝缘层上，然后形成一金属氧化物半导体晶体管于基底上，形成一层间介电层于金属氧化物半导体晶体管上，去除部分层间介电层以形成一第一开口暴露出绝缘层，再进行一湿蚀刻制作工艺经由该第一开口去除部分绝缘层以形成一第一气孔于金属氧化物半导体晶体管下方。
本发明另一实施例揭露一种半导体元件，其主要包含：一基底，该基底包含一第一半导体层、一绝缘层设于第一半导体层上以及一第二半导体层设于绝缘层上；一金属氧化物半导体晶体管设于基底上；以及一第一气孔设于绝缘层内并设于金属氧化物半导体晶体管正下方。
本发明又一实施例揭露一种半导体元件，其包含：一基底，该基底包含一第一半导体层、一绝缘层设于该第一半导体层上以及一第二半导体层设于该绝缘层上；一金属氧化物半导体晶体管设于基底上；一层间介电层设于金属氧化物半导体晶体管上；以及一第一气孔设于绝缘层内以及金属氧化物半导体晶体管下方并向上延伸至层间介电层内，其中该第一气孔包含U形。
附图说明
图1至图7为本发明一实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 第一半导体层
16 绝缘层 18 第二半导体层
20 陷阱(陷捕)层 22 浅沟隔离
24 衬垫层 26 绝缘层
28 金属氧化物半导体晶体管 30 栅极结构
32 间隙壁 34 源极/漏极区域
36 硅化金属层 38 栅极介电层
40 栅极电极 42 接触洞蚀刻停止层
44 层间介电层 46 接触插塞
48 金属间介电层 50 金属内连线
52 掩模层 54 第一开口
56 衬垫层 58 间隙壁
60 气孔 62 第二开口
64 金属间介电层 66 气孔
68 气孔 70 气孔
具体实施方式
请参照图1至图7，图1至图7为本发明一实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅覆绝缘(silicon-on-insulator,SOI)基底，其主要包含一第一半导体层14、一绝缘层16设于第一半导体层14上以及一第二半导体层18设于绝缘层16上。更具体而言，第一半导体层14与第二半导体层18可包含相同或不同材料且可分别选自由硅、锗以及锗化硅所构成的群组，设置于第一半导体层14与第二半导体层18之间的绝缘层16较佳包含二氧化硅(SiO2)，但不局限于此。另外本实施例的第一半导体层14以及绝缘层16之间又可依据制作工艺需求另设置一陷阱层20，其中陷阱层20较佳为一具有高阻值(如阻值高于四千欧姆)的多晶硅层或一介电层。在本实施例中多晶硅层可包含含有氢掺质的多晶硅而介电层则可包含氧化硅或氮化硅。
然后可去除部分第二半导体层18，再形成一浅沟隔离(shallowtrenchisolation,STI)22环绕第二半导体层18，其中被浅沟隔离22所环绕的第二半导体层18较佳用来设置一主动元件。在本实施例中，浅沟隔离22可包含一由氮化硅所构成的衬垫层24以及一由氧化硅所构成的绝缘层26，其中衬垫层24较佳覆盖于绝缘层16上表面并环绕之后所形成的主动元件而绝缘层26则设于衬垫层24上。
接着形成一主动元件于基底12上。在本实施例中，所制备的主动元件较佳为一金属氧化物半导体晶体管28，其主要包含一栅极结构30、一间隙壁32设于栅极结构30侧壁、一源极/漏极区域34设于间隙壁32两侧的第二半导体层18内以及一选择性硅化金属层36设于源极/漏极区域34表面。
在本实施例中，栅极结构30又细部包含一栅极介电层38以及一栅极材料层或栅极电极40设于栅极介电层38上，其中栅极介电层38可包含二氧化硅、氮化硅或高介电常数(high dielectric constant,high-k)材料而栅极电极40可包含金属材料、多晶硅或金属硅化物(silicide)等导电材料。
本实施例的间隙壁32较佳为单一间隙壁，其可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。除此之外，依据本发明一实施例，间隙壁32又可依据制作工艺需求为一复合式间隙壁，例如又可细部包含一第一子间隙壁(图未示)与第二子间隙壁(图未示)，第一子间隙壁与第二子间隙壁的其中一者的剖面可呈现L型或I型，第一子间隙壁与第二子间隙壁可包含相同或不同材料，且两者均可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，这些实施例均属本发明所涵盖的范围。
接着先形成一选择性接触洞蚀刻停止层42覆盖栅极结构30表面，再形成一层间介电层44于接触洞蚀刻停止层42上。之后可进行一图案转移制作工艺，例如可利用一图案化掩模去除栅极结构30旁的部分的层间介电层44以及部分接触洞蚀刻停止层42以形成多个接触洞(图未示)并暴露出下面的源极/漏极区域34。然后再于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。接着进行一平坦化制作工艺，例如以化学机械研磨制作工艺去除部分金属材料以形成接触插塞46于各接触洞内电连接源极/漏极区域48。之后可进行后续金属内连线制作工艺以于层间介电层44上形成金属间介电层48以及金属内连线50分别连接各接触插塞46。
如图2所示，随后形成一掩模层52于金属间介电层48上，再利用一图案化掩模(图未示)为掩模去除部分掩模层52、部分金属间介电层48、部分层间介电层44、部分接触洞蚀刻停止层42以及部分浅沟隔离22以形成第一开口54暴露出金属氧化物半导体晶体管28两侧的绝缘层表面16。值得注意的是，本阶段利用蚀刻制作工艺所形成的第一开口54较佳暴露出绝缘层16表面但不贯穿绝缘层16并暴露出下方的陷阱层20表面，其中所形成的第一开口54底部可约略切齐或略低绝缘层16上表面。
接着如图3所示，先形成一衬垫层56于掩模层52上以及第一开口54内，再利用蚀刻去除部分衬垫层56形成一间隙壁58于第一开口54侧壁。在本实施例中，掩模层52与衬垫层56可包含相同或不同材料，例如两者均可依据产品需求由氮化硅或氮碳化硅所构成。另外需注意的是，由于形成衬垫层56之前金属间介电层48上表面已设有一掩模层52，因此在形成衬垫层56后金属间介电层48上表面较佳设有掩模层52以及衬垫层56而金属间介电层48侧壁则仅有衬垫层56。
如图4所示，然后进行一湿蚀刻制作工艺经由第一开口54去除部分绝缘层16甚至部分衬垫层56以形成一气孔60于金属氧化物半导体晶体管28下方。在本实施例中，湿蚀刻制作工艺所使用的蚀刻剂可包含稀释氢氟酸(diluted hydrofluoric acid,dHF)或氢氟酸，但不局限于此。另外需注意的是，由于浅沟隔离22如前所述较佳包含一由氮化硅所构成的衬垫层24设于由氧化硅所构成的绝缘层26与下方的绝缘层16之间，因此本实施例利用湿蚀刻制作工艺去除部分绝缘层16形成气孔60的时候可同时利用衬垫层24作为阻隔，由此保护上方的绝缘层26不致在湿蚀刻制作工艺也被一同去除。
随后如图5所示，先形成一图案化掩模(图未示)于金属间介电层48上方并暴露出位于栅极结构30正上方的部分衬垫层56，然后利用图案化掩模为掩模去除部分衬垫层56、部分掩模层52以及栅极结构30正上方的部分金属间介电层48以形成一第二开口62。之后再去除图案化掩模。值得注意的是，本阶段利用蚀刻形成第二开口62时较佳仅去除部分金属间介电层48甚至部分层间介电层44但不去除任何接触动蚀刻停止层42，因此所形成的第二开口62底部可选择略低于、切齐或略高于层间介电层44上表面。
如图6所示，接着进行另一湿蚀刻制作工艺，利用例如磷酸完全去除间隙壁58以及剩余的掩模层52并暴露出金属间介电层48上表面、金属间介电层48侧壁、层间介电层44侧壁以及浅沟隔离22侧壁。
然后如图7所示，形成另一金属间介电层64于金属间介电层48上并密封第一开口54以及第二开口62以于金属氧化物半导体晶体管28正上方形成另一气孔66并同时于金属氧化物半导体晶体管两侧形成气孔68。更具体而言，本实施例原本第二开口62的位置较佳于金属间介电层64密封后形成气孔66，而原本第一开口54的位置则形成气孔68，其中气孔66与气孔68顶部较佳经由密封后形成倒V形，而设于金属氧化物半导体晶体管28底部的气孔60则较佳连接气孔68并一同构成形成新的气孔70且气孔70较佳环绕整个金属氧化物半导体晶体管28呈现U形。
请再参照图7，图7另揭露本发明一实施例的一半导体元件的结构示意图。如图7所示，本发明的半导体元件较佳包含一金属氧化物半导体晶体管28设于基底12上，层间介电层44设于金属氧化物半导体晶体管28上，金属间介电层48设于层间介电层44上，气孔66设于金属氧化物半导体晶体管28的栅极结构30正上方的层间介电层44及金属间介电层48内以及气孔70设于金属氧化物半导体晶体管28下方，包括栅极结构28以及源极/漏极区域34下方的绝缘层16内并沿着金属氧化物半导体晶体管28两侧向上延伸至层间介电层44以及金属间介电层48、64内构成约略U形。在本实施例中，设于金属氧化物半导体晶体管28两侧的气孔68顶部与栅极结构30正上方的气孔66顶部较佳呈现约略倒V形，且气孔68顶部的倒V形顶点又较佳切齐气孔66顶部的倒V形顶点。另外以气孔68的高度而言，设于金属氧化物半导体晶体管28两侧的气孔68顶部较佳高于金属氧化物半导体晶体管28的栅极结构30顶部以及栅极结构30两侧的接触插塞46及金属内连线50顶部。
综上所述，本发明主要先形成一主动元件于一SOI基底上，然后于主动元件上形成层间介电层以及金属间介电层，再利用蚀刻去除主动元件两侧的部分金属间介电层、部分层间介电层以及主动元件下方SOI基底的绝缘层以及主动元件正上方的部分层间介电层与部分金属间介电层，最后再覆盖另一金属间介电层以于主动元件下方及两侧形成约略U形的气孔并同时于主动元件正上方形成另一气孔。通过气孔的设置本发明可由此降低整个元件的电容值。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种制作半导体元件的方法，其特征在于，包含：
提供一基底，该基底包含第一半导体层、绝缘层设于该第一半导体层上以及第二半导体层设于该绝缘层上；
形成一金属氧化物半导体晶体管于该基底上；
形成一层间介电层于该金属氧化物半导体晶体管上；
去除部分该层间介电层以形成一第一开口暴露出该绝缘层；以及
进行一第一湿蚀刻制作工艺经由该第一开口去除部分该绝缘层以形成一第一气孔于该金属氧化物半导体晶体管下方。
2.如权利要求1所述的方法，另包含：
形成一浅沟隔离于该第二半导体层内并环绕该金属氧化物半导体晶体管；
形成一接触插塞于该金属氧化物半导体晶体管旁并位于该层间介电层内；以及
形成一第一金属间介电层于该接触插塞上。
3.如权利要求2所述的方法，另包含：
形成一掩模层于该第一金属间介电层上；
去除部分该掩模层、部分该第一金属间介电层、部分该层间介电层以及部分该浅沟隔离并暴露出该绝缘层；
形成一衬垫层于该掩模层上以及该第一开口内；以及
去除部分该衬垫层以形成一间隙壁于该第一开口侧壁。
4.如权利要求3所述的方法，另包含：
去除部分该掩模层以及部分该金属氧化物半导体晶体管正上方的部分该第一金属间介电层以形成一第二开口；
进行一第二湿蚀刻制作工艺去除该间隙壁以及部分该掩模层；以及
形成一第二金属间介电层于该第一金属间介电层上密封该第一开口以及该第二开口以于该金属氧化物半导体晶体管正上方形成第二气孔以及于该金属氧化物半导体晶体管两侧形成第三气孔。
5.如权利要求4所述的方法，其中该第一气孔连接该第三气孔并一同构成U形。
6.如权利要求4所述的方法，其中该第二气孔上表面切齐该第三气孔上表面。
7.如权利要求4所述的方法，其中该第三气孔顶部包含V形。
8.如权利要求1所述的方法，另包含陷阱层设于该绝缘层以及该第一半导体层之间。
9.如权利要求8所述的方法，其中该陷阱层包含多晶硅层或介电层。
10.一种半导体元件，其特征在于，包含：
基底，该基底包含第一半导体层、绝缘层设于该第一半导体层上以及第二半导体层设于该绝缘层上；
金属氧化物半导体晶体管，设于该基底上；以及
第一气孔，设于该绝缘层内并设于该金属氧化物半导体晶体管正下方。
11.如权利要求10所述的半导体元件，其中该金属氧化物半导体晶体管包含：
栅极结构，设于该基底上；以及
源极/漏极区域，设于该栅极结构两侧的该第二半导体层内。
12.如权利要求11所述的半导体元件，其中该第一气孔设于该栅极结构以及该源极/漏极区域下方。
13.如权利要求11所述的半导体元件，另包含：
层间介电层，设于该金属氧化物半导体晶体管上；
金属间介电层，设于该层间介电层上；以及
第二气孔，设于该金属间介电层内并设于该栅极结构正上方。
14.如权利要求10所述的半导体元件，另包含陷阱层，设于该绝缘层以及该第一半导体层之间。
15.如权利要求14所述的半导体元件，其中该陷阱层包含多晶硅层或介电层。
16.一种半导体元件，其特征在于，包含：
基底，该基底包含第一半导体层、绝缘层设于该第一半导体层上以及第二半导体层设于该绝缘层上；
金属氧化物半导体晶体管，设于该基底上；
层间介电层，设于该金属氧化物半导体晶体管上；以及
第一气孔，设于该绝缘层内以及该金属氧化物半导体晶体管下方并向上延伸至该层间介电层内，其中该第一气孔包含U形。
17.如权利要求16所述的半导体元件，另包含：
金属间介电层，设于该层间介电层上；以及
第二气孔，设于该金属间介电层内并设于该栅极结构正上方。
18.如权利要求17所述的半导体元件，其中该第二气孔上表面切齐该第一气孔上表面。
19.如权利要求16所述的半导体元件，另包含陷阱层，设于该绝缘层以及该第一半导体层之间。
20.如权利要求19所述的半导体元件，其中该陷阱层包含多晶硅层或介电层。
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