US20200027985A1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- US20200027985A1 US20200027985A1 US16/109,714 US201816109714A US2020027985A1 US 20200027985 A1 US20200027985 A1 US 20200027985A1 US 201816109714 A US201816109714 A US 201816109714A US 2020027985 A1 US2020027985 A1 US 2020027985A1
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- layer
- mos transistor
- air gap
- insulating layer
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000010410 layer Substances 0.000 claims abstract description 188
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000001039 wet etching Methods 0.000 claims abstract description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 7
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 238000005530 etching Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- JPNWDVUTVSTKMV-UHFFFAOYSA-N cobalt tungsten Chemical compound [Co].[W] JPNWDVUTVSTKMV-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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Definitions
- the invention relates to a method for fabricating semiconductor device, and more particularly to a method of forming air gap under active device for reducing capacitance of the device.
- a method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.
- MOS metal-oxide semiconductor
- ILD interlayer dielectric layer
- a semiconductor device includes: a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; a metal-oxide semiconductor (MOS) transistor on the substrate; and a first air gap in the insulating layer and directly under the MOS transistor.
- MOS metal-oxide semiconductor
- a semiconductor device includes: a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; a metal-oxide semiconductor (MOS) transistor on the substrate; an interlayer dielectric (ILD) layer on the MOS transistor; and a first air gap under the MOS transistor and extended upward into the ILD layer, wherein the first air gap comprises a U-shape.
- MOS metal-oxide semiconductor
- ILD interlayer dielectric
- FIGS. 1-7 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention.
- FIGS. 1-7 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention.
- a substrate 12 such as a silicon-on-insulator (SOI) substrate is provided, in which the substrate 12 preferably includes a first semiconductor layer 14 , an insulating layer 16 on the first semiconductor layer 14 , and a second semiconductor layer 18 on the insulating layer 16 .
- the first semiconductor layer 14 and the second semiconductor layer 18 could be made of same material or different material and could both be made of material including but not limited to for example silicon, germanium, or silicon germanium (SiGe).
- the insulating layer 16 disposed between the first semiconductor layer 14 and the second semiconductor layer 18 preferably includes SiO 2 , but not limited thereto.
- an additional trap rich layer 20 is disposed between the first semiconductor layer 14 and the insulating layer 16 depending on the demand of the process, in which the trap rich layer 20 preferably includes a polysilicon layer or a dielectric layer having high resistance (such as having a resistance greater than 4000 Ohms).
- the polysilicon layer could be a polysilicon layer doped with hydrogen and the dielectric layer could be made of silicon oxide or silicon nitride.
- the STI 22 preferably includes a liner 24 made of silicon nitride (SiN) and an insulating layer 26 made of silicon oxide, in which the liner 24 is disposed on the top surface of the insulating layer 16 and surrounding the active device formed afterwards and the insulating layer 26 is disposed on the liner 24 .
- the active device is preferably a MOS transistor 28 , which preferably includes a gate structure 30 , a spacer 32 on sidewalls of the gate structure 30 , a source/drain region 34 in the second semiconductor layer 18 adjacent to two sides of the spacer 32 , and a selective silicide 36 on the surface of the source/drain region 34 .
- MOS transistor 28 which preferably includes a gate structure 30 , a spacer 32 on sidewalls of the gate structure 30 , a source/drain region 34 in the second semiconductor layer 18 adjacent to two sides of the spacer 32 , and a selective silicide 36 on the surface of the source/drain region 34 .
- the gate structure 30 further includes a gate dielectric layer 38 and a gate material layer or gate electrode 40 on the gate dielectric layer 38 , in which the gate dielectric layer 38 could include SiO 2 , silicon nitride, or high-k dielectric layer and the gate electrode 40 could include metal, polysilicon, or silicides.
- the spacer 32 could be a single spacer made of material including but not limited to for example SiO 2 , SiN, SiON, SiCN, or combination thereof. Nevertheless, according to an embodiment of the present invention, the spacer 32 could also be a composite spacer including a first sub-spacer (not shown) and a second sub-spacer (not shown), in which one of the first sub-spacer and the second sub-spacer could be L-shaped or I-shaped, the first sub-spacer and the second sub-spacer could be made of same material or different material, and both the first sub-spacer and the second sub-spacer could be made of material including but not limited to for example SiO 2 , SiN, SiON, SiCN, or combination thereof, which are all within the scope of the present invention.
- a selective contact etch stop layer (CESL) 42 preferably made of silicon nitride could be formed on the substrate 12 to cover the gate structure 30 and an ILD layer 44 is formed on the CESL 42 .
- a pattern transfer process could be conducted by using a patterned mask to remove part of the ILD layer 44 and part of the CESL 42 adjacent to the gate structure 30 to form contact holes (not shown) exposing the source/drain region 34 underneath.
- metals including a barrier layer selected from the group consisting of Ti, Ta, TiN, TaN, and WN and a metal layer selected from the group consisting of W, Cu, Al, TiAl, and cobalt tungsten phosphide (CoWP) could be deposited into each of the contact holes.
- aplanarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the metal materials to form contact holes 46 in the contact holes for electrically connecting the source/drain region 48 .
- CMP chemical mechanical polishing
- metal-interconnect process could be conducted to form an inter-metal dielectric (IMD) layer 48 on the ILD layer 44 and metal interconnections 50 electrically connecting the contact plugs 46 .
- IMD inter-metal dielectric
- a mask layer 52 is formed on the IMD layer 48 , and a patterned mask (not shown) is used as mask to remove part of the mask layer 52 , part of the IMD layer 48 , part of the ILD layer 44 , part of the CESL 42 and part of the STI 22 to form first trenches 54 exposing the surface of the insulating layer 16 adjacent to two sides of the MOS transistor 28 .
- first trenches 54 formed through the etching process are preferably formed to expose the surface of the insulating layer 16 but does not penetrate through the insulating layer 16 and expose the trap rich layer 20 underneath, in which the bottom of the first trenches 54 could be even with or slightly lower than the top surface of the insulating layer 16 .
- a liner 56 is formed on the mask layer 52 and into the first trenches 54 , and an etching process is conducted to remove part of the liner 56 to form a spacer 58 on sidewalls of the first trenches 54 .
- the mask layer 52 and the liner 56 could be made of same material or different material while both layers 52 and 56 could be selected from the group consisting of SiN and SiCN.
- a mask layer 52 and a liner 56 are preferably disposed on the top surface of the IMD layer 48 after forming the liner 56 while only a liner 56 is disposed on sidewalls of the IMD layer 48 .
- a wet etching process is conducted to remove part of the insulating layer 16 and even part of the liner 56 through the first trenches 54 to form an air gap 60 under the MOS transistor 28 .
- etchant from the wet etching process could include but not limited to for example dilute hydrofluoric acid (dHF) or HF.
- the STI 22 preferably includes a liner 34 made of SiN between the insulating layer 26 made of the silicon oxide and the insulating layer 16 underneath, it would be desirable to use the liner 34 as a protective barrier to prevent loss of the insulating layer 26 when the wet etching process were conducted to remove part of the insulating layer 16 for forming the air gap 60 .
- apatterned mask (not shown) is formed on the IMD layer 48 to expose part of the liner 56 directly above the gate structure 30 , and an etching process is conducted by using the patterned mask as mask to remove part of the liner 56 , part of the mask layer 52 , and part of the IMD layer 48 directly on top of the gate structure 30 to form a second trench 62 , and the patterned mask is stripped thereafter.
- the etching process conducted to form the second trench 62 preferably removes part of the IMD layer 48 and even part of the ILD layer 44 but does not remove any of the CESL 42 so that the bottom of the second trench 62 could be slightly lower than, even with, or slightly higher than the top surface of the ILD layer, which are all within the scope of the present invention.
- etchant such as phosphoric acid to completely remove the spacer 58 and the remaining mask layer 52 to expose the top surface of the IMD layer 48 , sidewalls of the IMD layer 48 , sidewalls of the ILD layer 44 , and sidewalls of the STI 22 .
- another IMD layer 64 is formed on the IMD layer 48 to seal the first trenches 54 and the second trench 62 for forming another air gap 66 directly on top of the MOS transistor 28 and at the same time forming air gaps 68 adjacent to two sides of the MOS transistor 28 .
- the original second trench 62 is preferably sealed by the IMD layer 64 to form the air gap 66 while the original first trenches 54 are sealed to form air gaps 68 , in which the tip or topmost portion of each of the air gaps 66 and 68 preferably forms a reverse V-shape after the trenches 54 , 62 are sealed by the IMD layer 64 and the air gap 60 under the MOS transistor 28 is connected to the air gaps 68 to form a new air gap 70 altogether.
- the newly formed air gap 70 preferably surrounds the entire MOS transistor 28 and has a U-shape cross-section.
- FIG. 7 illustrates a structural view of a semiconductor device according to an embodiment of the present invention.
- the semiconductor device preferably includes an active device such as a MOS transistor 28 disposed on the substrate 12 , an ILD layer 44 disposed on the MOS transistor 28 , an IMD layer 48 disposed on the ILD layer 44 , an air gap 66 disposed in the ILD layer 44 and IMD layer 48 directly on top of the gate structure 30 of the MOS transistor 28 , and air gap 70 disposed under the MOS transistor 28 .
- an active device such as a MOS transistor 28 disposed on the substrate 12
- an ILD layer 44 disposed on the MOS transistor 28
- an IMD layer 48 disposed on the ILD layer 44
- an air gap 66 disposed in the ILD layer 44 and IMD layer 48 directly on top of the gate structure 30 of the MOS transistor 28
- air gap 70 disposed under the MOS transistor 28 .
- the air gap 70 is disposed in the insulating layer 16 under the gate structure 28 and source/drain region 34 and extending along two sides of the MOS transistor 28 upward into the ILD layer 44 and IMD layers 48 , 64 to form a U-shape.
- the tip of the air gaps 68 adjacent to two sides of the MOS transistor 28 and the tip of the air gap 66 directly on top of the gate structure 30 preferably include a reverse V-shape and the tip or topmost point of the reverse V-shape of the air gaps 68 is also substantially even with the tip or topmost point of the reverse V-shape of the air gap 66 .
- the tip or topmost point of the air gaps 68 adjacent to two sides of the MOS transistor 28 is preferably higher than the top surfaces of the gate structure 30 and the contact plugs 46 and metal interconnections 50 adjacent to two sides of the gate structure 30 .
- the present invention first forms an active device on a SOI substrate, forms an ILD layer and IMD layer on the active device, performs one or more etching processes to remove part of the IMD layer, part of the ILD layer, part of the insulating layer of the SOI substrate under the active device and part of the ILD layer and part of IMD layer directly above the active device, and then covers another IMD layer to form a U-shaped air gap under the active device and adjacent to two sides of the active device and at the same times forms another air gap directly on top of the active device.
- the formation of the air gaps could be used to lower the capacitance of the device substantially.
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Abstract
Description
- The invention relates to a method for fabricating semiconductor device, and more particularly to a method of forming air gap under active device for reducing capacitance of the device.
- In radio frequency (RF) integrated circuit application, such as RF switch device or power amplifier device, performance is suffered from “parasitic surface charge” issue, which in turn generates harmonic effect. There are several wafer process technologies available for solving the issue such as using semiconductor-on-insulator (SOI) wafer to isolate the charges from the high resistivity wafer substrate. However, the utilization of SOI wafer or substrate in current process usually results in higher cost. Hence how to improve the performance of current process while finding a more effective way to lower cost has become an important task in this field.
- According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.
- According to another aspect of the present invention, a semiconductor device includes: a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; a metal-oxide semiconductor (MOS) transistor on the substrate; and a first air gap in the insulating layer and directly under the MOS transistor.
- According to yet another aspect of the present invention, a semiconductor device includes: a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; a metal-oxide semiconductor (MOS) transistor on the substrate; an interlayer dielectric (ILD) layer on the MOS transistor; and a first air gap under the MOS transistor and extended upward into the ILD layer, wherein the first air gap comprises a U-shape.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIGS. 1-7 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. - Referring to
FIGS. 1-7 ,FIGS. 1-7 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown inFIG. 1 , asubstrate 12, such as a silicon-on-insulator (SOI) substrate is provided, in which thesubstrate 12 preferably includes afirst semiconductor layer 14, aninsulating layer 16 on thefirst semiconductor layer 14, and asecond semiconductor layer 18 on theinsulating layer 16. Preferably, thefirst semiconductor layer 14 and thesecond semiconductor layer 18 could be made of same material or different material and could both be made of material including but not limited to for example silicon, germanium, or silicon germanium (SiGe). Theinsulating layer 16 disposed between thefirst semiconductor layer 14 and thesecond semiconductor layer 18 preferably includes SiO2, but not limited thereto. Preferably, an additional traprich layer 20 is disposed between thefirst semiconductor layer 14 and theinsulating layer 16 depending on the demand of the process, in which the traprich layer 20 preferably includes a polysilicon layer or a dielectric layer having high resistance (such as having a resistance greater than 4000 Ohms). In this embodiment, the polysilicon layer could be a polysilicon layer doped with hydrogen and the dielectric layer could be made of silicon oxide or silicon nitride. - Next, as part of the
second semiconductor layer 18 could be removed to form a shallow trench isolation (STI) 22 around thesecond semiconductor layer 18, in which an active device is preferably formed on thesecond semiconductor layer 18 surrounded by theSTI 22. In this embodiment, theSTI 22 preferably includes aliner 24 made of silicon nitride (SiN) and aninsulating layer 26 made of silicon oxide, in which theliner 24 is disposed on the top surface of theinsulating layer 16 and surrounding the active device formed afterwards and theinsulating layer 26 is disposed on theliner 24. - Next, an active device is formed on the
substrate 12. In this embodiment, the active device is preferably aMOS transistor 28, which preferably includes agate structure 30, aspacer 32 on sidewalls of thegate structure 30, a source/drain region 34 in thesecond semiconductor layer 18 adjacent to two sides of thespacer 32, and aselective silicide 36 on the surface of the source/drain region 34. - In this embodiment, the
gate structure 30 further includes a gatedielectric layer 38 and a gate material layer orgate electrode 40 on the gatedielectric layer 38, in which the gatedielectric layer 38 could include SiO2, silicon nitride, or high-k dielectric layer and thegate electrode 40 could include metal, polysilicon, or silicides. - The
spacer 32 could be a single spacer made of material including but not limited to for example SiO2, SiN, SiON, SiCN, or combination thereof. Nevertheless, according to an embodiment of the present invention, thespacer 32 could also be a composite spacer including a first sub-spacer (not shown) and a second sub-spacer (not shown), in which one of the first sub-spacer and the second sub-spacer could be L-shaped or I-shaped, the first sub-spacer and the second sub-spacer could be made of same material or different material, and both the first sub-spacer and the second sub-spacer could be made of material including but not limited to for example SiO2, SiN, SiON, SiCN, or combination thereof, which are all within the scope of the present invention. - Next, a selective contact etch stop layer (CESL) 42 preferably made of silicon nitride could be formed on the
substrate 12 to cover thegate structure 30 and anILD layer 44 is formed on theCESL 42. Next, a pattern transfer process could be conducted by using a patterned mask to remove part of theILD layer 44 and part of theCESL 42 adjacent to thegate structure 30 to form contact holes (not shown) exposing the source/drain region 34 underneath. Next, metals including a barrier layer selected from the group consisting of Ti, Ta, TiN, TaN, and WN and a metal layer selected from the group consisting of W, Cu, Al, TiAl, and cobalt tungsten phosphide (CoWP) could be deposited into each of the contact holes. Next, aplanarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the metal materials to formcontact holes 46 in the contact holes for electrically connecting the source/drain region 48. Next, metal-interconnect process could be conducted to form an inter-metal dielectric (IMD)layer 48 on theILD layer 44 andmetal interconnections 50 electrically connecting thecontact plugs 46. - Next, as shown in
FIG. 2 , amask layer 52 is formed on theIMD layer 48, and a patterned mask (not shown) is used as mask to remove part of themask layer 52, part of theIMD layer 48, part of theILD layer 44, part of theCESL 42 and part of theSTI 22 to formfirst trenches 54 exposing the surface of theinsulating layer 16 adjacent to two sides of theMOS transistor 28. It should be noted that thefirst trenches 54 formed through the etching process are preferably formed to expose the surface of theinsulating layer 16 but does not penetrate through theinsulating layer 16 and expose the traprich layer 20 underneath, in which the bottom of thefirst trenches 54 could be even with or slightly lower than the top surface of theinsulating layer 16. - Next, as shown in
FIG. 3 , aliner 56 is formed on themask layer 52 and into thefirst trenches 54, and an etching process is conducted to remove part of theliner 56 to form aspacer 58 on sidewalls of thefirst trenches 54. In this embodiment, themask layer 52 and theliner 56 could be made of same material or different material while bothlayers mask layer 52 was already disposed on theIMD layer 48 before forming theliner 56, amask layer 52 and aliner 56 are preferably disposed on the top surface of theIMD layer 48 after forming theliner 56 while only aliner 56 is disposed on sidewalls of theIMD layer 48. - Next, as shown in
FIG. 4 , a wet etching process is conducted to remove part of theinsulating layer 16 and even part of theliner 56 through thefirst trenches 54 to form anair gap 60 under theMOS transistor 28. In this embodiment, etchant from the wet etching process could include but not limited to for example dilute hydrofluoric acid (dHF) or HF. Moreover, it should be noted that since theSTI 22 preferably includes aliner 34 made of SiN between the insulatinglayer 26 made of the silicon oxide and theinsulating layer 16 underneath, it would be desirable to use theliner 34 as a protective barrier to prevent loss of theinsulating layer 26 when the wet etching process were conducted to remove part of theinsulating layer 16 for forming theair gap 60. - Next, as shown in
FIG. 5 , apatterned mask (not shown) is formed on theIMD layer 48 to expose part of theliner 56 directly above thegate structure 30, and an etching process is conducted by using the patterned mask as mask to remove part of theliner 56, part of themask layer 52, and part of theIMD layer 48 directly on top of thegate structure 30 to form asecond trench 62, and the patterned mask is stripped thereafter. It should be noted that the etching process conducted to form thesecond trench 62 preferably removes part of theIMD layer 48 and even part of theILD layer 44 but does not remove any of theCESL 42 so that the bottom of thesecond trench 62 could be slightly lower than, even with, or slightly higher than the top surface of the ILD layer, which are all within the scope of the present invention. - Next, as shown in
FIG. 6 , another wet etching process is conducted by using etchant such as phosphoric acid to completely remove thespacer 58 and theremaining mask layer 52 to expose the top surface of theIMD layer 48, sidewalls of theIMD layer 48, sidewalls of theILD layer 44, and sidewalls of theSTI 22. - Next, as shown in
FIG. 7 , anotherIMD layer 64 is formed on theIMD layer 48 to seal thefirst trenches 54 and thesecond trench 62 for forming anotherair gap 66 directly on top of theMOS transistor 28 and at the same time formingair gaps 68 adjacent to two sides of theMOS transistor 28. Specifically, the originalsecond trench 62 is preferably sealed by theIMD layer 64 to form theair gap 66 while the originalfirst trenches 54 are sealed to formair gaps 68, in which the tip or topmost portion of each of theair gaps trenches IMD layer 64 and theair gap 60 under theMOS transistor 28 is connected to theair gaps 68 to form anew air gap 70 altogether. The newly formedair gap 70 preferably surrounds theentire MOS transistor 28 and has a U-shape cross-section. - Referring again to
FIG. 7 ,FIG. 7 illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG. 7 , the semiconductor device preferably includes an active device such as aMOS transistor 28 disposed on thesubstrate 12, anILD layer 44 disposed on theMOS transistor 28, anIMD layer 48 disposed on theILD layer 44, anair gap 66 disposed in theILD layer 44 andIMD layer 48 directly on top of thegate structure 30 of theMOS transistor 28, andair gap 70 disposed under theMOS transistor 28. Preferably, theair gap 70 is disposed in theinsulating layer 16 under thegate structure 28 and source/drain region 34 and extending along two sides of theMOS transistor 28 upward into theILD layer 44 andIMD layers air gaps 68 adjacent to two sides of theMOS transistor 28 and the tip of theair gap 66 directly on top of thegate structure 30 preferably include a reverse V-shape and the tip or topmost point of the reverse V-shape of theair gaps 68 is also substantially even with the tip or topmost point of the reverse V-shape of theair gap 66. Moreover, the tip or topmost point of theair gaps 68 adjacent to two sides of theMOS transistor 28 is preferably higher than the top surfaces of thegate structure 30 and thecontact plugs 46 andmetal interconnections 50 adjacent to two sides of thegate structure 30. - Overall, the present invention first forms an active device on a SOI substrate, forms an ILD layer and IMD layer on the active device, performs one or more etching processes to remove part of the IMD layer, part of the ILD layer, part of the insulating layer of the SOI substrate under the active device and part of the ILD layer and part of IMD layer directly above the active device, and then covers another IMD layer to form a U-shaped air gap under the active device and adjacent to two sides of the active device and at the same times forms another air gap directly on top of the active device. Preferably, the formation of the air gaps could be used to lower the capacitance of the device substantially.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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