TWI727068B - 半導體裝置以及其製作方法 - Google Patents

半導體裝置以及其製作方法 Download PDF

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TWI727068B
TWI727068B TW106122208A TW106122208A TWI727068B TW I727068 B TWI727068 B TW I727068B TW 106122208 A TW106122208 A TW 106122208A TW 106122208 A TW106122208 A TW 106122208A TW I727068 B TWI727068 B TW I727068B
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Taiwan
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gate
uppermost surface
metal gate
layer
semiconductor device
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TW106122208A
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English (en)
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TW201907452A (zh
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吳彥良
張文聰
楊瑞銘
張翊凡
江俊霆
林智偉
蘇柏羽
李季儒
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聯華電子股份有限公司
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Priority to TW106122208A priority Critical patent/TWI727068B/zh
Priority to US15/665,397 priority patent/US10062764B1/en
Priority to US16/043,120 priority patent/US10388749B2/en
Publication of TW201907452A publication Critical patent/TW201907452A/zh
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

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Abstract

一種半導體裝置包括一基底、一閘極結構、一間隙子、一遮罩層以及至少一空隙。閘極結構設置於基底上，且閘極結構包括一金屬閘極。間隙子設置於閘極結構之側壁上，且間隙子之最上表面係高於金屬閘極之最上表面。遮罩層設置於閘極結構上。空隙設置於遮罩層中且設置於金屬閘極與間隙子之間。

Description

半導體裝置以及其製作方法
本發明係關於一種半導體裝置以及其製作方法，尤指一種具有空隙(void)之半導體裝置以及其製作方法。
半導體積體電路之技術隨著時間不斷地進步成長，每個新世代製程下的產品都較前一個世代具有更小且更複雜的電路設計。在各晶片區域上的功能元件因產品革新需求而必須使其數量與密度不斷地提升，當然也就使得各元件幾何尺寸需越來越小。舉例來說，在場效電晶體(field effect transistor，FET)中，閘極線之間的間距需變得越來越小以提升積體電路的積集度。然而，由於微影製程(photolithography process)的曝光極限限制，在閘極線之間的空間變得極小的狀態下並不易形成對應源極/汲極結構之接觸結構，且在此狀況下形成之接觸結構與閘極線之間的距離亦非常狹小，容易造成互相干擾以及電性上的不良影響。
本發明提供了一種半導體裝置以及其製作方法，利用於閘極結構上之遮罩層中形成位於金屬閘極與間隙子之間的空隙，藉此提升源極/汲極結構對 應之接觸結構與閘極結構之間的隔離效果。
根據本發明之一實施例，本發明提供了一種半導體裝置，包括一基底、一閘極結構、一間隙子、一遮罩層以及至少一空隙。閘極結構設置於基底上，且閘極結構包括一金屬閘極。間隙子設置於閘極結構之側壁上，且間隙子之最上表面係高於金屬閘極之最上表面。遮罩層設置於閘極結構上。空隙設置於遮罩層中且設置於金屬閘極與間隙子之間。
根據本發明之一實施例，本發明還提供了一種半導體裝置的製作方法，包括下列步驟。首先，於一基底上形成一閘極結構。閘極結構係形成於被一間隙子圍繞之一溝槽中。閘極結構包括一金屬閘極，且間隙子之最上表面係高於金屬閘極之最上表面。然後，於溝槽中以及閘極結構上形成一遮罩層，至少一空隙係形成於位於溝槽中的遮罩層中，且空隙係形成於金屬閘極與間隙子之間。
10:基底
11:半導體結構
20:間隙子
20S:第一最上表面
30:源極/汲極結構
41:蝕刻停止層
41S:第二最上表面
42:介電層
50:閘極結構
51:閘極介電層
51S:第五最上表面
52:功函數層
52S:第四最上表面
53:金屬閘極
53S:第三最上表面
60:絕緣材料
60A:空隙
60M:遮罩層
71:層間介電層
72:接觸結構
91:回蝕刻製程
92:移除製程
100:半導體裝置
D1:第一方向
D2:第二方向
D3:第三方向
TR:溝槽
第1圖至第6圖所繪示為本發明一實施例之半導體裝置的製作方法示意圖，其中第2圖繪示了第1圖之後的製作方法示意圖；第3圖繪示了第2圖之後的製作方法示意圖；第4圖繪示了第3圖之後的製作方法示意圖；第5圖繪示了第4圖之後的製作方法示意圖；第6圖繪示了第5圖之後的製作方法示意圖。
第6圖所繪示為本發明一實施例之半導體裝置的示意圖。
請參閱第1圖至第6圖。第1圖至第6圖所繪示為本發明一實施例之半導體裝置的製作方法示意圖，而第6圖所繪示為本實施例之半導體裝置的示意圖。本實施例之半導體裝置的製作方法包括下列步驟。如第1圖與第2圖所示，於一基底10上形成一閘極結構50。閘極結構50係形成於被一間隙子20圍繞之一溝槽TR中。在一些實施例中，一半導體結構11可先形成於基底10上。基底10可包括矽基底、磊晶矽基底、矽鍺基底、碳化矽基底或絕緣層覆矽(silicon-on-insulator，SOI)基底，但並不以此為限。半導體結構11可為半導體層、半導體鰭狀結構或其它適合之半導體結構。在一些實施例中，複數個閘極結構50可形成於半導體結構11上，各閘極結構50可包括沿一第一方向D1延伸之閘極線，且各閘極結構50可彼此互相平行設置且沿一第二方向D2重複設置，而第一方向D1可大體上與第二方向D2正交，但並不以此為限。在一些實施例中，閘極結構50可藉由取代金屬閘極製程(replacement metal gate process)形成，但並不以此為限。舉例來說，複數個虛置閘極(未繪示)可先形成於半導體結構11上，然後再於虛置閘極的側壁上形成間隙子20，並藉由間隙子20當作遮罩於半導體結構11中形成複數個源極/汲極結構30。之後，形成蝕刻停止層41以及介電層42覆蓋虛置閘極以及源極/汲極結構30，並可藉由一平坦化製程例如化學機械研磨(chemical mechanical polishing，CMP)製程移除於垂直基底10的一第三方向D3上位於虛置閘極上的蝕刻停止層41與介電層42，藉此將虛置閘極暴露出以便將虛置閘極移除而形成溝槽TR。第三方向D3可被視為基底10的厚度方向，但並不以此為限。之後，可依序於溝槽TR中形成多層所需之材料層，並再搭配另一平坦化製程來移除位於溝槽TR之外的材料層而形成閘極結構50。在一些實施例中，間隙子20的材料可包括氮化矽(SiNx)、碳氮化矽(SiCN)、碳氧氮化矽 (silicon-carbon-oxy-nitride，SiCON)或其它適合之絕緣材料，蝕刻停止層41的材料可包括氮化矽(SiNx)或其它適合之絕緣材料，源極/汲極結構30可包括磊晶層、矽化物層、半導體結構11中之摻雜區或其它適合之源極/汲極結構型態。
接著，如第2圖至第3圖所示，對閘極結構50進行一回蝕刻製程91，用以對閘極結構50中的至少部分材料層進行蝕刻。舉例來說，在一些實施例中，各閘極結構50可包括一金屬閘極53以及一功函數層52，功函數層52可圍繞金屬閘極53。在一些實施例中，於回蝕刻製程91進行之前，間隙子20的最上表面(例如第2圖中所示之第一最上表面20S)、蝕刻停止層41的最上表面(例如第2圖中所示之第二最上表面41S)、金屬閘極53的最上表面(例如第2圖中所示之第三最上表面53S)以及功函數層52的最上表面(例如第2圖中所示之第四最上表面52S)可大體上於第三方向D3上等高，但並不以此為限。藉由調整回蝕刻製程91的蝕刻選擇比或/及利用多種不同的蝕刻步驟來進行回蝕刻製程91，可於回蝕刻製程91之後使得間隙子20的第一最上表面20S以及蝕刻停止層41的第二最上表面41S於第三方向D3上均高於金屬閘極53的第三最上表面53S，且功函數層52的第四最上表面52S於回蝕刻製程91之後係於第三方向D3上低於金屬閘極53的第三最上表面53S。
換句話說，回蝕刻製程91對於功函數層52的蝕刻率可高於對於金屬閘極53的蝕刻率，使得金屬閘極53被回蝕刻的程度低於功函數層52被回蝕刻的程度，藉此形成如第3圖所示之金屬閘極53高於功函數層52的狀況。更進一步說明，於溝槽TR中，功函數層52可於第三方向D3上部分位於金屬閘極53與基底10之間，且功函數層52可於水平方向(例如第一方向D1或/及第二方向D2)上圍繞金屬閘極53，故功函數層52可於一剖視圖中具有一U字形結構，但並不以此為限。 此外，由於在回蝕刻製程91進行之前，金屬閘極53的第三最上表面53S與功函數層52的第四最上表面52S可大體上於第三方向D3上等高，故於回蝕刻製程91之後，功函數層52的第四最上表面52S於第三方向D3上並未被金屬閘極53覆蓋。金屬閘極53可包括一低電阻金屬材料例如鋁(Al)、鎢(W)、銅(Cu)、鈦鋁合金(TiAl)或其他適合之低電阻金屬導電材料，而功函數層52可包括氮化鉭(tantalum nitride，TaN)、氮化鈦(titanium nitride，TiN)、碳化鈦(titanium carbide，TiC)、鋁鈦合金(titanium aluminide，TiAl)、碳化鈦鋁(titanium aluminum carbide，TiAlC)或其他適合之N型或/及P型功函數材料。
此外，如第2圖至第3圖所示，在一些實施例中，各閘極結構50可更括一閘極介電層51圍繞金屬閘極53。閘極介電層51可包括一高介電常數(high-k)介電層例如氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide，HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化鋁(aluminum oxide，Al2O3)、氧化鉭(tantalum oxide，Ta2O5)、氧化鋯(zirconium oxide，ZrO2)或其他適合之高介電常數材料。此外，在一些實施例中，亦可視需要於閘極介電層51與功函數層52之間形成一阻障層(未繪示)。於回蝕刻製程91進行之前，閘極介電層51的最上表面(例如第2圖中所示之第五最上表面51S)與金屬閘極53的第三最上表面53S可於第三方向D3上大體上等高，但並不以此為限。藉由調整回蝕刻製程91的蝕刻選擇比或/及利用多種不同的蝕刻步驟來進行回蝕刻製程91，可於回蝕刻製程91之後使得閘極介電層51之第五最上表面51S低於金屬閘極53之第三最上表面53S。
換句話說，回蝕刻製程91對於閘極介電層51的蝕刻率可高於對於金屬閘極53的蝕刻率，使得金屬閘極53被回蝕刻的程度低於閘極介電層51被回蝕 刻的程度，藉此形成如第3圖所示之金屬閘極53高於閘極介電層51的狀況。此外，由於在回蝕刻製程91進行之前，金屬閘極53的第三最上表面53S與閘極介電層51的第五最上表面51S可大體上於第三方向D3上等高，故於回蝕刻製程91之後，閘極介電層51的第五最上表面51S於第三方向D3上並未被金屬閘極53覆蓋。此外，於溝槽TR中，閘極介電層51可於第三方向D3上部分位於功函數層52與基底10之間，且閘極介電層51可於水平方向(例如第一方向D1或/及第二方向D2)上圍繞金屬閘極53與功函數層52，故閘極介電層51亦可於一剖視圖中具有一U字形結構，但並不以此為限。上述之閘極介電層51的形成方式可被視為一高介電常數後製(high-k last)製程，但並不以此為限。在本發明之另一些實施例中，亦可視需要採用高介電常數先製(high-k first)製程，而在此狀況下之閘極介電層則不具有U字形結構且亦不會於水平方向上圍繞金屬閘極53與功函數層52。
如第3圖至第5圖所示，於回蝕刻製程91之後，於溝槽TR中以及各閘極結構50上形成一遮罩層60M，且至少一空隙(void)60A係形成於位於溝槽TR中的遮罩層60M中，且空隙60A係於水平方向(例如第二方向D2)上形成於金屬閘極53與間隙子20之間。更進一步說明，在一些實施例中，遮罩層60M可藉由於溝槽TR中填入一絕緣材料60並搭配一移除製程92(例如另一個CMP製程)將位於溝槽TR之外的絕緣材料60移除而形成，但並不以此為限。藉由上述之回蝕刻製程使得功函數層52的第四最上表面52S或/及閘極介電層51的第五最上表面51S低於金屬閘極53之第三最上表面53S，可於溝槽TR中在金屬閘極53與間隙子20之間形成一較為窄小空間，而藉由絕緣材料60的材料選擇、形成絕緣材料60之製程方式或/及形成絕緣材料60之製程的參數調整，可使得絕緣材料60較不容易完全填滿此窄小空間，進而於絕緣材料60填入後形成空隙60A。因此，空隙60A的至少部分可於第三方向D3上低於金屬閘極53之第三最上表面53S。此外，絕緣材料60 可包括氮化矽(SiNx)或其他填洞能力較差的絕緣材料，但並不以此為限。在一些實施例中，空隙60A可於水平方向(例如第二方向D2)上形成於金屬閘極53與蝕刻停止層41之間，且空隙60A可於第三方向D3上形成於功函數層52之第四最上表面52S或/及閘極介電層51之第五最上表面51S之上，而遮罩層60M的底面可直接接觸閘極介電層51之第五最上表面51S。在一些實施例中，複數個空隙60A可形成於位於溝槽TR中的遮罩層60M中，且多個空隙60A中的至少兩個可分別形成於金屬閘極53於水平方向(例如第二方向D2)上的相對兩側。
如第6圖所示，於形成遮罩層60M與空隙60A之後，可先形成一層間介電層71覆蓋間隙子20、蝕刻停止層41、介電層42以及遮罩層60M，然後再形成複數個接觸結構72貫穿層間介電層71、介電層42以及蝕刻停止層41，而使各接觸結構72與對應之源極/汲極結構30相連而形成電性連接。在一些實施例中，接觸結構72可以自對準(self-aligned)的方式形成，但並不以此為限。經由上述的製作方法，可形成如第6圖中所示之半導體裝置100。半導體裝置100包括基底10、閘極結構50、間隙子20、遮罩層60M以及至少一空隙60A。閘極結構50設置於基底10上，且閘極結構50包括金屬閘極53。間隙子20設置於閘極結構50之側壁上，且間隙子20之第一最上表面20S係於第三方向D3上高於金屬閘極53之第三最上表面53S。遮罩層60M設置於閘極結構50上，而空隙60A設置於遮罩層60M中且於水平方向(例如第二方向D2)上設置於金屬閘極53與間隙子20之間。此外，閘極結構50可更包括功函數層52以及閘極介電層51。在一些實施例中，功函數層52可圍繞金屬閘極53的一下部，且功函數層52之第四最上表面52S可於第三方向D3上低於金屬閘極53之第三最上表面53S。在一些實施例中，閘極介電層51可圍繞金屬閘極53的下部，且閘極介電層51之第五最上表面51S可於第三方向D3上低於金屬閘極53之第三最上表面53S。於半導體裝置100之一剖視圖(例如第6圖)中， 功函數層52可包括一U字形結構圍繞金屬閘極53之下部，閘極介電層51可包括一U字形結構圍繞功函數層52以及金屬閘極53之下部，但並不以此為限。功函數層52之第四最上表面52S可於第三方向D3上未被金屬閘極53覆蓋，且至少一空隙60A可於第三方向D3上設置於功函數層52之第四最上表面52S之上。閘極介電層51之第五最上表面51S可於第三方向D3上未被金屬閘極53覆蓋，且至少一空隙60A可於第三方向D3上設置於閘極介電層51之第五最上表面51S之上。由於功函數層52的第四最上表面52S或/及閘極介電層51的第五最上表面51S低於金屬閘極53之第三最上表面53S，故可於溝槽TR中位於金屬閘極53與間隙子20之間的窄小空間中形成空隙60A，而空隙60A的至少部分可於第三方向D3上低於金屬閘極53之第三最上表面53S。
此外，半導體裝置100可更包括源極/汲極結構30、蝕刻停止層41以及接觸結構72。源極/汲極結構30與間隙子20相鄰設置，蝕刻停止層41設置於源極/汲極結構30上，接觸結構72貫穿蝕刻停止層41而與對應之源極/汲極結構30相連而形成電性連接。蝕刻停止層41之第二最上表面41S可於第三方向D3上高於金屬閘極53之第三最上表面53S，且至少一空隙60A可於水平方向(例如第二方向D2)上設置於金屬閘極53與蝕刻停止層41之間。在一些實施例中，半導體裝置100可包括複數個空隙60A設置於遮罩層60M中，且多個空隙60A中的至少兩個可於水平方向(例如第二方向D2)上分別設置於金屬閘極53的相對兩側，但並不以此為限。遮罩層60M中的空隙60A可被視為一空氣間隔(air gap)，而空隙60A的形成可加強接觸結構72與閘極結構50之間的隔離效果，藉此達到提升半導體裝置100之電性表現的目的。
綜上所述，在本發明之半導體裝置以及其製作方法中，可利用對於 閘極結構進行之回蝕刻製程的蝕刻選擇比控制，使得功函數層的最上表面或/及閘極介電層之最上表面低於金屬閘極的最上表面，且金屬閘極的最上表面於回蝕刻製程之後可低於間隙子的最上表面。因此，可在於金屬閘極上形成遮罩層之前，於金屬閘極與間隙子之間形成一窄小空間，而藉由填洞能力較差的絕緣材料或/及製程方式來形成位於閘極結構上之遮罩層則可於此空間中形成空隙。於金屬閘極與間隙子之間所形成的空隙可用以加強源極/汲極結構對應之接觸結構與閘極結構之間的隔離效果，進而可提升半導體裝置之電性表現。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10:基底
11:半導體結構
20:間隙子
20S:第一最上表面
30:源極/汲極結構
41:蝕刻停止層
41S:第二最上表面
42:介電層
50:閘極結構
51:閘極介電層
51S:第五最上表面
52:功函數層
52S:第四最上表面
53:金屬閘極
53S:第三最上表面
60:絕緣材料
60A:空隙
60M:遮罩層
71:層間介電層
72:接觸結構
100:半導體裝置
D1:第一方向
D2:第二方向
D3:第三方向
TR:溝槽

Claims (18)

  1. 一種半導體裝置，包括：一基底；一閘極結構，設置於該基底上，其中該閘極結構包括一金屬閘極以及一閘極介電層圍繞該金屬閘極的一下部；一間隙子設置於該閘極結構之側壁上，其中該間隙子之最上表面係高於該金屬閘極之最上表面；一遮罩層設置於該閘極結構上；至少一空隙(void)設置於該遮罩層中且設置於該金屬閘極與該間隙子之間，其中該遮罩層的底面直接接觸該閘極介電層之最上表面；一源極/汲極結構與該間隙子相鄰設置；一蝕刻停止層設置於該源極/汲極結構上；以及一接觸結構貫穿該蝕刻停止層，其中該蝕刻停止層與該間隙子設置於該至少一空隙與該接觸結構之間。
  2. 如請求項1所述之半導體裝置，其中該閘極結構更包括一功函數層圍繞該金屬閘極的該下部，且該功函數層之最上表面係低於該金屬閘極之該最上表面。
  3. 如請求項2所述之半導體裝置，其中該功函數層之該最上表面係未被該金屬閘極覆蓋，且該至少一空隙係設置於該功函數層之該最上表面之上。
  4. 如請求項2所述之半導體裝置，其中該功函數層包括一U字形結構圍繞該金屬閘極之該下部。
  5. 如請求項1所述之半導體裝置，其中該閘極介電層之該最上表面係低於該金屬閘極之該最上表面。
  6. 如請求項5所述之半導體裝置，其中該閘極介電層之該最上表面係未被該金屬閘極覆蓋，且該至少一空隙係設置於該閘極介電層之該最上表面之上。
  7. 如請求項5所述之半導體裝置，其中該閘極介電層包括一U字形結構圍繞該金屬閘極之該下部。
  8. 如請求項1所述之半導體裝置，其中該蝕刻停止層之最上表面係高於該金屬閘極之該最上表面，且該至少一空隙係設置於該金屬閘極與該蝕刻停止層之間。
  9. 如請求項1所述之半導體裝置，更包括複數個該空隙設置於該遮罩層中，其中該等空隙中的至少兩個係分別設置於該金屬閘極的相對兩側。
  10. 如請求項1所述之半導體裝置，其中該至少一空隙的至少部分係低於該金屬閘極之該最上表面。
  11. 一種半導體裝置的製作方法，包括：於一基底上形成一閘極結構，且該閘極結構係形成於被一間隙子圍繞之一溝槽中，其中該閘極結構包括一金屬閘極以及一閘極介電層圍繞該金屬閘 極的一下部，且該間隙子之最上表面係高於該金屬閘極之最上表面；於該溝槽中以及該閘極結構上形成一遮罩層，其中至少一空隙(void)係形成於位於該溝槽中的該遮罩層中，該至少一空隙係形成於該金屬閘極與該間隙子之間，該至少一空隙的至少部分係低於該金屬閘極之該最上表面，且該遮罩層的底面直接接觸該閘極介電層之最上表面；形成一源極/汲極結構，該源極/汲極結構與該間隙子相鄰；於該源極/汲極結構上形成一蝕刻停止層；以及形成一接觸結構貫穿該蝕刻停止層，其中該蝕刻停止層與該間隙子設置於該至少一空隙與該接觸結構之間。
  12. 如請求項11所述之半導體裝置的製作方法，更包括：於形成該遮罩層之前，對該閘極結構進行一回蝕刻製程，其中該閘極結構更括一功函數層圍繞該金屬閘極，且該功函數層之最上表面於該回蝕刻製程之後係低於該金屬閘極之該最上表面。
  13. 如請求項12所述之半導體裝置的製作方法，其中該功函數層之該最上表面係未被該金屬閘極覆蓋，且該至少一空隙係形成於該功函數層之該最上表面之上。
  14. 如請求項12所述之半導體裝置的製作方法，其中該閘極介電層之該最上表面於該回蝕刻製程之後係低於該金屬閘極之該最上表面。
  15. 如請求項14所述之半導體裝置的製作方法，其中該閘極介電層之該最上表面係未被該金屬閘極覆蓋，且該至少一空隙係形成於該閘極介電層之 該最上表面之上。
  16. 如請求項12所述之半導體裝置的製作方法，其中該蝕刻停止層之最上表面於該回蝕刻製程之後係高於該金屬閘極之該最上表面，且該至少一空隙係形成於該金屬閘極與該蝕刻停止層之間。
  17. 如請求項11所述之半導體裝置的製作方法，其中複數個該空隙係形成於位於該溝槽中的該遮罩層中，且該等空隙中的至少兩個係分別形成於該金屬閘極的相對兩側。
  18. 如請求項11所述之半導體裝置的製作方法，其中該遮罩層包括氮化矽。
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