CN106328507B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN106328507B
CN106328507B CN201510336284.6A CN201510336284A CN106328507B CN 106328507 B CN106328507 B CN 106328507B CN 201510336284 A CN201510336284 A CN 201510336284A CN 106328507 B CN106328507 B CN 106328507B
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layer
substrate
doped region
epitaxial layer
gate
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CN106328507A (zh
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李秋德
林克峰
李年中
黄庆男
黄世腾
刘明彦
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。该半导体元件的制作方法为，首先提供一基底，然后形成一掺杂区于基底中，形成一热氧化层于基底及掺杂区上，去除热氧化层以形成一第一凹槽，形成一外延层于基底上并填入第一凹槽内，以及形成一栅极介电层于外延层中。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种在基底上的高压元件区制作栅极介电层的方法。
背景技术
在现有半导体产业中，多晶硅系广泛地应用于半导体元件如金属氧化物半导体(metal-oxide-semiconductor,MOS)晶体管中，作为标准的栅极填充材料选择。然而，随着MOS晶体管尺寸持续地微缩，传统多晶硅栅极因硼穿透(boron penetration)效应导致元件效能降低，及其难以避免的空乏效应(depletion effect)等问题，使得等效的栅极介电层厚度增加、栅极电容值下降，进而导致元件驱动能力的衰退等困境。因此，半导体业界更尝试以新的栅极填充材料，例如利用功函数(work function)金属来取代传统的多晶硅栅极，用以作为匹配高介电常数(High-K)栅极介电层的控制电极。
然而在现今金属栅极晶体管制作过程中，由于高压区的栅极介电层通常突出于基底表面，因此高压区所完成的金属栅极一般明显高于低压区的金属栅极，使后续以化学机械研磨(chemical mechanical polishing,CMP)制作工艺去除部分层间介电层时容易磨掉大部分高压区的金属栅极。因此如何改良现行金属栅极制作工艺以解决此问题即为现今一重要课题。
发明内容
本发明优选实施例揭露一种制作半导体元件的方法。首先提供一基底，然后形成一掺杂区于基底中，形成一热氧化层于基底及掺杂区上，去除热氧化层以形成一第一凹槽，形成一外延层于基底上并填入第一凹槽内，以及形成一栅极介电层于外延层中。
本发明另一实施例揭露一种半导体元件，其包含一基底、一第一凹槽设于基底内、一外延层设于基底上以及一栅极介电层设于部分外延层中。其中外延层包含一第一部分镶嵌于第一凹槽内以及一第二部分设于基底上，栅极介电层则设于外延层的第一部分上。
附图说明
图1至图7为本发明优选实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 高压区
16 图案化掩模 18 离子注入制作工艺
20 掺杂区 22 热氧化层
24 第一凹槽 26 外延层
28 第二凹槽 30 栅极介电层
32 浅沟隔离 34 第一衬垫层
36 第二衬垫层
40 低压区 42 氧化层
44 第一部分 46 第二部分
52 栅极结构 54 间隙壁
56 源极/漏极区域 58 层间介电层
60 功函数金属层 62 低阻抗金属层
具体实施方式
请参照图1至图7，图1至图7为本发明优选实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板。基底12上定义有一元件区，例如一高压元件区(或简称高压区14)，其优选于后续制作工艺中用来制作一高压半导体元件。然后利用一图案化掩模16来进行一离子注入制作工艺18，以于基底12中形成至少一掺杂区20。在本实施例中，离子注入制作工艺18所注入的离子优选为N型掺质，例如可选自由锑及砷所构成的群组，且所形成的掺杂区20优选为一N+埋入层(n+buriedlayer,NBL)。另外本实施例虽以形成单一一个掺杂区20为例，但掺杂区20的数量并不局限于此，而可视制作工艺需求任意调整。
如图2所示，接着去除图案化掩模16并进行一热氧化制作工艺以形成一热氧化层22于基底12上并覆盖掺杂区20。在本实施例中，热氧化制作工艺的温度优选大于1000℃，且本发明形成热氧化层22时优选将掺杂区20往下推，使掺杂区20的上表面低于掺杂区20周围的基底12上表面。另外，在热氧化的过程中，被离子注入制作工艺所掺杂的区域会具有较快的氧化成长速度，因此设于掺杂区20正上方的热氧化层22厚度优选高于掺杂区20周围的基底12表面的热氧化层22厚度，例如掺杂区20正上方的热氧化层22优选约800埃，而设于掺杂区20周围的基底12表面的热氧化层22厚度则优选低于400埃，或更佳约300埃至400埃。
然后如图3所示，进行一蚀刻或清洗制作工艺，利用例如氢氟酸等蚀刻溶液来去除热氧化层22并暴露出下面的掺杂区20，且在去除热氧化层22后同时于掺杂区20上的基底12内形成一第一凹槽24。在本实施例中，第一凹槽24的深度，或是由掺杂区20顶部至基底12上表面的垂直距离约为380埃至420埃，或更佳为400埃。
随后如图4所示，可先选择性进行一清洗制作工艺去除第一凹槽24内或基底12表面所残留的不纯物或氧化物，然后全面性形成一外延层26于基底12上并填入第一凹槽24内。依据本发明的优选实施例，形成外延层26于基底12上并填入第一凹槽24内的同时优选于掺杂区20正上方的外延层26中形成对应第一凹槽24的第二凹槽28，其中第二凹槽28的深度优选等同图3中第一凹槽24的深度，例如约为380埃至420埃，或更佳为400埃。
接着如图5所示，形成一栅极介电层30于外延层26内的第二凹槽28中以及多个浅沟隔离32于外延层26中，其中栅极介电层30优选作为高压半导体元件的栅极介电层而浅沟隔离32则用来隔离各高压半导体元件与周边的每一个低压元件。在本实施例中，形成栅极介电层30的方式可进行一热氧化制作工艺，以于第二凹槽28中形成由氧化物所构成的栅极介电层30。形成浅沟隔离32的方法可先依序沉积一由氮化硅所构成的第一衬垫层(图未示)以及一由氧化硅所构成的第二衬垫层(图未示)于外延层26表面，然后进行一光刻暨蚀刻制作工艺去除部分第二衬垫层、部分第一衬垫层以及部分外延层26形成浅沟隔离所需的凹槽，之后再填入氧化物于凹槽内并以平坦化方式去除部分氧化物、第二衬垫层以及第一衬垫层以形成浅沟隔离32，并使浅沟隔离32、栅极介电层30与外延层26等的顶表面相互切齐。
值得注意的是，前述实施例虽以先形成栅极介电层30之后再形成浅沟隔离32为例，但不局限于此顺序，本发明的另一优选实施例又可选择先形成浅沟隔离32于外延层26内以及所需的掺杂阱(图未示)之后，再形成栅极介电层30于各第二凹槽28内。举例来说，如图6所示，可先依序沉积一由氮化硅所构成的第一衬垫层34以及一由氧化硅所构成的第二衬垫层36于外延层26表面并填入各第二凹槽28，然后进行一光刻暨蚀刻制作工艺，在不移除第二凹槽28内的第一衬垫层34与第二衬垫层36的情况下去除第二凹槽28旁的部分第二衬垫层36、部分第一衬垫层34与部分外延层26以形成浅沟隔离32所需的凹槽，之后再填入氧化物于凹槽内并以平坦化方式去除部分外延层26表面的氧化物、第二衬垫层36与第一衬垫层34以形成浅沟隔离32，并使浅沟隔离32、栅极介电层30与外延层26等的顶表面相互切齐。由于用来形成浅沟隔离32凹槽的第一衬垫层34与第二衬垫层36于形成栅极介电层30之前便已填入各第二凹槽28内，因此后续所形成的栅极介电层30与外延层26之间优选设有U型的第一衬垫层34与U型的第二衬垫层36，此实施例也属本发明所涵盖的范围。
请继续参照图7，本发明于形成图5的浅沟隔离后可依据制作工艺需求搭配低压区40进行后续晶体管制作工艺，例如可先于低压区40与高压区14覆盖一氧化层42，然后于低压区40及高压区34的氧化层42上分别形成一栅极结构52，其中低压区40的栅极结构52上表面优选与高压区14的栅极结构52上表面齐平。
在本实施例中，栅极结构52的制作方式可依据制作工艺需求以先栅极(gatefirst)制作工艺、后栅极(gate last)制作工艺的先栅极介电层(high-k first)制作工艺以及后栅极制作工艺的后栅极介电层(high-k last)制作工艺等方式制作完成。以本实施例的先栅极介电层制作工艺为例，可先于低压区40及高压区14的外延层26上分别形成一包含高介电常数介电层与多晶硅材料所构成的虚置栅极(图未示)，然后于虚置栅极侧壁形成间隙壁54。接着于各虚置栅极与间隙壁54两侧的外延层26中分别形成一源极/漏极区域56、形成一接触洞蚀刻停止层(图未示)覆盖虚置栅极，并形成一由四乙氧基硅烷(Tetraethylorthosilicate,TEOS)所组成的层间介电层58于接触洞蚀刻停止层上。
之后可进行一金属栅极置换(replacement metal gate)制作工艺，先平坦化部分的层间介电层58及接触洞蚀刻停止层，并再将各虚置栅极转换为一金属栅极。金属栅极置换制作工艺可包括先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammoniumhydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除各虚置栅极中的多晶硅材料以于层间介电层58中分别形成一凹槽。之后形成一至少包含U型功函数金属层60与低阻抗金属层62的导电层于各该凹槽内，并再搭配进行一平坦化制作工艺使U型功函数金属层60与低阻抗金属层62的表面与层间介电层58表面齐平，以形成栅极结构52的栅极电极。此外，本发明的其他优选实施例也可在高压区14的栅极结构52两侧下方分别另形成一浅沟隔离而介于栅极介电层30与源极/漏极区域56之间，但视元件特性需求的不同，也可以只在高压区14的栅极结构52单一侧下方形成有浅沟隔离，或者是如图7所示，仅在高压区14中形成一厚而平坦的栅极介电层30且完全埋设于基底12上的外延层26内。
在本实施例中，功函数金属层60优选用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层60可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层60可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层60与低阻抗金属层62之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层62则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极乃此领域者所熟知技术，在此不另加赘述。
又如图7所示，本发明另揭露一种半导体元件结构，其包含一高压元件设于高压区14与一低压元件设于低压区40。高压区14的高压元件主要包含一掺杂区20设于基底12中、一外延层26设于掺杂区20与基底12上、一栅极介电层30镶嵌于外延层26中以及一栅极结构52设于栅极介电层30上。其中外延层26又细部包含一第一部分44镶嵌于基底12内以及一第二部分46设于基底12与第一部分44上。
从元件关系来看，掺杂区20的上表面优选低于基底12上表面，栅极介电层30、源极/漏极区域56与浅沟隔离32均设于外延层26的第二部分46内，其中浅沟隔离32上表面与栅极介电层30及源极/漏极区域56上表面齐平。由于源极/漏极区域56设于外延层26中，浅沟隔离32上表面又同时与栅极结构52两侧源极/漏极区域56中的外延层26第二部分46上表面齐平。
综上所述，本发明主要先形成一掺杂区于一基底上的高压元件区，接着利用热氧化制作工艺形成一热氧化层于基底与掺杂区上并同时将掺杂区往下推，使掺杂区上表面低于掺杂区周围的基底表面。之后去除热氧化层形成凹槽，形成一外延层于基底上并填入该凹槽，然后再形成栅极介电层于外延层中。由于去除热氧化层时所形成的凹槽可间接于外延层中形成对应的凹槽，后续所形成的栅极介电层便可完全填入外延层的凹槽内且与外延层表面齐平，如此高压区的金属栅极便不至因突出的栅极介电层而于CMP制作工艺中被研磨掉。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (16)

1.一种制作半导体元件的方法，包含：
提供一基底；
形成一掺杂区于该基底中；
形成一热氧化层于该基底及该掺杂区上；
去除该热氧化层以形成一第一凹槽；
形成一外延层于该基底上并填入该第一凹槽内而于该外延层中形成一第二凹槽；以及
形成一栅极介电层于该第二凹槽内且与该外延层的上表面齐平。
2.如权利要求1所述的方法，其中该掺杂区包含N+埋入层。
3.如权利要求1所述的方法，还包含形成该掺杂区于该基底中并使该掺杂区的上表面与该基底表面齐平。
4.如权利要求1所述的方法，还包含进行一热氧化制作工艺以形成该热氧化层并将该掺杂区往下推以使该掺杂区的上表面低于该掺杂区周围的该基底的上表面。
5.如权利要求4所述的方法，其中该热氧化制作工艺的温度大于1000℃。
6.如权利要求1所述的方法，其中该第二凹槽位于该掺杂区上方。
7.如权利要求6所述的方法，其中该第二凹槽的高度等同该第一凹槽的高度。
8.如权利要求1所述的方法，还包含于形成该栅极介电层之前形成一浅沟隔离于该外延层中。
9.如权利要求1所述的方法，还包含于形成该栅极介电层之后形成一浅沟隔离于该外延层中。
10.如权利要求1所述的方法，还包含：
形成一栅极结构于该栅极介电层上；以及
进行一金属栅极置换制作工艺以将该栅极结构转换为金属栅极。
11.一种半导体元件，包含：
基底；
掺杂区，设于该基底中，形成一热氧化层于该基底及该掺杂区上，去除该热氧化层以形成一第一凹槽；
外延层，设于该第一凹槽内及该基底上，该外延层包含：
第一部分镶嵌于该第一凹槽内；以及
第二部分设于该基底与该第一部分上，其中该第二部分包括一第二凹槽；以及
栅极介电层，设于该第二凹槽内并与该外延层的该第二部分的上表面齐平。
12.如权利要求11所述的半导体元件，其中该掺杂区的上表面低于该基底的上表面。
13.如权利要求12所述的半导体元件，其中该掺杂区包含N+埋入层。
14.如权利要求11所述的半导体元件，还包含一浅沟隔离设于该外延层的该第二部分中。
15.如权利要求14所述的半导体元件，其中该浅沟隔离的上表面与该栅极介电层及该外延层的第二部分的上表面齐平。
16.如权利要求11所述的半导体元件，还包含金属栅极，设于该栅极介电层上。
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