TWI658591B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

Info

Publication number
TWI658591B
TWI658591B TW104108137A TW104108137A TWI658591B TW I658591 B TWI658591 B TW I658591B TW 104108137 A TW104108137 A TW 104108137A TW 104108137 A TW104108137 A TW 104108137A TW I658591 B TWI658591 B TW I658591B
Authority
TW
Taiwan
Prior art keywords
dielectric layer
gate structure
interlayer dielectric
hard mask
doped region
Prior art date
Application number
TW104108137A
Other languages
English (en)
Other versions
TW201633537A (zh
Inventor
呂佳霖
陳俊隆
廖琨垣
張峰溢
黃志森
洪慶文
黃偉豪
Original Assignee
聯華電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯華電子股份有限公司 filed Critical 聯華電子股份有限公司
Priority to TW104108137A priority Critical patent/TWI658591B/zh
Priority to US14/681,119 priority patent/US9698255B2/en
Publication of TW201633537A publication Critical patent/TW201633537A/zh
Priority to US15/602,087 priority patent/US9985123B2/en
Application granted granted Critical
Publication of TWI658591B publication Critical patent/TWI658591B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底，該基底上具有一閘極結構、一層間介電層環繞閘極結構以及一硬遮罩設於閘極結構上，然後形成一介電層於閘極結構及層間介電層上，去除部分介電層以暴露出硬遮罩及層間介電層以及進行一表面處理以形成一摻雜區於硬遮罩及層間介電層內。

Description

半導體元件及其製作方法
本發明是關於一種半導體元件及其製作方法，尤指一種利用表面處理於閘極結構上的硬遮罩以及層間介電層中形成摻雜區的製作方法。
在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor，MOS)電晶體中，作為標準的閘極填充材料選擇。然而，隨著MOS電晶體尺寸持續地微縮，傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低，及其難以避免的空乏效應(depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容值下降，進而導致元件驅動能力的衰退等困境。因此，半導體業界更嘗試以新的閘極填充材料，例如利用功函數(work function)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數(High-K)閘極介電層的控制電極。
在現今金屬閘極電晶體製作過程中，特別是在進行自行對準接觸插塞(self-aligned contacts,SAC))製程時通常會過度去除金屬 閘極上的硬遮罩，使接觸插塞直接電連接金屬閘極造成短路。因此如何改良現行金屬閘極製程以解決此問題即為現今一重要課題。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，該基底上具有一閘極結構、一層間介電層環繞閘極結構以及一硬遮罩設於閘極結構上，然後形成一介電層於閘極結構及層間介電層上，去除部分介電層以暴露出硬遮罩及層間介電層以及進行一表面處理以形成一摻雜區於硬遮罩及層間介電層內。
本發明另一實施例揭露一種半導體元件，包含一基底、一閘極結構設於基底上以及一層間介電層環繞閘極結構、一硬遮罩設於閘極結構上且該硬遮罩包含一摻雜區、一源極/汲極區域設於閘極結構兩側以及一接觸插塞設於層間介電層中並同時位於部分硬遮罩上。
12‧‧‧基底
14‧‧‧鰭狀結構
18‧‧‧閘極結構
20‧‧‧閘極結構
24‧‧‧側壁子
26‧‧‧源極/汲極區域
28‧‧‧磊晶層
30‧‧‧接觸洞蝕刻停止層
32‧‧‧層間介電層
34‧‧‧功函數金屬層
36‧‧‧低阻抗金屬層
38‧‧‧硬遮罩
40‧‧‧介電層
42‧‧‧圖案化遮罩
44‧‧‧開口
46‧‧‧摻雜區
48‧‧‧開口
50‧‧‧接觸插塞
52‧‧‧溝渠導體
54‧‧‧接觸洞導體
第1圖至第5圖為本發明較佳實施例製作一半導體元件之方法示意圖。
請參照第1圖至第5圖，第1圖至第5圖為本發明較佳實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上可定義有一電晶 體區，例如一PMOS電晶體區或一NMOS電晶體區。基底12上具有至少一鰭狀結構14及一絕緣層(圖未示)，其中鰭狀結構14之底部係被絕緣層，例如氧化矽所包覆而形成淺溝隔離，且部分的鰭狀結構14上另分別設有複數個閘極結構18、20。需注意的是，本實施例雖以兩個閘極結構為例，但閘極結構的數量並不侷限於此，而可視製程需求任意調整。
上述鰭狀結構14之形成方式可以包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中。接著，對應三閘極電晶體元件及雙閘極鰭狀電晶體元件結構特性的不同，而可選擇性去除或留下圖案化遮罩，並利用沈積、化學機械研磨(chemical mechanical polishing,CMP)及回蝕刻製程而形成一環繞鰭狀結構14底部之絕緣層。除此之外，鰭狀結構14之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出半導體層，此半導體層即可作為相對應的鰭狀結構14。同樣的，另可以選擇性去除或留下圖案化硬遮罩層，並透過沈積、CMP及回蝕刻製程形成一絕緣層以包覆住鰭狀結構14之底部。另外，當基底12為矽覆絕緣(SOI)基板時，則可利用圖案化遮罩來蝕刻基底上之一半導體層，並停止於此半導體層下方的一底氧化層以形成鰭狀結構，故可省略前述製作絕緣層的步驟。
閘極結構18、20之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先閘極介電層(high-k first)製程以及後閘極製程之後閘極介電層(high-k last)製程等方式製作完成。以本實施例之先閘極介電層製程為例，可先於鰭狀結構14 與絕緣層上形成一較佳包含高介電常數介電層與多晶矽材料所構成的虛置閘極(圖未示)，然後於虛置閘極側壁形成側壁子24。接著於側壁子24兩側的鰭狀結構14以及/或基底12中形成一源極/汲極區域26與磊晶層28、形成一接觸洞蝕刻停止層30覆蓋虛置閘極，並形成一由四乙氧基矽烷(Tetraethyl orthosilicate,TEOS)所組成的層間介電層32於接觸洞蝕刻停止層30上。
之後可進行一金屬閘極置換(replacement metal gate)製程，先平坦化部分之層間介電層32及接觸洞蝕刻停止層30，並再將虛置閘極轉換為一金屬閘極。金屬閘極置換製程可包括先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除虛置閘極中的多晶矽材料以於層間介電層32中形成一凹槽。之後形成一至少包含U型功函數金屬層34與低阻抗金屬層36的導電層於該凹槽內，並再搭配進行一平坦化製程使U型功函數金屬層34與低阻抗金屬層36的表面與層間介電層32表面齊平。
在本實施例中，功函數金屬層34較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層34可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層34可選用功函數為4.8eV~5.2eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層34與低 阻抗金屬層36之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層36則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。
形成閘極結構18、20後可先去除部分功函數金屬層34與低阻抗金屬層36以於側壁子24間蝕刻出一凹槽，然後填入一硬遮罩38於功函數金屬層34與低阻抗金屬層36上。其中硬遮罩38可為單一材料層或複合材料層，例如一包含氧化矽與氮化矽之複合層。
接著依序形成一介電層40以及一由遮罩層(圖未示)於層間介電層32上並覆蓋閘極結構18、20，然後進行一微影暨蝕刻製程去除部分遮罩層，以於介電層40上形成一圖案化遮罩42。在本實施例中，介電層40較佳包含氧化矽，圖案化遮罩42則較佳包含氮化鈦，但不侷限於此。
然後如第2圖所示，利用圖案化遮罩42進行一蝕刻製程，去除部分介電層40以形成一開口44或接觸洞暴露出閘極結構18、20上的部分硬遮罩38及閘極結構18、20之間的層間介電層32。
如第3圖所示，接著進行一表面處理，以於部分硬遮罩38與層間介電層32中形成一摻雜區46。在本實施例中，表面處理可利用一離子佈植或一固態擴散(solid-state diffusion,SSD)技術將 硼或碳等離子植入硬遮罩38與層間介電層32中以形成摻雜區46，其中離子佈植較佳直接將離子植入硬遮罩38等對象物中，而固態擴散技術則是先覆蓋一含有離子的摻雜層(圖未示)，例如一硼矽酸鹽(borosilicate glass,BSG)摻雜層於硬遮罩38與層間介電層32上，進行一退火製程將摻雜層中的離子或摻質趨入硬遮罩38及層間介電層32以形成摻雜區46，最後再拔除摻雜層。
更具體而言，所植入的離子較佳與開口44所暴露出的所有物件，包括硬遮罩38、側壁子24、接觸洞蝕刻停止層30以及層間介電層32等反應而形成摻雜區46。以植入硼離子為例，若硬遮罩38、側壁子24及接觸洞蝕刻停止層30等包含氮化矽而層間介電層32包含氧化物，則所植入的硼離子經由離子佈植或固態擴散方式植入後較佳分別與氮化矽及氧化物反應，以於硬遮罩38、側壁子24及接觸洞蝕刻停止層30中形成由硼氮化物(boron nitride)所組成的摻雜區46，並同時於層間介電層32中形成由氧化硼所構成的摻雜區46。
值得注意的是，本實施例雖同時於硬遮罩38、側壁子24、接觸洞蝕刻停止層30以及層間介電層32中形成摻雜區46，但在層間介電層32中由例如硼氧化物(boron oxide)所構成的摻雜區46並不會改變後續蝕刻的速率，反之硬遮罩38、側壁子24以及接觸洞蝕刻停止層30中由硼氮化物所構成的摻雜區46則會大幅降低蝕刻製程的速率。換句話說，後續利用蝕刻去除部分層間介電層32以形成開口或接觸洞時層間介電層32可依據一般蝕刻率被順利去除但硬遮罩38、側壁子24以及接觸洞蝕刻停止層30等則可藉由摻雜區46的保護較不受到蝕刻劑的影響而耗損。
之後如第4圖所示，利用圖案化遮罩42進行另一蝕刻製程，去除閘極結構18、20兩側的部分層間介電層32以形成另一開口48或接觸洞暴露出閘極結構18、20兩側的磊晶層28。
接著如第5圖所示，於開口44、48中填入所需的金屬材料，並搭配進行一平坦化製程，例如以化學機械研磨去除部分金屬材料以形成一接觸插塞50於部分閘極結構18、20上並電連接源極/汲極區域26，其中接觸插塞50更細部包含一溝渠導體(trench conductor)52以及一接觸洞導體(via conductor)54。其中，於開口44、48中填入所需的金屬材料之前，亦可先進行一金屬矽化物製程，以於開口48所暴露的磊晶層28上形成一金屬矽化物。由於製作接觸插塞50的過程為本技術領域所熟知技藝，在此不另加贅述。至此即完成本發明較佳實施例製作一半導體元件的方法。
請再參照第5圖，其另揭露本發明較佳實施例之一半導體元件之結構示意圖。如第5圖所示，半導體元件較佳包含一基底12、至少一閘極結構18設於基底12上、一層間介電層32環繞閘極結構18、一硬遮罩38設於閘極結構18上，一摻雜區46設於部分硬遮罩38中、一源極/汲極區域26設於閘極結構18兩側、一介電層40位於層間介電層32及部分硬遮罩38上以及一接觸插塞50設於部分介電層40與層間介電層32中並同時位於部分硬遮罩38上。
在本實施例中，摻雜區46除了設於部分硬遮罩38中，又可同時設置於硬遮罩38兩側的部分側壁子24及接觸洞蝕刻停止層30內，其中摻雜區46的邊緣較佳不超過溝渠導體52的邊緣部分， 而摻雜區46的深度則較佳不超過硬遮罩38的底部。另外本實施例之摻雜區46較佳包含硼或碳，但不侷限於此。此外，上述實施例雖以具有金屬閘極的鰭型電晶體(FinFET)來做說明，但本發明亦可應用於例如多閘極電晶體(multi-gate,MOSFET)之非平面式(non-planar)結構的金氧半電晶體以及非傳統型平面式結構的金氧半電晶體的製程中，或者是其他鄰近具有硬遮罩之半導體元件的介電層蝕刻製程中，以藉由摻雜區的保護來使硬遮罩等較不受到蝕刻劑的影響而耗損。
綜上所述，本發明主要於形成接觸接觸插塞之前先利用一表面處理將硼或碳等離子植入閘極結構上的硬遮罩以及閘極結構周圍的層間介電層以形成一摻雜區，並藉由此摻雜區使層間介電層與周圍的硬遮罩、側壁子以及接觸洞蝕刻停止層之間具有不同蝕刻選擇比，如此後續利用蝕刻去除部分層間介電層以形成接觸洞時便可在順利去除層間介電層的情況下使硬遮罩、側壁子以及接觸洞蝕刻停止層較不受到蝕刻過程的影響而耗損，進而防止後續所形成的接觸插塞不至因硬遮罩或接觸洞蝕刻停止層的耗損而與閘極結構直接接觸造成短路。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (14)

  1. 一種製作半導體元件的方法，包含：提供一基底，該基底上具有一閘極結構、一層間介電層環繞該閘極結構以及一硬遮罩設於該閘極結構上；形成一介電層於該閘極結構及該層間介電層上；去除部分該介電層以暴露出該硬遮罩及該層間介電層；以及進行一表面處理以形成一摻雜區於該硬遮罩及該層間介電層內。
  2. 如申請專利範圍第1項所述之方法，另包含：於進行該表面處理後去除部分鄰近該閘極結構之該層間介電層；以及形成一接觸插塞於該硬遮罩上並鄰近該閘極結構。
  3. 如申請專利範圍第2項所述之方法，另包含於去除部分該層間介電層時去除部分該層間介電層中之該摻雜區。
  4. 如申請專利範圍第1項所述之方法，其中該表面處理包含一離子佈植。
  5. 如申請專利範圍第1項所述之方法，其中該表面處理包含一固態擴散。
  6. 如申請專利範圍第1項所述之方法，其中該摻雜區包含硼或碳。
  7. 一種半導體元件，包含：一基底，該基底上具有一閘極結構以及一層間介電層環繞該閘極結構；一硬遮罩設於該閘極結構上，該硬遮罩包含一摻雜區以及一無摻雜區；一源極/汲極區域設於該閘極結構兩側；以及一接觸插塞設於該層間介電層中並同時位於部分該硬遮罩上，其中該接觸插塞之一垂直邊緣切齊並接觸該摻雜區以及該無摻雜區之間之一垂直交界線且該垂直邊緣以及該垂直交界線均垂直於該基底上表面。
  8. 如申請專利範圍第7項所述之半導體元件，另包含一介電層位於該層間介電層及部分該硬遮罩上。
  9. 如申請專利範圍第8項所述之半導體元件，其中該接觸插塞位於部分該介電層中。
  10. 如申請專利範圍第7項所述之方法，其中該摻雜區包含硼或碳。
  11. 如申請專利範圍第7項所述之半導體元件，另包含一接觸洞蝕刻停止層鄰近該閘極結構，且該接觸洞蝕刻停止層包含一第二摻雜區。
  12. 如申請專利範圍第11項所述之半導體元件，其中該摻雜區下表面切齊該第二摻雜區下表面。
  13. 如申請專利範圍第11項所述之半導體元件，另包含一側壁子環繞該閘極結構以及一第三摻雜區設於部分該側壁子內。
  14. 如申請專利範圍第13項所述之半導體元件，其中該摻雜區下表面切齊該第三摻雜區下表面。
TW104108137A 2015-03-13 2015-03-13 半導體元件及其製作方法 TWI658591B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW104108137A TWI658591B (zh) 2015-03-13 2015-03-13 半導體元件及其製作方法
US14/681,119 US9698255B2 (en) 2015-03-13 2015-04-08 Semiconductor device having gate structure with doped hard mask
US15/602,087 US9985123B2 (en) 2015-03-13 2017-05-22 Method for fabricating a semiconductor device having gate structure with doped hard mask

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW104108137A TWI658591B (zh) 2015-03-13 2015-03-13 半導體元件及其製作方法

Publications (2)

Publication Number Publication Date
TW201633537A TW201633537A (zh) 2016-09-16
TWI658591B true TWI658591B (zh) 2019-05-01

Family

ID=56888257

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104108137A TWI658591B (zh) 2015-03-13 2015-03-13 半導體元件及其製作方法

Country Status (2)

Country Link
US (2) US9698255B2 (zh)
TW (1) TWI658591B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10998228B2 (en) * 2014-06-12 2021-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned interconnect with protection layer
US9627534B1 (en) 2015-11-20 2017-04-18 United Microelectronics Corp. Semiconductor MOS device having a dense oxide film on a spacer
CN107104051B (zh) * 2016-02-22 2021-06-29 联华电子股份有限公司 半导体元件以及其制作方法
US11088033B2 (en) * 2016-09-08 2021-08-10 International Business Machines Corporation Low resistance source-drain contacts using high temperature silicides
KR102472133B1 (ko) * 2016-09-22 2022-11-29 삼성전자주식회사 집적회로 소자
CN108389861B (zh) * 2017-02-03 2019-06-28 联华电子股份有限公司 半导体元件及其形成方法
US10283617B1 (en) * 2017-11-01 2019-05-07 Globalfoundries Inc. Hybrid spacer integration for field-effect transistors
US11205703B2 (en) * 2019-07-08 2021-12-21 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device and fabrication method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070111448A1 (en) * 2005-11-15 2007-05-17 Hong-Jyh Li Semiconductor devices and methods of manufacture thereof
US20120032238A1 (en) * 2010-08-03 2012-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Contact etch stop layers of a field effect transistor
US20130277767A1 (en) * 2012-04-18 2013-10-24 International Business Machines Corporation Etch stop layer formation in metal gate process
US20140312397A1 (en) * 2013-04-22 2014-10-23 International Business Machines Corporation Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100295061B1 (ko) * 1999-03-29 2001-07-12 윤종용 챔퍼가 형성된 실리사이드층을 갖춘 반도체소자 및 그 제조방법
US7462302B2 (en) * 2006-01-20 2008-12-09 Chung-Cheng Chang Indium oxide based material and method for preparing the same
US8877645B2 (en) * 2011-09-15 2014-11-04 International Business Machines Corporation Integrated circuit structure having selectively formed metal cap
US8741723B2 (en) * 2012-04-25 2014-06-03 Globalfoundries Inc. Methods of forming self-aligned contacts for a semiconductor device
US8802560B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating an semiconductor interconnect structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070111448A1 (en) * 2005-11-15 2007-05-17 Hong-Jyh Li Semiconductor devices and methods of manufacture thereof
US20120032238A1 (en) * 2010-08-03 2012-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Contact etch stop layers of a field effect transistor
US20130277767A1 (en) * 2012-04-18 2013-10-24 International Business Machines Corporation Etch stop layer formation in metal gate process
US20140312397A1 (en) * 2013-04-22 2014-10-23 International Business Machines Corporation Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact

Also Published As

Publication number Publication date
US20170263744A1 (en) 2017-09-14
US9698255B2 (en) 2017-07-04
US9985123B2 (en) 2018-05-29
TW201633537A (zh) 2016-09-16
US20160268203A1 (en) 2016-09-15

Similar Documents

Publication Publication Date Title
CN111653483B (zh) 半导体器件及其制作方法
TWI658591B (zh) 半導體元件及其製作方法
US9947766B2 (en) Semiconductor device and fabricating method thereof
TWI675406B (zh) 半導體元件及其製作方法
US9653356B2 (en) Methods of forming self-aligned device level contact structures
TWI650804B (zh) 半導體元件及其製作方法
CN105489490B (zh) 半导体元件及其制作方法
CN107808849B (zh) 半导体元件及其制作方法
CN113659004A (zh) 半导体元件及其制作方法
CN114300363A (zh) 半导体元件及其制作方法
CN106409764B (zh) 制作半导体元件的方法
TW201622141A (zh) 具有磊晶結構之鰭狀場效電晶體
TWI728174B (zh) 半導體元件及其製作方法
TW201733116A (zh) 半導體裝置
TW201608641A (zh) 半導體元件及其製作方法
CN106206714B (zh) 半导体器件
US11456304B2 (en) Semiconductor structure and forming method thereof
US10418286B2 (en) Semiconductor structure and fabrication method thereof
CN108666267B (zh) 半导体结构及其形成方法
CN108022842B (zh) 半导体元件及其制作方法
CN110828377B (zh) 一种具有不对称功函数金属层的半导体元件
TWI502633B (zh) 形成金屬閘極之方法
CN114078762B (zh) 半导体结构及其形成方法
CN220963349U (zh) 半导体装置
CN114068394B (zh) 半导体结构的形成方法