CN105762106A - 半导体装置及其制作工艺 - Google Patents

半导体装置及其制作工艺 Download PDF

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Publication number
CN105762106A
CN105762106A CN201410794508.3A CN201410794508A CN105762106A CN 105762106 A CN105762106 A CN 105762106A CN 201410794508 A CN201410794508 A CN 201410794508A CN 105762106 A CN105762106 A CN 105762106A
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groove
semiconductor device
epitaxial structure
substrate
device described
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CN105762106B (zh
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黄世贤
张哲玮
叶志杰
蔡子仪
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US14/613,343 priority patent/US9466678B2/en
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Abstract

本发明公开一种半导体装置及其制作工艺，该半导体装置包含一基底；一外延结构；以及一沟槽。该外延结构位于该基底内。该沟槽位于该外延结构内，其中该沟槽在垂直该基底的方向上具有一截面，该截面的至少一部分自该沟槽的开口向下逐渐扩张。

Description

半导体装置及其制作工艺
技术领域
本发明涉及一种半导体装置及其制作工艺，特别是涉及一种具有沟槽的外延结构的半导体装置及其制作工艺。
背景技术
在半导体集成电路的制作工艺中，金属氧化物半导体(metal-oxide-semiconductor；MOS)晶体管是一种极重要的电子元件，而随着半导体元件的尺寸越来越小，MOS晶体管的制作工艺步骤也有许多的改进，以制造出体积小而高品质的MOS晶体管。
现有的MOS晶体管制作工艺是在半导体基底上形成栅极结构之后，再于栅极结构相对两侧的基底中形成轻掺杂漏极结构(lightlydopeddrain；LDD)。接着于栅极结构侧边形成间隙壁(spacer)，并以此栅极结构及间隙壁做为掩模，再进行离子注入步骤，以于半导体基底中形成源极/漏极区域。而为了要将晶体管的栅极与源极/漏极区域适当电连接于电路中，因此需要形成接触插塞(contactplug)来进行导通。通常接触插塞的材质为钨(W)、铝、铜等金属导体，然而其与栅极结构、源极/漏极区域等多晶或单晶硅等材质之间的直接导通并不理想；因此为了改善金属插塞与栅极结构、源极/漏极区之间的欧米接触(Ohmicontact)，通常会在栅极结构与源极/漏极区域的表面再形成一金属硅化物(silicide)。
然而，现阶段的金属硅化物制作工艺仍有许多待改进的缺点，因此如何改良现行制作工艺以提升MOS晶体管的效能即为现今一重要课题。
发明内容
本发明的目的在于提供一种新颖的半导体装置，其接触插塞与源极/漏极之间具有较低的接触电阻值(contactresistance；Rc)，而能达到优选的效能。
本发明另一目的在于提供一种半导体装置的制作工艺，其可有效增加接触插塞与源极/漏极的接触面积，进而降低两者之间的接触电阻值。
本发明的目的在于提供一种半导体装置，其包含一基底；一外延结构；以及一沟槽。该外延结构位于该基底内。该沟槽位于该外延结构内，其中该沟槽在垂直该基底的方向上具有一截面，该截面的至少一部分自该沟槽的开口向下逐渐扩张。
本发明的另一目的在于提供一种半导体装置的制作工艺，包含下列步骤。首先，在一基底上形成一第一沟槽。接着，在该第一沟槽内形成一外延结构。之后，在该外延结构内形成一第二沟槽，其中该第二沟槽在垂直该基底的方向上具有一截面，该截面的至少一部分自该第二沟槽的开口向下逐渐扩张。
本发明的半导体制作工艺，主要是在接触孔蚀刻制作工艺中，先形成位于介电层内的接触孔，再进一步穿过接触孔，而于栅极结构两侧基底的外延结构内形成一沟槽。该沟槽具有由上而下逐渐扩张的截面形状，由此，可使随后形成的金属硅化物结构形成在该沟槽的一内表面，因而可有效降低接触插塞与金属硅化物之间的电阻。
附图说明
图1至图6为本发明第一实施例中半导体制作工艺的步骤示意图；
图7至图8为本发明第二实施例中半导体制作工艺的步骤示意图；
图9为本发明第二实施例的一变化型的的步骤示意图；
图10为本发明第二实施例的另一变化型的步骤示意图。
主要元件符号说明
300基底
310接触孔
320鳍状结构
330接触插塞
331阻障层
332接触金属层
340栅极结构
341介质层
342虚置栅极
343帽盖层
344间隙壁
345轻掺杂源极/漏极
346栅极介电层
347功函数金属层
348金属栅极
349盖层
350接触插塞
351阻障层
352接触金属层
360沟槽
360a源极/漏极
361外延结构
362沟槽
362a底面
362S1截面
363沟槽
364金属硅化物层
365金属硅化物层
366沟槽
366a底面
366S1截面
368沟槽
368a底面
368S1截面
380层间介电层
400介电层
d深度
W最宽处
θ、θ’角度
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的数个优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
请参照图1至图6，所绘示者为本发明第一实施例中形成半导体装置的制作工艺示意图。首先，如图1所示，提供一基底300，例如一硅基底(siliconsubstrate)、外延硅(epitaxialsiliconsubstrate)、硅锗半导体基底(silicongermaniumsubstrate)、碳化硅基底(siliconcarbidesubstrate)或硅覆绝缘(silicononinsulation；SOI)基板，并且在基底300上形成至少一栅极结构340。在本实施例中，先在基底300上形成至少一鳍状结构320及一绝缘层(未绘示)，再于鳍状结构320上形成栅极结构340。鳍状结构320的形成方式例如包含先于基底300上形成一图案化掩模(未绘示)，再经过一蚀刻制作工艺，将该图案化掩模的图案转移至基底300中，再移除该图案化掩模，即可在基底300中形成多个沟槽(未绘示)，后续在沟槽中填入绝缘层(未绘示)，使得突出于绝缘层的基底300形成鳍状结构320，该绝缘层形成浅沟隔离。在其他实施例中，若形成的晶体管为平面晶体管(planartransistor)，也可省略该鳍状结构，直接在平面基底上形成该栅极结构。
在一实施例中，栅极结构340包含一介质层(interfaciallayer)341、一虚置栅极(dummygate)342、一帽盖层(cappinglayer)343、一间隙壁(spacer)344以及一轻掺杂源极/漏极(LDD)345。其中，介质层341例如可包含二氧化硅(SiO2)或氮化硅(SiN)。虚置栅极342例如是多晶硅(polysilicon)，包含不具有任何掺杂(undoped)多晶硅材料、具有掺杂的多晶硅材料、或非晶硅材料等，但也可以是由上述材料的组合。帽盖层343可选择为一复合膜层结构，如图1所示，例如包含二氧化硅、氮化硅、碳化硅(SiC)、碳氮化硅(SiCN)或上述材料的组合等，但在其他实施例中也可是由上述材料组成的单一膜层。间隙壁344同样可选择为一单层或复合膜层的结构，例如其可包含高温氧化硅层(hightemperatureoxide；HTO)、氮化硅、氧化硅、氮氧化硅或使用六氯二硅烷(hexachlorodisilane；Si2Cl6)形成的氮化硅(HCD-SiN)。本实施例的栅极结构340形成步骤，例如先在基底300上全面形成一介质材料层(未绘示)、一虚置栅极材料层(未绘示)、帽盖材料层(未绘示)后，再图案化这些堆叠材料层，进而形成了一栅极堆叠结构(未绘示)。接着，再于该栅极堆叠结构两侧的鳍状结构320(基底300)中形成轻掺杂源极/漏极345，最后再于该栅极堆叠结构的侧壁上形成间隙壁344，由此形成本实施例的栅极结构340。然而，本领域者应可轻易了解，本发明的栅极结构也可能以其他方式形成，并不限于前述的制作步骤。此外，本实施例中的栅极结构340虽是采用「后栅极(gate-last)制作工艺」并搭配「后高介电常数介电层(high-klast)制作工艺」为实施样态进行说明，但并不以此为限，在其他实施例中，也可选择直接于该基底上形成一金属栅极结构(未绘示)，该金属栅极结构至少包含一功函数金属层(workfunctionlayer)及一金属栅极。
接着，如图2所示，进行一蚀刻制作工艺以在栅极结构340两侧的鳍状结构320(基底)上形成一沟槽360。举例来说，该蚀刻制作工艺可包含先进行一干蚀刻步骤以在栅极结构340两侧的鳍状结构320中预先形成一初始沟槽(未绘示)，再接着进行一湿蚀刻制作工艺，各向同性地加大该初始沟槽，以形成沟槽360。在本发明的一实施例中，该湿蚀刻例如可选择使用氢氧化铵(ammoniumhydroxide；NH4OH)或氢氧化四甲基铵(tetramethylammoniumhydroxide；TMAH)等的蚀刻液体。值得注意的是，形成沟槽360的方式不限于前述干蚀刻搭配湿蚀刻的方式，也可以通过单次或多次的干蚀刻及/或湿蚀刻的方式来形成。在一实施例中，沟槽360可具有不同的截面形状，例如是圆弧、六边形(hexagon；又称sigmaΣ)或八边形(octagon)等截面形状，本实施例是以六边形的截面形状为实施样态说明，但本发明并不以此为限。
而后，如图3所示，进行一选择性外延成长(selectiveepitaxialgrowth；SEG)制作工艺，以于沟槽360中形成一外延结构361，如图3所示。在本实施例中，外延结构361的一顶表面会与鳍状结构320的一顶表面齐平，且优选会具有与沟槽360相同的截面形状，如圆弧、六边形(hexagon；又称sigmaΣ)或八边形(octagon)的截面形状，但也可以是其他截面形状。在本发明优选实施例中，外延结构361根据不同的金属氧化物半导体(MOS)晶体管类型而可以具有不同的材质，举例来说，若该金属氧化物半导体晶体管为一P型晶体管(PMOS)时，外延结构361可选择包含硅化锗(SiGe)、硅化锗硼(SiGeB)或硅化锗锡(SiGeSn)。而于本发明另一实施例中，若该金属氧化物半导体晶体管为一N型晶体管(NMOS)时，则外延结构361则可选择包含碳化硅(SiC)、碳磷化硅(SiCP)或磷化硅(SiP)。此外，选择性外延制作工艺可以用单层或多层的方式来形成，且其异质原子(例如锗原子或碳原子)也可以渐层的方式改变，但优选是使外延结构361的表面较淡或者无锗原子，以利后续金属硅化物层的形成。另一方面，本实施例虽是以顶表面与鳍状结构320的顶表面齐平的外延结构361为实施样态说明，但在本发明的其他实施例中，也可选择使外延结构进一步向上延伸至高于基底300的该顶表面。
后续，进行一离子注入制作工艺，以在外延结构361的一部分或全部形成一源极/漏极360a。在另一实施例中，源极/漏极360a的形成也可同步(in-situ)于选择性外延成长制作工艺进行，例如金属氧化物半导体是PMOS时，形成硅化锗外延结构、硅化锗硼外延结构或硅化锗锡外延结构，可以伴随着注入P型掺杂；或是当金属氧化物半导体是NMOS时，形成硅化碳外延结构、硅化碳磷外延结构或硅化磷外延结构，可以伴随着注入N型掺杂。由此，可省略后续该P型/N型晶体管的源极/漏极的离子注入步骤。且在另一实施例中，源极/漏极360a的掺杂也可以渐层的方式形成。
之后，则如图4所示，在基底300上形成一层间介电层380覆盖在栅极结构340后，进行一金属栅极置换(replacementmetalgate)制作工艺，将虚置栅极342转换为一金属栅极。本实施例的金属栅极的形成步骤，例如先在基底300上全面性地形成一层间介电材料层(未绘示)，例如是一氧化硅层，以全面覆盖栅极结构340，通过一平坦化制作工艺，如化学机械研磨制作工艺、蚀刻制作工艺或两者的组合，部分移除该层间介电材料层及部分的间隙壁344，并完全移除帽盖层343，而后再进行一选择性的干蚀刻或湿蚀刻制作工艺来去除虚置栅极342及介质层341，以形成一栅极沟槽(未绘示)及层间介电层380。最后，依序于该栅极沟槽内填入一栅极介电材料层(未绘示)、功函数金属材料层(未绘示)一金属栅极材料层(未绘示)及一盖层材料层(未绘示)，再通过一化学机械研磨制作工艺移除栅极沟槽外的上述材料层，而形成如图4所示的一栅极介电层346、一功函数金属层347、一金属层348及一盖层349。于一实施例中，也可在功函数金属层347以及基底300的鳍状结构320之间进一步形成一阻障层(未绘示)，例如是一钛(Ti)层、氮化钛(TiN)层、钽(Ta)层或氮化钽(TaN)层等，但不以此为限。此外，在本发明的另一实施例中，还可选择在基底300上全面地形成一接触洞蚀刻停止层(contactetchstoplayer；CESL；未绘示)，例如是一单一层或复合层，以覆盖该金属栅极，由此对该金属栅极施加所需的压缩应力或是伸张应力。
在本发明的一实施例中，栅极介电层346例如是包含二氧化硅(SiO2)、氮化硅(SiN)或高介电常数(highdielectricconstant，high-k)材料，而功函数金属层347优选用以调整形成金属栅极的功函数，功函数金属层347可视该金属氧化物半导体晶体管的类型而做调整。举例说明，若该金属氧化物晶体管为N型晶体管，功函数金属层347可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或碳化钛铝(TiAlC)等，但不以此为限；若该金属氧化物晶体管为P型晶体管，功函数金属层347则可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。金属层348则例如是包含铝(Al)、钛、钽或钨(W)等，但不以此为限。另一方面，本领域者应可轻易了解，本发明的金属栅极结构也可能以其他方式或材料形成，并不限于前述的制作步骤与材料选择，此是本领域者所熟知技术，不再另加赘述。此外，在一实施例中，若原始栅极结构340已能符合产品需求，也可选择性省略此金属栅极置换步骤。
后续，如图5所示，进行接触孔蚀刻制作工艺。具体来说，先在层间介电层380上形成一介电层400，其可包含和层间介电层380一样的材质或是其他适合的材质。接着在介电层400以及层间介电层380中形成至少一接触孔310以分别暴露部分的外延结构361。该接触孔蚀刻制作工艺，例如包含进行一光刻蚀刻制作工艺，形成一图案化光致抗蚀剂层(图未示)于介电层400上，接着进行一蚀刻制作工艺，去除部分介电层400与栅极结构340两侧的层间介电层380，以形成多个接触孔310并暴露出部分的外延结构361。值得说明的是，本实施例的接触孔蚀刻制作工艺在形成接触孔310后，更进一步沿着接触孔310垂直向下蚀刻外延结构361，以在外延结构361形成一沟槽363，如图5所示。需进一步说明的是，沟槽363具有一深度d，且深度d优选是外延结构361高度的30％至70％，使沟槽363的一底面363a的最低点低于外延结构361的截面最宽处W。随后，可选择进行一预清洗制作工艺，去除接触孔310及沟槽363内经由前述光刻蚀刻制作工艺后所剩余的残留物。然而，在本发明的其他实施例中，也可选择省略该预清洗制作工艺。
接着，如图6所示，依序进行一金属硅化制作工艺及接触插塞制作工艺，以在接触孔310所暴露出的外延结构361表面形成一金属硅化物层365，并在接触孔310内形成一接触插塞(contactplug)330。更详言之，本实施例的金属硅化制作工艺，例如是先共形地(conformally)形成一金属层(未绘示)于接触孔310及沟槽363内，其中，该金属层优选选自钛、钴、镍及铂等所构成的群组，且最佳为钛，但不以此为限。然后，再依序进行一热处理制作工艺以在外延结构361上形成金属硅化物365，例如是硅化钛等。在本实施例中，该热处理制作工艺例如是包含一浸入式退火(soakanneal)制作工艺，其温度优选介于500℃至600℃，且最佳为550℃，而其处理时间则优选介于10秒至60秒；以及一峰值退火(spikeanneal)制作工艺，其温度优选介于600℃至950℃，且最佳为600℃，而其处理优选时间则优选介于100毫秒至5秒。最后，移除该未反应的金属层。然而，本领域者应可轻易了解，本发明的金属硅化物制作工艺也可能以其他方式形成，并不限于前述的制作步骤，例如，在另一实施例中，也可选择依序形成一第一金属层(未绘示)及第二金属层(未绘示)于该接触孔内，该第一金属层例如是钛层，而第该二金属层例如是氮化钛等金属化合物，并且于该热处理制作工艺后，选择性地移除该第一层金属层与第二层金属层，或不要移除该第二金属层，使第二金属层直接做为接触插塞的阻障层。
形成金属硅化物层365后，则接续进行该接触插塞制作工艺。具体来说，接触插塞330会填满接触孔310及沟槽363，且其包含一阻障层(barrierlayer)331以及一接触金属层(contactmetallayer)332。在本发明的一实施例中，阻障层331例如是钛层、氮化钛层、钽层或氧化钽层，而接触金属层332例如是钨或其他低电阻的金属，但不以此为限。值得说明的是，在本实施例中，阻障层331会直接接触金属硅化物层365，且由于金属硅化物层365是形成在外延结构361的沟槽363表面，因此，使阻障层331与金属硅化物层365之间的接触面积得以增加，如图6所示。在这样的情况下，接触插塞330的接触金属层332与金属硅化物层365之间的接触面积可也得以增加，可有效降低两者接面的电阻，进而增加半导体装置整体的电性表现。由此，即可完成本发明第一实施例的半导体装置。此外，在形成了接触插塞330后，后续可继续进行其他金属内连线制作工艺，该技术应为本领域者所熟知，在此不多做描述。
本发明的半导体装置的制作工艺，主要是在接触孔蚀刻制作工艺中，先形成位于介电层内的接触孔，再进一步穿过接触孔，而于栅极结构两侧鳍状结构(基底)的外延结构内形成一沟槽。由此，可使随后形成的金属硅化物结构形成在该沟槽的一内表面，因而可有效降低接触插塞与金属硅化物之间的电阻。
下文将针对本发明半导体元件制作工艺的其他实施例进行说明。且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件系以相同的标号进行标示，以利于各实施例间互相对照。
请参照图7至图8所示，所绘示者为本发明第二实施例中形成半导体装置的制作工艺示意图。本实施例的半导体制作工艺和前述第一实施例的图1至图5相同，在此不再赘述。如图7所示，本实施例与前述实施例的主要差异在于，在形成如图5所示的半导体结构后，进一步侧向蚀刻外延结构361，特别是沿着沟槽363的侧壁横向蚀刻，以形成沟槽362，使沟槽362具有自其开口端逐渐向下扩张的一侧壁。具体来说，该侧向蚀刻优选是沿着<111>面进行，优选是沿着与基底300顶表面之间具有50度至72度角度的方向，更佳是53度。在此情况下，沟槽362的该侧壁与基底300的该顶表面之间可形成一角度θ，大体上为50度至72度，更佳是53度，由此使沟槽362的一截面362S1形成自开口向下逐渐扩张的截面形状，例如是呈六边形(hexagon；又称sigmaΣ)，如图7所示。值得进一步说明的是，前述的截面362S1是指沟槽362在垂直基底300方向的一剖面，于一实施例中，沟槽362的截面362S1具有低于基底300该顶表面的一底面362a，且底面362a的最低点优选是低于外延结构361截面的最宽处W，如图7所示。于另一实施例中，通过调配不同的蚀刻比例，也可形成截面366S1如梯形状的沟槽366，如图9所示，且沟槽366截面366S1的一底角θ’大体上为50度至72度。此外，在另一实施例中，另可通过控制该侧向蚀刻的蚀刻比例，形成截面368S1近似六面型的不规则状沟槽368，如图10所示，且沟槽368的截面368S1可具有一圆弧底面368a。
接着，则如同前述第一实施例，依序进行金属硅化制作工艺及接触插塞制作工艺，以形成金属硅化物层364及接触插塞350。如图8所示，本实施例的金属硅化物层364同样会形成于外延结构361的沟槽362表面，因而会共形地形成自开口向下逐渐扩张的截面形状，例如是呈六边形(hexagon；又称sigmaΣ)。因此，可进一步增加阻障层351与金属硅化物层364之间的接触面积。同理可知，在上述图7、图8、图9及图10的实施例中，都可以看出该侧向蚀刻可使沟槽362、366、368的该侧壁与基底300的顶表面之间形成一特定角度，例如是一锐角，且该锐角于一实施例中大体上为50度至72度。也就是说，沟槽362、366、368截面362S1、366S1、368S1的至少一部分(特别是靠近沟槽开口的部分)都是由上而下逐渐扩张，由此得以增加外延结构361与金属硅化物层364及/或接触插塞350(接触金属层352)的接触面积。因而可有效降低两者接面的电阻，进而增加半导体装置整体的电性表现。由此，即可完成本发明第二实施例的半导体装置。此外，需额外注意的是，除前述差异外，本实施例的其他步骤，都与前述实施例相同，故不再赘述。
此外，前述实施例以「后栅极(gatelast)」的「后高介电常数层(high-klast)」为示例，但本发明的半导体装置也可能在「前栅极」或「前高介电常数层」的制作工艺下形成。或者，前述实施例主要以非平面晶体管(non-planartransistor)的制作方法为例，但本发明也可应用于其他平面晶体管(planartransistor)制作方法，例如省略该鳍状结构，而直接于基底上形成栅极结构、外延结构等，本领域者应可轻易理解，这些实施例均应属本发明所涵盖的范围。
综上所述，本发明提供了一种半导体装置的结构以及制作工艺，其主要是在接触孔蚀刻制作工艺中，先形成位于介电层内的接触孔，再进一步穿过接触孔，而于栅极结构两侧的外延结构内形成一沟槽，例如是呈六边形状、梯形状或不规则状。由此，可使随后形成的金属硅化物结构形成在该沟槽的一内表面，进一步增加接触插塞与该金属硅化物层之间的接触面积，因而可有效降低接触插塞与金属硅化物之间的电阻。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种半导体装置的制作工艺，其特征在于包含下列步骤：
在一基底上形成一第一沟槽；
在该第一沟槽内形成一外延结构；以及
在该外延结构内形成一第二沟槽，其中该第二沟槽在垂直该基底的方向上具有一截面，该截面的至少一部分自该第二沟槽的开口向下逐渐扩张。
2.依据权利要求1所述的半导体装置的制作工艺，其特征在于，形成该第二沟槽的步骤包含：
垂直蚀刻该外延结构，以形成一第三沟槽；以及
侧向蚀刻该第三沟槽的一侧壁，以形成该第二沟槽。
3.依据权利要求1所述的半导体装置的制作工艺，其特征在于，还包含：
在该第二沟槽的表面上形成一金属硅化物层。
4.依据权利要求3所述的半导体装置的制作工艺，其特征在于，还包含：
在该基底上形成一介电层；
在该介电层内形成一接触孔；
穿过该接触孔以在该外延结构中形成该第二沟槽；以及
进行一金属硅化物制作工艺以形成该金属硅化物层。
5.依据权利要求1所述的半导体装置的制作工艺，其特征在于，还包含：
提供一鳍状结构，该鳍状结构位于该基底内，且该第一沟槽形成在该鳍状结构内。
6.一半导体装置，其特征在于，包含：
基底；
外延结构，该外延结构位于该基底内；以及
沟槽，该沟槽位于该外延结构内，其中该沟槽在垂直该基底的方向上具有一截面，该截面的至少一部分自该沟槽的开口向下逐渐扩张。
7.依据权利要求6所述的半导体装置，其特征在于，该沟槽的该截面具有一底面，该底面低于该基底的顶表面。
8.依据权利要求7所述的半导体装置，其特征在于，该沟槽的该截面具有一侧壁，该侧壁与该基底的该顶表面之间具有一角度，该角度为50度至72度。
9.依据权利要求6所述的半导体装置，其特征在于，该沟槽的该截面具有一底面，该底面的最低点低于该外延结构截面的最宽处。
10.依据权利要求9所述的半导体装置，其特征在于，该底面为圆弧底面。
11.依据权利要求6所述的半导体装置，其特征在于，该沟槽具有一深度，该深度为该外延结构的高度的30％至70％。
12.依据权利要求6所述的半导体装置，其特征在于，该沟槽的该截面是呈梯形或六边形(hexagon；又称sigmaΣ)。
13.依据权利要求6所述的半导体装置，其特征在于，还包含：
金属硅化物层，该金属硅化物层位于该沟槽的一表面上。
14.依据权利要求13所述的半导体装置，其特征在于，还包含：
介电层，该介电层位于该基底上；以及
接触插塞，该接触插塞位于该介电层内且电连接该外延结构。
15.依据权利要求14所述的半导体装置，其特征在于，该金属硅化物层位于该接触插塞与该外延结构之间。
16.依据权利要求13所述的半导体装置，其特征在于，该金属硅化物层包含硅化钛。
17.依据权利要求6所述的半导体装置，其特征在于，还包含：
鳍状结构，该外延结构是位于该鳍状结构中。
18.一半导体装置，其特征在于，包含：
基底；
外延结构，该外延结构位于该基底内；以及
沟槽，该沟槽位于该外延结构内，其中该沟槽具有一深度，该深度为该外延结构的高度的30％至70％。
19.依据权利要求18所述的半导体装置，其特征在于，还包含：
金属硅化物层，该金属硅化物层位于该沟槽的一表面上。
20.依据权利要求18所述的半导体装置，其特征在于，该沟槽的截面具有一底面，该底面的最低点低于该外延结构截面的最宽处。
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