CN109786378B - 集成电路器件 - Google Patents

集成电路器件 Download PDF

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Publication number
CN109786378B
CN109786378B CN201811337662.2A CN201811337662A CN109786378B CN 109786378 B CN109786378 B CN 109786378B CN 201811337662 A CN201811337662 A CN 201811337662A CN 109786378 B CN109786378 B CN 109786378B
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gate
contact
guide pattern
substrate
integrated circuit
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CN109786378A (zh
Inventor
裵德汉
金商瑛
柳炳赞
俞宗昊
D-U.全
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract

本公开提供了集成电路器件。一种集成电路器件包括：基板，具有在第一方向上延伸的鳍型有源区域；栅极结构，在基板上与鳍型有源区域交叉并在垂直于第一方向且平行于基板的上表面的第二方向上延伸；引导图案，在第二方向上在栅极结构上延伸，并具有在第二方向上延伸的倾斜侧表面；源极/漏极区域，设置在栅极结构的两侧；以及第一接触，电连接到源极/漏极区域之一，并且第一接触的上部接触引导图案的倾斜侧表面。引导图案的上部在第一方向上的宽度小于引导图案的下部在第一方向上的宽度。

Description

集成电路器件
技术领域
本发明构思涉及集成电路器件及其制造方法。更具体地，本发明构思涉及包括鳍型有源区域的集成电路器件以及制造该集成电路器件的方法。
背景技术
随着电子产品变得轻、薄、短和小，对高度集成的电路器件的需求增加。在集成电路器件的按比例缩小中，产生晶体管的短沟道效应，因此集成电路器件的可靠性劣化。为了减小短沟道效应，已经提出了包括鳍型有源区域的集成电路器件。然而，随着设计规则的减小，用于与鳍型有源区域电连接的接触结构的尺寸也减小。
发明内容
根据本发明构思的一个方面，提供一种集成电路器件，该集成电路器件包括：基板，具有鳍型有源区域，该鳍型有源区域在平行于基板的上表面的第一方向上纵向地延伸；栅极结构，在基板上与鳍型有源区域交叉并在垂直于第一方向且平行于基板的上表面的第二方向上纵向地延伸；引导图案，设置在栅极结构的顶上并在第二方向上纵向地延伸；源极/漏极区域，设置在栅极结构的两侧；以及第一接触，电连接到源极/漏极区域之一。引导图案具有倾斜侧表面，并且引导图案的上部在第一方向上的宽度小于引导图案的下部在第一方向上的宽度。第一接触具有与引导图案的倾斜侧表面接触的上部。
根据本发明构思的另一方面，提供一种集成电路器件，该集成电路器件包括：基板，具有鳍型有源区域，该鳍型有源区域在平行于基板的上表面的第一方向上纵向地延伸；多个栅极结构，在基板上与鳍型有源区域交叉，每个栅极结构在垂直于第一方向且平行于基板的上表面的第二方向上纵向地延伸；多个引导图案，分别设置在所述多个栅极结构的顶上；源极/漏极区域，所述多个栅极结构中的在第一方向上彼此相邻的两个栅极结构位于源极/漏极区域的相反两侧；有源接触，电连接到源极/漏极区域；以及栅极隔离绝缘层。每个引导图案在第二方向上纵向地延伸并具有倾斜侧表面，并且每个引导图案的上部在第一方向上的宽度小于引导图案的下部在第一方向上的宽度。有源接触的上部插设在所述多个引导图案中的两个引导图案的相对的倾斜侧表面之间，所述两个引导图案分别设置在所述多个栅极结构中的在第一方向上彼此相邻的两个栅极结构上。栅极隔离绝缘层在基板上在第一方向上纵向地延伸并接触所述多个栅极结构的一端。所述多个引导图案中的至少一个在栅极隔离绝缘层上在第二方向上纵向地延伸。
根据本发明构思的另一方面，提供一种集成电路器件，该集成电路器件包括：基板，具有鳍型有源区域，该鳍型有源区域在平行于基板的上表面的第一方向上纵向地延伸；栅极结构，在基板上与鳍型有源区域交叉，在垂直于第一方向且平行于基板的上表面的第二方向上纵向地延伸，并包括栅电极和设置在栅电极的两个侧表面上的栅极间隔物；引导图案，设置在栅极结构的顶上并在第二方向上纵向地延伸；源极/漏极区域，设置在栅极结构的两侧；以及第一接触，电连接到源极/漏极区域之一。引导图案具有倾斜侧表面。引导图案的上部在第一方向上的宽度小于引导图案的下部在第一方向上的宽度。第一接触具有接触栅极间隔物的侧面的下部以及接触引导图案的倾斜侧表面的上部。
根据本发明构思的另一方面，提供一种集成电路器件，该集成电路器件包括：基板，具有在平行于基板的上表面的第一方向上纵向地延伸的鳍型有源区域；栅极结构，在基板上与鳍型有源区域交叉，该栅极结构包括在垂直于第一方向且平行于基板的上表面的第二方向上纵向地延伸的栅电极；引导图案，设置在栅极结构的顶上并在第二方向上纵向地延伸；源极/漏极区域，设置在栅极结构的两侧；以及接触，电连接到源极/漏极区域之一。引导图案在垂直于基板的上表面且平行于第一方向的垂直平面中具有在远离栅极结构的向上方向上逐渐变小的截面，使得引导图案的上部在所述第一方向上的宽度小于引导图案的下部在所述第一方向上的宽度。该接触具有在引导图案旁边设置为在第一方向上与其横向地并列的上部以及在栅极结构旁边设置为在第一方向上与其横向地并列的下部，该接触的上部在所述垂直平面中具有在朝向基板的上表面的向下方向上逐渐变小的截面。
根据本发明构思的另一方面，提供一种制造集成电路器件的方法，该方法包括：在基板上形成鳍型有源区域以在第一方向上延伸；在基板上形成与鳍型有源区域交叉并在垂直于第一方向的第二方向上延伸的多个栅极结构，并形成填充所述多个栅极结构之间的空间的栅极间绝缘层；在所述多个栅极结构和栅极间绝缘层上形成在第二方向上延伸并具有倾斜侧表面的多个引导图案；在栅极间绝缘层上形成绝缘层间层以填充所述多个引导图案之间的空间；在所述多个栅极结构当中的两个相邻的栅极结构之间以及在所述多个引导图案当中的两个相邻的引导图案之间形成第一接触孔；扩大第一接触孔直到所述两个相邻的栅极结构的侧表面和所述两个相邻的引导图案的倾斜侧表面被暴露；以及在扩大的第一接触孔中形成第一接触。
附图说明
从以下结合附图对其示例的详细描述，本发明构思将被更清楚地理解，附图中：
图1是根据本发明构思的集成电路器件的示例的布局图；
图2是沿着图1的线A-A'和线B-B'截取的截面图；
图3是沿着图1的线C-C'和线D-D'截取的截面图；
图4是沿着图1的线E-E'截取的截面图；
图5和图6是根据本发明构思的集成电路器件的示例的截面图；
图7是根据本发明构思的集成电路器件的示例的截面图；
图8是根据本发明构思的集成电路器件的示例的布局图；
图9是沿着图8的线F-F'截取的截面图；
图10、图11、图12、图13、图14、图15、图16、图17和图18是集成电路器件在其制造过程中的截面图，并一起示出根据本发明构思的制造该集成电路器件的方法的示例。
具体实施方式
将参照图1-图4详细描述根据本发明构思的集成电路器件100的示例。为了方便起见，在附图中仅示出集成电路器件100的一部分。这里以及在整个说明书中，为了易于描述，单个的元件可以被提及，这样的描述将被理解为应用于如附图所示的多个这样的元件中的每个。此外，术语“延伸”将通常被理解为指的是特定元件或特征(尤其是线性元件或特征)的纵长尺寸或纵向方向。
参照图1至图4，鳍型有源区域FA可以从基板110的上表面110F1突出。鳍型有源区域FA可以在平行于基板110的上表面110F1的第一方向(图1中的X方向)上延伸。如在本领域中被很好地理解的，“鳍型”区域是指其长度实质上大于其宽度的直立结构。
基板110的示例是包括IV族半导体(诸如Si或Ge)、IV-IV族化合物半导体(诸如SiGe或SiC)、或III-V族化合物半导体(诸如GaAs、InAs或InP)的那些。此外，基板110可以包括掺杂有杂质的导电区域阱或掺杂有杂质的结构。鳍型有源区域FA可以是构成p沟道金属氧化物半导体(PMOS)晶体管或n沟道金属氧化物半导体(NMOS)晶体管的有源区域。
覆盖鳍型有源区域FA的两个侧表面的下部的隔离层112可以设置在基板110的上表面110F1上。在鳍型有源区域FA和隔离层112上，栅极结构120可以设置为在与基板110的上表面110F1平行且垂直于第一方向的第二方向(图2的Y方向)上延伸。栅极结构120可以包括栅电极122、栅极绝缘层124、栅极覆盖层126和栅极间隔物128。
每个栅电极122可以对应于在第二方向(图1中的Y方向)上延伸的相应栅极线GL。栅电极122可以包括掺杂的多晶硅、金属或其组合。例如，栅电极122可以包括铝(Al)、铜(Cu)、钛(Ti)、钽(Ta)、钨(W)、钼(Mo)、TaN、NiSi、CoSi、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、TiAlC、或任何上述金属的组合。然而，本发明构思不限于此。栅电极122可以包括功函数含金属层和间隙填充金属层。功函数含金属层可以包括Ti、W、钌(Ru)、铌(Nb)、Mo、铪(Hf)、镍(Ni)、钴(Co)、铂(Pt)、镱(Yb)、铽(Tb)、镝(Dy)、铒(Er)和钯(Pd)当中的至少一种金属。间隙填充金属层可以包括W层或Al层。栅电极122可以包括TiAlC/TiN/W的堆叠结构、TiN/TaN/TiAlC/TiN/W的堆叠结构、或TiN/TaN/TiN/TiAlC/TiN/W的堆叠结构。然而，本发明构思不限于此。
每个栅极绝缘层124可以在第二方向上在栅电极122的底表面和侧表面上延伸。栅极绝缘层124可以插设在栅电极122与鳍型有源区域FA之间以及在栅电极122与隔离层112的上表面之间。栅极绝缘层124可以包括硅氧化物层、硅氮氧化物层、具有比硅氧化物层的介电常数高的介电常数的高k电介质层、或任何上述层的组合。高k电介质层可以包括金属氧化物或金属氮氧化物。可用作栅极绝缘层124的高k电介质层可以包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、锆氧化物、铝氧化物、HfO2-Al2O3混合物、或任何上述材料的组合。然而，本发明构思不限于此。
每个栅极覆盖层126可以设置在栅电极122上。栅极覆盖层126可以在第二方向(图2中的Y方向)上延伸，同时覆盖栅电极122的上表面。在示例中，栅极覆盖层126包括硅氮化物。
每个栅极间隔物128可以在栅电极122的两侧和栅极覆盖层126的两侧上延伸。栅极间隔物128可以在栅电极122的两个侧表面上在栅电极122的延伸方向上延伸。栅极绝缘层124可以插设在栅电极122和栅极间隔物128之间。在示例中，栅极间隔物128可以包括SiOx、SiNx、SiOxNy、SiCxNy、SiOxCyNz、或任何上述材料的组合。
图2示出其中栅极间隔物128由单层组成的示例。在另一些示例中，栅极间隔物128包括不同材料的多个层。例如，栅极间隔物128可以包括顺序地堆叠在栅电极122的侧表面上的第一间隔物层、第二间隔物层和第三间隔物层。在示例中，第一间隔物层和第三间隔物层可以包括硅氮化物、硅氧化物或硅氮氧化物。第二间隔物层可以包括具有比第一间隔物层的介电常数低的介电常数的绝缘材料。在另一示例中，第二间隔物层可以是空气空间。
源极/漏极区域114可以在栅极结构120的两侧设置在鳍型有源区域FA中。源极/漏极区域114可以包括掺杂的SiGe层、掺杂的Ge层、掺杂的SiC层或掺杂的InGaAs层。然而，本发明构思不限于此。源极/漏极区域114可以通过去除栅极结构120的两侧的鳍型有源区域FA的部分以形成凹陷R1以及通过外延工艺生长填充凹陷R1的半导体层来形成。在示例中，如图3所示，源极/漏极区域114可以具有多边形形状，该多边形形状具有多个倾斜表面114F。
例如，当鳍型有源区域FA是用于NMOS晶体管的有源区域时，源极/漏极区域114可以包括掺杂的SiC，并且当鳍型有源区域FA是用于PMOS晶体管的有源区域时，源极/漏极区域114可以包括掺杂的SiGe。
此外，源极/漏极区域114可以包括具有不同成分的多个半导体层。在示例中，源极/漏极区域114包括顺序地填充凹陷R1的下半导体层(未示出)、上半导体层(未示出)和覆盖半导体层(未示出)。下半导体层、上半导体层和覆盖半导体层可以每个包括SiGe，并且Si的量和/或Ge的量可以彼此不同。
如图4所示，覆盖源极/漏极区域114的栅极间绝缘层132可以设置在栅极结构120和相邻的栅极结构120之间。栅极间绝缘层132可以包括硅氮化物、硅氧化物或硅氮氧化物。
如图1所示，栅极线GL可以在第一方向上以均匀的间隔彼此分隔并在第二方向上延伸。栅极线GL可以在第二方向(Y方向)上以均匀的间隔彼此分隔，使栅极切割区域CR被插设在它们之间。图1示出其中栅极切割区域CR在第一方向(X方向)上延伸从而与五个连续设置的栅极线GL相交的示例。然而，本发明构思不限于此。栅极切割区域CR的长度可以根据集成电路器件100的期望规格而变化。
栅极隔离绝缘层134可以设置在栅极切割区域CR中。栅极隔离绝缘层134可以设置为接触栅极结构120的一端。栅极隔离绝缘层134可以具有与栅极结构120的上表面处于相同水平面的上表面。栅极隔离绝缘层134可以包括硅氮化物、硅氧化物或硅氮氧化物。
蚀刻停止层136可以设置在栅极结构120、栅极间绝缘层132和栅极隔离绝缘层134上。蚀刻停止层136可以包括硅氮化物、硅氧化物或硅氮氧化物。
引导图案140可以设置在蚀刻停止层136上。如图1所示，引导图案140可以分别设置在多条栅极线GL上，并可以每个在第二方向(Y方向)上延伸。引导图案140可以与栅极切割区域CR重叠。引导图案140可以在栅极隔离绝缘层134上在第二方向上延伸。
每个引导图案140可以在垂直于基板110的上表面110F1且平行于第一方向的垂直平面(附图中的X-Z平面)中具有在远离栅极结构120的向上方向上逐渐变小的截面，使得引导图案140的上部的宽度小于引导图案140的下部的宽度。
为此，每个引导图案140可以包括在第二方向(Y方向)上延伸的一对倾斜侧表面140S。该对倾斜侧表面140S可以以第一倾斜角相对于基板110的上表面110F1倾斜，并且第一倾斜角可以小于约80°。此示例中的倾斜表面是平坦表面，但是术语“倾斜表面”不限于描述平坦表面。而是，术语“倾斜表面”可以指具有不垂直的斜度的表面。
引导图案140的上表面在第一方向上的第一宽度W11可以小于引导图案140的底表面在第一方向上的第二宽度W12。该对倾斜侧表面140S的底部可以与栅极间隔物128的外侧表面对准，使蚀刻停止层136插设在其间。也就是，引导图案140的底表面的第二宽度W12可以等于栅极结构120在第一方向上的宽度，并且引导图案140可以与栅极结构120重叠，即可以与栅极结构120垂直地并列。这里以及在下面的描述中，术语“宽度”将指的是垂直于元件或特征的纵长尺寸或纵向尺寸的尺寸。因此，在此示例中，引导图案140的宽度指的是引导图案140在第一(X)方向上的尺寸。
引导图案140可以包括硅氮化物、硅氧化物或硅氮氧化物。引导图案140可以包括相对于蚀刻停止层136和/或栅极间绝缘层132具有蚀刻选择性的材料。在示例中，蚀刻停止层136和栅极间绝缘层132中的每个包括硅氧化物，引导图案140包括硅氮化物。
绝缘层间层138可以设置在蚀刻停止层136和引导图案140上。绝缘层间层138可以接触引导图案140的倾斜侧表面140S。绝缘层间层138可以包括硅氮化物、硅氧化物、硅氮氧化物、正硅酸乙酯(TEOS)层、或具有约2.2至约2.4的介电常数的超低K(ULK)层。
有源接触CA设置在源极/漏极区域114上，栅极接触CB可以设置在栅极结构120上。
有源接触CA可以包括有源接触插塞152和导电的阻挡层154。在示例中，有源接触插塞152包括Co、W、Ni、Ru、Cu、Al、任何上述金属的硅化物、以及任何上述金属的合金中的至少一种。例如，有源接触插塞152可以是Co。导电的阻挡层154可以设置为在其圆周方向上围绕有源接触插塞152。导电的阻挡层154可以插设在有源接触插塞152和栅极间隔物128之间、在有源接触插塞152和引导图案140之间以及在有源接触插塞152和源极/漏极区域114之间。导电的阻挡层154可以包括Ti、Ta、TiN、TaN或任何上述材料的组合。
根据示例，每个有源接触CA包括在下文被分别称为第一接触CA1和第二接触CA2的第一部分和第二部分。第一接触CA1可以设置在两个相邻的栅极结构120之间的源极/漏极区域114上。第二接触CA2可以在第二方向上从所述两个相邻的栅极结构120延伸到栅极隔离绝缘层134的一侧上。
第一接触CA1可以进而包括在比栅极结构120的上表面低的水平面处的第一部分CA1a以及在比第一部分CA1a高的水平面处的第二部分CA1b。第一接触CA1的第一部分CA1a的侧表面可以接触栅极间隔物128并可以垂直于基板110的上表面110F1延伸，即下部的第一部分CA1a可以在栅极结构120旁边设置为在第一方向上与其横向地并列。第一接触CA1的第二部分CA1b的侧表面可以接触引导图案140，并可以相对于基板110的上表面110F1倾斜以与引导图案140的倾斜侧表面140S共形或对应，即平行于引导图案140的倾斜侧表面140S延伸。因此，上部的第二部分CA1b可以在引导图案140旁边设置为在第一方向上与其横向地并列。第一接触CA1的第二部分CA1b的侧表面可以相对于基板110的上表面110F1以小于80°的倾斜角倾斜。因此，第一接触CA1的第二部分CA1b(上部)可以在X-Z平面中具有在朝向基板110的上表面110F1的向下方向上逐渐变小的截面。
如图2所示，第一接触CA1的第一部分CA1a的侧表面和第一接触CA1的第二部分CA1b的侧表面可以连接而不发生其斜率的急剧变化(此状态可以在下文称为“平缓地连接”)。也就是，根据本发明构思的一方面，第一接触CA1的位于第一部分CA1a的侧表面与第二部分CA1b的侧表面相遇处的区域不包括台阶部分、突起或弯折(kink)。由于引导图案140的倾斜侧表面140S的底部与栅极间隔物128的侧表面对准，所以第一部分CA1a的接触栅极间隔物128的侧表面可以与第二部分CA1b的接触倾斜侧表面140S的侧表面连续地连接。
如图2所示，第一接触CA1的第一部分CA1a具有第一宽度W21，第一接触CA1的第二部分CA1b具有第二宽度W22，第二宽度W22可以大于第一宽度W21。也就是，第一接触CA1可以具有其中上部宽度(例如第二宽度W22)大于下部宽度(例如第一宽度W21)的轮廓。
在第一接触CA1通过用诸如Co的金属材料填充第一接触孔CA1H来形成的情况下，当第一接触孔CA1H的宽度小和/或在第一接触孔CA1H的侧表面上形成包括侧表面中的斜率的快速变化的弯折时，金属材料不能完全填充第一接触孔CA1H或者金属材料的质量不会是高的。然而，根据本发明构思的示例，第一接触孔CA1H具有这样的轮廓，其中第一接触孔CA1H的上部宽度大于第一接触孔CA1H的下部宽度，并且第一接触孔CA1H的侧表面被平缓地连接而没有弯折。因此，金属材料完全填充第一接触孔CA1H，或者形成在第一接触孔CA1H中的第一接触CA1的质量可以是高的。
第二接触CA2可以设置在两个相邻的栅极结构120之间的源极/漏极区域114上，在第二方向上延伸，并可以接触栅极隔离绝缘层134。如图1所示，在平面图中，第二接触CA2设置在沿第一方向(X方向)彼此间隔开的两条栅极线GL之间以及沿第二方向(Y方向)与所述两条栅极线GL间隔开的两条栅极线GL之间，并且第二接触CA2与栅极切割区域CR重叠。
第二接触CA2可以包括面对或接触栅极结构120的侧表面的第三部分CA2a和面对或接触栅极隔离绝缘层134的第四部分CA2b。第二接触CA2的第三部分CA2a的第一宽度W31可以小于第二接触CA2的第四部分CA2b的第二宽度W32。
在一示例中，第一接触CA1和第二接触CA2通过如下形成：形成暴露源极/漏极区域114的上表面的一部分的第一接触孔CA1H和第二接触孔CA2H；扩大第一接触孔CA1H和第二接触孔CA2H；以及在扩大的第一接触孔CA1H和第二接触孔CA2H中填充金属材料。在扩大第一接触孔CA1H和第二接触孔CA2H的工艺中，由于栅极间隔物128和栅极隔离绝缘层134之间的蚀刻速率的差异，可以去除更多的栅极隔离绝缘层134。因此，第二接触CA2的第四部分CA2b的第二宽度W32可以大于第二接触CA2的第三部分CA2a的第一宽度W31。
每个栅极接触CB可以包括栅极接触插塞156和导电的阻挡层158。栅极接触插塞156可以包括Co、W、Ni、Ru、Cu、Al、任何上述金属的硅化物、或者任何上述金属的合金。在一示例中，栅极接触插塞156是Co。导电的阻挡层158可以在其圆周方向上围绕栅极接触插塞156。导电的阻挡层158可以插设在栅极接触插塞156和栅极间隔物128之间、在栅极接触插塞156和栅电极122之间、以及在栅极接触插塞156和引导图案140之间。导电的阻挡层158可以包括Ti、Ta、TiN、TaN或任何上述金属的组合。
根据示例，栅极接触CB可以包括第三接触CB1和第四接触CB2。第三接触CB1可以由于穿过引导图案140而设置在栅极结构120上。第四接触CB2可以设置在栅极结构120以及与该栅极结构120相邻的相邻栅极结构120上。第四接触CB2的侧表面的一部分可以被引导图案140围绕。如图1中示范性地示出的，在平面图中，第三接触CB1与一条栅极线GL重叠，并且第四接触CB2与在第一方向(X方向)上分隔的两条栅极线GL以及在所述两条栅极线GL之间的栅极间绝缘层132重叠。
选择性地，硅化物层(未示出)可以形成在源极/漏极区域114与有源接触CA之间。硅化物层可以包括金属硅化物，诸如Co硅化物、Ni硅化物或W硅化物。
通路(未示出)和上布线(未示出)可以形成在引导图案140和绝缘层间层138上。通路可以设置在有源接触CA与上布线之间或者在栅极接触CB与上布线之间。上布线可以包括处于不同水平面的多个布线层的堆叠结构。还可以形成围绕通路和上布线的上绝缘层间层(未示出)。
根据上述集成电路器件100，具有倾斜侧表面140S的引导图案140可以设置在栅极结构120和与栅极结构120接触的第一接触CA1上，并且引导图案140可以具有比下部宽的上部以及平缓地连接到下侧表面的上侧表面。因此，在用金属材料填充第一接触孔CA1H的工艺中，金属材料可以完全填充第一接触孔CA1H，或者形成在第一接触孔CA1H中的第一接触CA1的膜质量可以是高的。因此，第一接触CA1的尺寸可以是最小的，并且仍可以提供可靠的电连接。
现在将参照图5和图6详细描述根据本发明构思的集成电路器件100A的另一些示例。在图5和图6中，与图1至图4中的那些元件相同的元件由相同的附图标记表示。除了没有形成蚀刻停止层136之外，图5和图6的集成电路器件100A类似于图1至图4中描述的集成电路器件100。
参照图5和图6，引导图案140可以直接设置在栅极结构120上。引导图案140的底表面可以接触栅极覆盖层126的上表面和栅极间隔物128的上表面。
第一接触CA1的第一部分CA1a接触栅极间隔物128并可以垂直于基板110的上表面110F1延伸。第一接触CA1的第二部分CA1b接触引导图案140的倾斜侧表面140S并可以相对于基板110的上表面110F1以小于约80°的第一倾斜角倾斜。引导图案140的底部的第二宽度W12可以与栅极结构120的宽度基本上相同，并且倾斜侧表面140S的底表面可以与栅极结构120的侧表面对准。因此，第一接触CA1的第一部分CA1a的侧表面和第二部分CA1b的侧表面可以平缓地连接而没有弯折，该弯折在第一接触CA1的第一部分CA1a的侧表面与第二部分CA1b的侧表面之间的过渡点处提供斜率的快速变化。
图7示出根据本发明构思的集成电路器件100B的另一示例。在图7中，与图1至图6中的那些元件相同的元件由相同的附图标记表示。除了引导图案140A的形状之外，图7的集成电路器件100B类似于图1至图4中描述的集成电路器件100。
参照图7，引导图案140A可以包括在第二方向(Y方向)上延伸的一对倾斜侧表面140SA。在引导图案140A中，引导图案140A的下部的宽度W12可以大于上部的宽度W11。每个倾斜侧表面140SA的至少一部分可以是弯曲(凸起)表面。该对倾斜侧表面140SA可以设置为使得相对于基板110的上表面110F1的斜率逐渐减小。第一接触CA1的第一部分CA1a的侧表面可以平缓地连接到第一接触CA1的第二部分CA1b的与倾斜侧表面140SA接触的侧表面。第一接触CA1的第二部分CA1b的侧表面可以是与倾斜侧表面140SA互补的凹入表面。因此，类似于之前的示例，引导图案140A在垂直于基板110的上表面110F1且平行于第一方向的垂直平面(附图中的X-Z平面)中具有在远离栅极结构120的向上方向上逐渐变小的截面。
根据上述集成电路器件100B，在通过用金属材料填充第一接触孔CA1H而形成第一接触CA1的工艺中，金属材料可以完全填充第一接触孔CA1H，或者形成在第一接触孔CA1H中的第一接触CA1的膜质量可以是高的。因此，第一接触CA1的尺寸可以是最小的，并且仍可以提供可靠的电连接。
图8是根据本发明构思的集成电路器件100C的另一些示例的布局图。图9是沿着图8的线F-F'截取的截面图。在图8中，为方便起见仅示出集成电路器件100C的一部分。
参照图8和图9，隔离结构IS可以在第二方向(Y方向)上在多条栅极线GL的一侧延伸。隔离结构IS可以形成在栅极结构120的一侧，在形成于鳍型有源区域FA中的沟槽110T的内表面上。隔离结构IS可以包括硅氧化物、硅氮化物或硅氮氧化物。
图9示出隔离结构IS由单层形成。然而，隔离结构IS可以替代地包括包含多个层的堆叠结构。例如，隔离结构IS可以包括共形地形成在沟槽110T的内表面上的界面层(未示出)以及在界面层上填充沟槽110T的掩埋绝缘层(未示出)。根据另一示例，隔离结构IS包括下掩埋层(未示出)和上掩埋层(未示出)，该下掩埋层填充沟槽110T并具有在与鳍型有源区域FA的上表面的水平面相似的水平面处的上表面，该上掩埋层设置在下掩埋层上并具有在与栅极结构120的上表面的水平面相似的水平面处的上表面。根据另一示例，隔离结构IS包括在第二方向(Y方向)上延伸同时覆盖鳍型有源区域FA的上表面和两个侧表面的一对绝缘间隔物(未示出)以及填充该对绝缘间隔物之间的沟槽110T并在第二方向上延伸的掩埋绝缘层(未示出)。然而，隔离结构IS不限于这些特定示例中的任何一个。
在隔离结构IS上，引导图案140可以在第二方向上延伸。在图8所示的平面图中，多条栅极线GL在第一方向上以均匀的间隔彼此隔开。所述多条栅极线GL中的一条栅极线GL和与该栅极线GL相邻的隔离结构IS可以以与所述多条栅极线GL彼此间隔开的间隔相同的间隔彼此隔开。引导图案140可以与所述多条栅极线GL和隔离结构IS重叠。
图10至图18示出根据本发明构思的制造集成电路器件的方法。
在图10至图18中，按工艺顺序示出与沿着图1的线A-A'和线B-B'截取的截面对应的截面。在图10至18中，与图1至图9中的那些元件类似的元件由相同的附图标记表示。
参照图10，从基板110的上表面110F1垂直地突出并在一个方向(图10的X方向)上延伸的鳍型有源区域FA可以通过蚀刻掉基板110的有源区域的一部分来形成。
覆盖鳍型有源区域FA的两个侧表面的隔离层112可以形成在基板110上。尽管没有示出，但是共形地覆盖鳍型有源区域FA的侧表面的界面层(未示出)可以进一步形成在鳍型有源区域FA上从而插设在隔离层112和鳍型有源区域FA之间。
牺牲栅极214和牺牲栅极绝缘层图案212可以通过在基板110上顺序地形成牺牲栅极绝缘层(未示出)、牺牲栅极导电层(未示出)和硬掩模图案216以及通过使用硬掩模图案216作为蚀刻掩模来图案化牺牲栅极导电层和牺牲栅极绝缘层来形成。
通过使用原子层沉积(ALD)工艺或化学气相沉积(CVD)工艺形成覆盖硬掩模图案216、牺牲栅极214和牺牲栅极绝缘层图案212的间隔物绝缘层(未示出)以及对间隔物绝缘层执行各向异性蚀刻工艺，可以在硬掩模图案216的侧表面、牺牲栅极214的侧表面和牺牲栅极绝缘层图案212的侧表面上形成栅极间隔物128。在一示例中，栅极间隔物128由硅氮化物形成。然而，本发明构思不限于此。
在下文，牺牲栅极绝缘层图案212、牺牲栅极214、硬掩模图案216和栅极间隔物128将统称为牺牲栅极结构210。
参照图11，凹陷R1通过蚀刻牺牲栅极结构210的两侧的鳍型有源区域FA的一部分而形成，并且源极/漏极区域114可以形成在凹陷R1中。
根据示例，源极/漏极区域114可以通过使用鳍型有源区域FA的暴露到凹陷R1的侧表面和基板110的上表面作为籽晶层经由外延工艺形成。外延工艺可以是气相外延(VPE)工艺、诸如超高真空化学气相沉积(UHV-CVD)工艺的CVD工艺、分子束外延工艺、或以上工艺的组合。在外延工艺中，作为形成源极/漏极区域114所需的前体，可以使用液态或气态前体。
通过控制外延工艺中的生长条件，源极/漏极区域114可以形成为具有各种形状。在一示例中，源极/漏极区域114可以形成为具有多边形的形状，其中倾斜表面114F(参照图3)形成为相对于彼此界定给定角度。然而，源极/漏极区域114的形状不限于此。取决于鳍型有源区域FA的材料、源极/漏极区域114的材料、形成在基板110上的晶体管的种类以及外延工艺的条件，源极/漏极区域114可以具有各种形状。
然后，栅极间绝缘层132可以通过在基板110上形成覆盖栅极间隔物128和硬掩模图案216的绝缘层(未示出)以及平坦化该绝缘层直到栅极间隔物128的上表面和硬掩模图案216的上表面被暴露来形成。
参照图12，限定在栅极间隔物128的侧表面之间的栅极空间(未示出)通过去除硬掩模图案216(参照图11)、牺牲栅极214(参照图11)和牺牲栅极绝缘层图案212(参照图11)来形成。然后，栅极绝缘层124可以沿着限定栅极空间的侧面和底部的表面形成。
然后，栅电极122可以通过在栅极绝缘层124上形成填充剩余的栅极空间的导电层(未示出)并蚀刻该导电层的上部来形成。然后，填充栅极空间的栅极覆盖层126可以通过在栅电极122和栅极间绝缘层132上形成填充栅极空间的剩余部分的绝缘层(未示出)以及去除该绝缘层的上部直到栅极间绝缘层132或栅极间隔物128的上表面被暴露来形成。
去除牺牲栅极结构210的工艺的示例是湿蚀刻工艺。用于湿蚀刻的蚀刻剂的示例包括HNO3、DHF(稀释的氢氟酸)、NH4OH、四甲基氢氧化铵(TMAH)、KOH、或上述蚀刻剂的组合。
在下文，栅电极122、栅极绝缘层124、栅极覆盖层126和栅极间隔物128将被统称为栅极结构120。在用于形成栅极结构120的回蚀刻工艺中，栅极间绝缘层132的上部和栅极间隔物128的上部被去除特定的量，使得栅极间绝缘层132和栅极间隔物128的高度可以减小。
参照图13，包括暴露栅极切割区域CR(参照图1)的开口(未示出)的掩模图案(未示出)形成在栅极结构120和栅极间绝缘层132上，并且栅极结构120的与栅极切割区域CR重叠的部分可以通过使用掩模图案作为蚀刻掩模去除。然后，形成绝缘层(未示出)从而填充通过去除栅极结构120的一部分而获得的空间，并且栅极隔离绝缘层134可以通过回蚀刻该绝缘层的上部来形成。
根据另一示例，在形成栅极结构120之前，从牺牲栅极结构210去除与栅极切割区域CR重叠的部分，并形成填充被去除的空间的栅极隔离绝缘层134。然后，限定在栅极间隔物128的侧表面之间的栅极空间(未示出)通过去除硬掩模图案216(参照图11)、牺牲栅极214(参照图11)和牺牲栅极绝缘层图案212来形成，并且栅极绝缘层124、栅电极122和栅极覆盖层126可以顺序地形成在该栅极空间中。
参照图14，形成覆盖栅极结构120和栅极间绝缘层132的蚀刻停止层136，并且引导图案层140L可以形成在蚀刻停止层136上。引导图案层140L可以通过使用相对于蚀刻停止层136具有蚀刻选择性的材料来形成。在一示例中，蚀刻停止层136是硅氧化物，引导图案层140L是硅氮化物。
蚀刻停止层136和引导图案层140L还可以覆盖栅极隔离绝缘层134的上表面。
然后，掩模图案220可以形成在引导图案层140L上。掩模图案220形成为与栅极结构120重叠并可以在第二方向(Y方向)上延伸。
参照图15，引导图案140可以通过使用掩模图案220作为蚀刻掩模蚀刻引导图案层140L(参照图14)来形成。
引导图案140可以通过渐缩蚀刻方法形成。例如，引导图案140可以通过使用离子束蚀刻工艺或倾斜等离子体蚀刻工艺形成。引导图案140可以包括一对倾斜侧表面140S，并且上部宽度W11可以小于下部宽度W12。
蚀刻停止层136可以在形成引导图案140的工艺中不被蚀刻，从而防止蚀刻停止层136下面的栅极间隔物128或栅极间绝缘层132被损坏。
然后，可以去除掩模图案220。绝缘层间层138可以形成在引导图案140和蚀刻停止层136上。绝缘层间层138可以完全覆盖引导图案140的上表面。
参照图16，暴露源极/漏极区域114的上表面的一部分的第一接触孔CA1H和第二接触孔CA2H可以通过在绝缘层间层138上形成掩模图案(未示出)以及通过使用该掩模图案作为蚀刻掩模蚀刻绝缘层间层138、蚀刻停止层136和栅极间绝缘层132来形成。
此时，第一接触孔CA1H和第二接触孔CA2H中的每个可以具有小的宽度W4，使得栅极间隔物128的侧表面没有被暴露。在一示例中，第一接触孔CA1H和第二接触孔CA2H中的每个的宽度W4小于两个相邻的栅极结构120之间的距离。
第一接触孔CA1H可以暴露相邻的栅极结构120之间的源极/漏极区域114的上表面。第二接触孔CA2H暴露相邻的栅极结构120之间的源极/漏极区域114的上表面并可以穿过栅极隔离绝缘层134暴露隔离层112的上表面。
参照图17，栅极间隔物128的侧表面和引导图案140可以通过去除由第一接触孔CA1H和第二接触孔CA2H暴露的栅极间绝缘层132、栅极隔离绝缘层134和绝缘层间层138来暴露。
去除工艺可以是使第一接触孔CA1H和第二接触孔CA2H在横向方向上扩大的工艺。例如，去除工艺可以是蚀刻工艺，其中栅极间绝缘层132、栅极隔离绝缘层134和绝缘层间层138具有比栅极间隔物128和引导图案140更高的蚀刻速率。去除工艺可以是湿蚀刻工艺或干蚀刻工艺。
在蚀刻工艺中，当蚀刻栅极间绝缘层132、栅极隔离绝缘层134和绝缘层间层138时，蚀刻停止层136也可以被蚀刻，使得第一接触孔CA1H的侧面和第二接触孔CA2H的侧面在它们的上部和下部之间具有平缓的过渡。
在蚀刻工艺中，由于栅极隔离绝缘层134具有高的蚀刻速率，所以可以去除由第二接触孔CA2H暴露的大量的栅极隔离绝缘层134。因此，限定在栅极隔离绝缘层134的侧表面之间的第二接触孔CA2H的宽度W42可以大于限定在栅极间隔物128的侧表面之间的第二接触孔CA2H的宽度W41。也就是，如图17所示，限定在栅极隔离绝缘层134的侧表面之间的第二接触孔CA2H可以包括从相邻的引导图案140的倾斜侧表面140S的底部延伸的凹陷。
通常，根据等比例缩小集成电路器件的趋势，栅极线GL之间的距离减小，并且栅极线GL之间形成的接触的宽度减小。由于接触具有小的宽度，接触电阻增大或难以形成接触。因此，为了使接触的宽度最大化，采用使用栅极覆盖层126和栅极间隔物128作为自对准掩模的自对准接触。然而，为了在用于形成自对准接触的蚀刻工艺中防止栅电极122被损坏或者为了确保蚀刻工艺余量，需要栅极覆盖层126和栅极间隔物128具有大的高度。这增加了成功实施后续工艺的难度。
然而，根据按照本发明构思的方法的一方面，在形成具有小宽度的第一接触孔CA1H和第二接触孔CA2H之后，第一接触孔CA1H和第二接触孔CA2H横向地扩大，直到引导图案140的侧表面和栅极间隔物128的侧表面被暴露。因此，与使用自对准接触蚀刻方法的情况相比，栅极覆盖层126和栅极间隔物128可以具有小的高度。因此，可以提高后续工艺的精度。
参照图18，导电的阻挡层154可以通过使用Ti、Ta、TiN、TaN或上述材料的组合而形成在第一接触孔CA1H和第二接触孔CA2H中的每个的内表面上。
然后，通过在导电的阻挡层154上形成填充第一接触孔CA1H和第二接触孔CA2H的有源接触插塞152以及去除有源接触插塞152的上部和导电的阻挡层154的上部直到引导图案140的上表面被暴露，第一接触CA1和第二接触CA2可以分别形成在第一接触孔CA1H和第二接触孔CA2H中。
有源接触插塞152可以包括Co、W、Ni、Ru、Cu、Al、上述金属的硅化物、或上述金属的合金。在其中有源接触插塞152包括Co的示例中，由于第一接触孔CA1H和第二接触孔CA2H的轮廓，填充第一接触孔CA1H和第二接触孔CA2H的有源接触插塞152的膜质量可以是高的。
对比地，如果接触孔的上部的宽度小或者如果形成在接触孔的侧部处产生斜率的快速变化的结构诸如弯折或台阶，用于形成有源接触插塞152的钴源材料不能顺利地供应到接触孔中。结果，异常的金属层将形成在该结构上，和/或孔隙会形成在该结构周围。也就是，接触孔不会被钴金属层完全填充，或者接触孔中的钴金属层的膜质量会是差的。
然而，根据本发明构思，第一接触孔CA1H和第二接触孔CA2H可以由于倾斜侧表面140S而确保大的上部宽度。例如，如图18所示，第一接触孔CA1H的上部宽度W22大于下部宽度W21。此外，第一接触孔CA1H和第二接触孔CA2H可以具有拥有平缓变化的斜率的侧表面轮廓，例如没有任何弯折。因此，Co金属层完全填充第一接触孔CA1H和第二接触孔CA2H，或者至少该金属层在其作为接触的性能方面具有高的质量。
返回参照图4，暴露栅电极122的上表面的第三接触孔CB1H和第四接触孔CB2H可以通过在绝缘层间层138上形成掩模图案(未示出)以及通过使用该掩模图案作为蚀刻掩模部分地去除引导图案140和绝缘层间层138而形成。引导图案140可以通过第三接触孔CB1H和第四接触孔CB2H暴露。
然后，导电的阻挡层158可以通过使用Ti、Ta、TiN、TaN或上述金属的组合形成为衬垫(line)第三接触孔CB1H和第四接触孔CB2H中的每个。填充第三接触孔CB1H和第四接触孔CB2H的剩余部分的第三接触CB1和第四接触CB2可以通过在导电的阻挡层158上形成栅极接触插塞156而形成。栅极接触插塞156可以包括Co、W、Ni、Ru、Cu、Al、上述金属中的任何一种的硅化物、或任何上述金属的合金。这里以及在下面的描述中，与特定特征的材料结合使用的术语“包括”还可以表示该特征可以由该材料或来自所提供的组的材料组成，即该特征可以由指定的或列出的材料之一形成。
根据另一些示例，在形成第一接触孔CA1H和第二接触孔CA2H之后，并且在形成第一接触CA1和第二接触CA2之前，形成第三接触孔CB1H和第四接触孔CB2H，然后形成分别填充第一接触孔CA1H、第二接触孔CA2H、第三接触孔CB1H和第四接触孔CB2H的第一接触CA1、第二接触CA2、第三接触CB1和第四接触CB2。
根据制造集成电路器件100的方法，在形成具有倾斜侧表面140S的引导图案140之后，形成第一接触孔CA1H和第二接触孔CA2H，并且第一接触孔CA1H和第二接触孔CA2H被扩大直到引导图案140的倾斜侧表面140S被暴露。因此，可以获得其上部宽度增大并具有平缓侧表面轮廓的第一接触孔CA1H和第二接触孔CA2H。当第一接触孔CA1H和第二接触孔CA2H用诸如Co的金属材料填充时，所得到的第一接触CA1和第二接触CA2将是高质量的。
此外，在扩大第一接触孔CA1H和第二接触孔CA2H的工艺中，当引导图案140A的上部局部地进一步暴露于蚀刻剂并被去除时，引导图案140A的上边缘可以被倒圆。在这样的情况下，可以获得包括引导图案140A的集成电路器件100B，引导图案140A包括参照图7描述的弯曲的倾斜侧表面140SA。
此外，尽管图14示出其中蚀刻停止层136形成在栅极结构120上的示例，但是在另一示例中，引导图案层140L可以直接形成在栅极结构120和栅极间绝缘层132上。在这样的情况下，参照图5和图6描述的集成电路器件100A可以通过与以上参照图10-图18另外地描述的方法类似的方法形成。
尽管已经参照其示例具体示出和描述了本发明构思，但是将理解，可以对这样的示例进行形式和细节上的各种改变，而没有脱离由权利要求书限定的发明构思的精神和范围。
本申请要求于2017年11月14日在韩国知识产权局提交的韩国专利申请第10-2017-0151723号的权益，其公开内容通过引用整体地结合于此。

Claims (20)

1.一种集成电路器件，包括：
基板，具有鳍型有源区域，该鳍型有源区域在平行于所述基板的上表面的第一方向上纵向地延伸；
栅极结构，在所述基板上与所述鳍型有源区域交叉并在垂直于所述第一方向且平行于所述基板的所述上表面的第二方向上纵向地延伸；
在所述基板上在所述第一方向上延伸的栅极隔离绝缘层，所述栅极隔离绝缘层接触所述栅极结构的沿所述第一方向设置的第一侧表面；
引导图案，设置在所述栅极结构和所述栅极隔离绝缘层之上，所述引导图案在所述第二方向上纵向地延伸并具有倾斜侧表面，并且所述引导图案的上部在所述第一方向上的宽度小于所述引导图案的下部在所述第一方向上的宽度；
源极/漏极区域，设置在所述栅极结构的两侧；以及
第一接触，电连接到所述源极/漏极区域之一并具有接触所述引导图案的所述倾斜侧表面的上部。
2.根据权利要求1所述的集成电路器件，其中所述倾斜侧表面相对于所述基板的所述上表面倾斜小于80°的角度。
3.根据权利要求1所述的集成电路器件，其中所述第一接触具有被限制到在所述栅极结构的上表面的水平面之下的水平面的第一部分以及在所述第一部分上的第二部分，
所述第一接触的所述第一部分的侧表面垂直于所述基板的所述上表面，并且
所述第一接触的所述第二部分的侧表面相对于所述基板的所述上表面倾斜从而具有与所述引导图案的所述倾斜侧表面的轮廓共形的轮廓。
4.根据权利要求3所述的集成电路器件，其中所述栅极结构包括：
栅电极，在所述基板上与所述鳍型有源区域交叉并在所述第二方向上纵向地延伸；
栅极覆盖层，设置在所述栅电极之上并在所述第二方向上纵向地延伸；以及
栅极间隔物，设置在所述栅电极和所述栅极覆盖层两者的侧表面上，
其中所述第一接触的所述第一部分的所述侧表面接触所述栅极间隔物，并且
所述第一接触的所述第二部分的所述侧表面接触所述引导图案的所述倾斜侧表面。
5.根据权利要求3所述的集成电路器件，其中所述第一接触的包含所述第一接触的所述第一部分和所述第一接触的所述第二部分的区域不包括台阶、突起或弯折。
6.根据权利要求3所述的集成电路器件，还包括插设在所述引导图案与所述栅极结构的所述上表面之间的蚀刻停止层，
其中所述第一接触的所述第一部分的所述侧表面和所述第一接触的所述第二部分的所述侧表面在设置于所述蚀刻停止层旁边而与其横向地并列的区域中相接。
7.根据权利要求6所述的集成电路器件，其中所述蚀刻停止层也插设在所述引导图案和所述栅极隔离绝缘层之间。
8.根据权利要求1所述的集成电路器件，其中所述引导图案与所述栅极结构和所述栅极隔离绝缘层重叠，并且
所述栅极隔离绝缘层具有处于与所述栅极结构的上表面相同的水平面处的上表面。
9.根据权利要求8所述的集成电路器件，还包括第二接触，所述第二接触电连接到所述源极/漏极区域之一并从所述栅极结构旁边的位置延伸到所述栅极隔离绝缘层旁边的位置，
其中所述第二接触具有面对所述栅极结构的侧表面的一个部分和面对所述栅极隔离绝缘层的侧表面的另一部分，并且
所述第二接触的所述一个部分在所述第一方向上的宽度小于所述第二接触的所述另一部分在所述第一方向上的宽度。
10.根据权利要求1所述的集成电路器件，其中所述引导图案直接设置在所述栅极结构上，并直接设置在所述栅极隔离绝缘层上。
11.根据权利要求1所述的集成电路器件，还包括以下中的至少一个：
第三接触，设置在所述栅极结构上并穿过所述引导图案；和
第四接触，设置在所述栅极结构和相邻的栅极结构上，所述第四接触的侧表面的一部分被所述引导图案覆盖。
12.根据权利要求1所述的集成电路器件，其中所述倾斜侧表面的至少一部分是弯曲的。
13.根据权利要求1所述的集成电路器件，还包括：
沟槽，在所述栅极结构的一侧且在所述鳍型有源区域中；
隔离结构，填充所述沟槽，在所述第一方向上与所述栅极结构分隔并在所述第二方向上纵向地延伸；和
第二引导图案，在所述第二方向上在所述隔离结构上纵向地延伸并具有倾斜侧表面，所述第二引导图案的上部在所述第一方向上的宽度小于所述第二引导图案的下部在所述第一方向上的宽度。
14.一种集成电路器件，包括：
基板，具有鳍型有源区域，该鳍型有源区域在平行于所述基板的上表面的第一方向上纵向地延伸；
多个栅极结构，在所述基板上与所述鳍型有源区域交叉，每个所述栅极结构在垂直于所述第一方向且与所述基板的所述上表面平行的第二方向上纵向地延伸；
多个引导图案，分别设置在所述多个栅极结构之上，每个所述引导图案在所述第二方向上纵向地延伸并具有倾斜侧表面，并且每个所述引导图案的上部在所述第一方向上的宽度小于所述引导图案的下部在所述第一方向上的宽度；
源极/漏极区域，所述多个栅极结构中的在所述第一方向上彼此相邻的两个栅极结构位于所述源极/漏极区域的相反两侧；
有源接触，电连接到所述源极/漏极区域，所述有源接触的上部插设在所述多个引导图案中的两个引导图案的相对的倾斜侧表面之间，所述两个引导图案分别设置在所述多个栅极结构中的在所述第一方向上彼此相邻的所述两个栅极结构上；以及
栅极隔离绝缘层，在所述基板上在所述第一方向上纵向地延伸并接触所述多个栅极结构的沿所述第一方向设置的第一侧表面，
其中所述多个引导图案中的至少一个在所述栅极隔离绝缘层上在所述第二方向上纵向地延伸。
15.根据权利要求14所述的集成电路器件，其中所述有源接触具有插设在所述多个栅极结构中的在所述第一方向彼此相邻的所述两个栅极结构之间的第一部分以及插设在所述两个引导图案之间的第二部分，
所述有源接触的所述第一部分的侧表面垂直于所述基板的所述上表面，并且
所述有源接触的所述第二部分的侧表面相对于所述基板的所述上表面倾斜从而具有与所述两个引导图案的所述倾斜侧表面的轮廓共形的轮廓。
16.根据权利要求14所述的集成电路器件，其中所述有源接触在所述第二方向上从所述多个栅极结构中的在所述第一方向上彼此相邻的所述两个栅极结构之间的位置纵向地延伸到所述两个栅极结构的端部之外的位置，
所述栅极隔离绝缘层设置在所述有源接触的两侧，并且
所述有源接触具有插设在所述多个栅极结构中的在所述第一方向上彼此相邻的所述两个栅极结构之间的一个部分以及设置在所述栅极隔离绝缘层旁边的另一部分，
所述有源接触的所述一个部分的宽度小于所述有源接触的所述另一部分的宽度。
17.根据权利要求14所述的集成电路器件，还包括设置在所述多个栅极结构中的一个栅极结构上的栅极接触，
其中所述栅极接触的侧表面的至少一部分被设置在所述多个栅极结构中的所述一个栅极结构上的所述引导图案覆盖。
18.一种集成电路器件，包括：
基板，具有鳍型有源区域，该鳍型有源区域在平行于所述基板的上表面的第一方向上纵向地延伸；
栅极结构，在所述基板上与所述鳍型有源区域交叉，所述栅极结构包括栅电极，所述栅电极在垂直于所述第一方向且平行于所述基板的所述上表面的第二方向上纵向地延伸；
在所述基板上在所述第一方向上延伸的栅极隔离绝缘层，所述栅极隔离绝缘层接触所述栅极结构的沿所述第一方向设置的第一侧表面；
引导图案，设置在所述栅极结构和所述栅极隔离绝缘层之上，所述引导图案在所述第二方向上纵向地延伸；
源极/漏极区域，设置在所述栅极结构的两侧；以及
接触，电连接到所述源极/漏极区域之一，
其中所述引导图案在垂直于所述基板的所述上表面且平行于所述第一方向的垂直平面中具有在远离所述栅极结构的向上方向上逐渐变小的截面，使得所述引导图案的上部的宽度小于所述引导图案的下部的宽度，并且
所述接触具有在所述引导图案旁边设置为在所述第一方向上与其横向并列的上部以及在所述栅极结构旁边设置为在所述第一方向上与其横向并列的下部，所述接触的所述上部在所述垂直平面中具有在朝向所述基板的所述上表面的向下方向上逐渐变小的截面。
19.根据权利要求18所述的集成电路器件，其中所述引导图案具有相对于所述基板的所述上表面倾斜地延伸的平坦侧表面，并且所述接触的所述上部具有倾斜地延伸并平行于所述引导图案的所述平坦侧表面的平坦侧表面。
20.根据权利要求18所述的集成电路器件，其中所述引导图案具有凸起的侧表面，并且所述接触的所述上部具有与所述引导图案的所述凸起的侧表面互补的凹入的侧表面。
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