CN105448862A - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
CN105448862A
CN105448862A CN201410514075.1A CN201410514075A CN105448862A CN 105448862 A CN105448862 A CN 105448862A CN 201410514075 A CN201410514075 A CN 201410514075A CN 105448862 A CN105448862 A CN 105448862A
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material layer
wafer
layer
metal
top surface
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CN201410514075.1A
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CN105448862B (zh
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丁敬秀
何作鹏
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN201410514075.1A priority Critical patent/CN105448862B/zh
Priority to US14/861,139 priority patent/US9754893B2/en
Publication of CN105448862A publication Critical patent/CN105448862A/zh
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Publication of CN105448862B publication Critical patent/CN105448862B/zh
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Abstract

一种半导体结构及其制作方法，其中半导体结构的制作方法包括：提供第一晶圆以及第二晶圆，第一晶圆内形成有第一金属层，第二晶圆内形成有第二金属层；在第一晶圆表面形成第一材料层；在第二晶圆表面形成第二材料层；对所述第一晶圆与第二晶圆进行对准处理以及键合处理，使第一材料层与第二材料层对准且表面相接触；在进行键合处理后，对所述第一材料层以及第二材料层进行加热处理，使第一材料层以及第二材料层相互熔融，提高第一金属层与第二金属层之间的对准精度。本发明利用第一材料层以及第二材料层相互熔融产生的表面张力，使第一材料层和第二材料层相互拉近，从而提高第一金属层和第二金属层之间的对准精度，减小键合偏移。

Description

半导体结构及其制作方法
技术领域
本发明涉及半导体制作领域技术，特别涉及一种半导体结构及其制作方法。
背景技术
随着半导体制作技术的飞速发展，半导体器件为了达到更快的运算速度、更大的资料存储量以及更多的功能，半导体芯片向更高集成度方向发展。而半导体芯片的集成度越高，半导体器件的特征尺寸(CD：CriticalDimension)越小。
三维集成电路(3DIC：Three-DimensionalIntegratedCircuit)是利用先进的芯片堆叠技术制备而成，其是将具不同功能的芯片堆叠成具有三维结构的集成电路。相较于二维结构的集成电路，三维集成电路的堆叠技术不仅可使三维集成电路信号传递路径缩短，还可以使三维集成电路的运行速度加快；简言之，三维集成电路的堆叠技术具有以下优点：满足半导体器件更高性能、更小尺寸、更低功耗以及更多功能的需求。
根据三维集成电路中芯片间的连接方法的不同，使堆叠的芯片能互连的技术分为金属引线键合(WireBonding)以及倒装芯片键合(WaferBonding)。其中，倒装芯片键合技术具有比金属引线键合技术更短的电连接路径，能够提供更优良的热特性、电特性以及更小的结构尺寸，因此倒装芯片键合技术是目前热门的关键技术之一，以实现不同芯片之间的临时性或永久性的粘结。
倒装芯片键合技术的键合类型包括：硅-硅直接键合技术、硅-玻璃静电键合技术以及-金属-金属键合技术，其中，金属-金属键合技术是研究的重点之一。金属-金属键合是指通过纯金属或合金，依靠金属间、金属与晶圆表面间的扩散、金属熔融等作用使两个晶圆面对面的键合在一起。
然而，采用现有技术提供的键合方法形成的半导体结构的性能有待提高。
发明内容
本发明解决的问题是提供一种半导体结构及其制作方法，提高晶圆之间的对准精度，以减小键合偏移。
为解决上述问题，本发明提供一种半导体结构的制作方法，包括：提供第一晶圆以及第二晶圆，所述第一晶圆内形成有第一金属层，且第一晶圆表面暴露出第一金属层顶部表面，所述第二晶圆内形成有第二金属层，且第二晶圆表面暴露出第二金属层顶部表面；在所述第一晶圆表面形成第一材料层，且所述第一材料层与第一金属层位于第一晶圆的同一面；在所述第二晶圆表面形成第二材料层，且所述第二材料层与第二金属层位于第二晶圆的同一面；对所述第一晶圆与第二晶圆进行对准处理以及键合处理，使第一材料层与第二材料层对准且表面相接触，所述第一金属层与第二金属层之间具有第一对准精度；在进行键合处理后，对所述第一材料层以及第二材料层进行加热处理，使第一材料层以及第二材料层相互熔融，所述第一金属层与第二金属层之间具有第二对准精度，且所述第二对准精度大于第一对准精度。
可选的，所述第一材料层覆盖于第一金属层顶部表面，所述第二材料层覆盖于第二金属层顶部表面，且所述第一材料层和第二材料层具有导电性。
可选的，所述第一材料层和第二材料层的材料包括锡银合金、锡铅合金、铋银合金、锡铋合金或锡铋铅合金。
可选的，在进行所述键合处理过程中，对第一晶圆背面施加压力。
可选的，形成第一材料层的工艺步骤包括：形成覆盖于第一晶圆表面的第一种子层，且所述第一种子层还覆盖于第一金属层顶部表面；在所述第一种子层表面形成第一光刻胶层，且第一光刻胶层表面暴露出位于第一金属层顶部表面的第一种子层；在所述暴露出的第一种子层表面形成第一导电层；去除所述第一光刻胶层以及位于第一光刻胶层底部的第一种子层。
可选的，在所述第一金属层顶部表面以外的第一晶圆表面形成第一材料层；在第二金属层顶部表面以外的第二晶圆表面形成第二材料层，且第一材料层和第二材料层的材料为绝缘材料或导电材料。
可选的，在进行所述键合处理之后，第一金属层顶部表面与第二金属层顶部表面之间具有间隙。
可选的，在进行所述键合处理过程中，对第一晶圆背面施加第一压力。
可选的，所述第一压力的大小为1千牛至20千牛。
可选的，在进行所述加热处理后，还包括步骤：对所述第一晶圆与第二晶圆进行二次键合处理，使第一金属层与第二金属层顶部表面相接触。
可选的，在进行所述二次键合处理过程中，对第一晶圆背面施加第二压力，所述第二压力方向为沿第一晶圆背面指向第一晶圆表面，且所述第二压力大于第一压力。
可选的，所述第二压力的大小为10千牛至100千牛。
可选的，所述键合处理在第一温度下进行，所述加热处理在第二温度下进行，且所述第一温度小于第二温度。
可选的，所述第一材料层和第二材料层的材料熔点大于第一温度且小于第二温度。
可选的，所述第一温度为100℃至250℃，所述第二温度为200℃至350℃。
可选的，所述第一晶圆内形成有第一对准结构，所述第二晶圆内形成有第二对准结构，通过使所述第一对准结构与第二对准结构对准，以进行对准处理。
本发明还提供一种半导体结构，包括：第一晶圆，位于第一晶圆内的第一金属层，所述第一金属层顶部表面被暴露出来，位于第一晶圆表面的第一材料层，且所述第一材料层与第一金属层位于第一晶圆的同一面；第二晶圆，位于第二晶圆内的第二金属层，所述第二金属层顶部表面被暴露出来，位于第二晶圆表面的第二材料层，且所述第二材料层与第二金属层位于第二晶圆的同一面；表面具有第一材料层的第一晶圆与表面具有第二材料层的第二晶圆相键合，第一材料层与第二材料层对准且表面相接触，所述第一金属层与第二金属层之间具有第二对准精度。
可选的，所述第一材料层覆盖于第一金属层顶部表面，所述第二材料层覆盖于第二金属层顶部表面，且所述第一材料层和第二材料层具有导电性。
可选的，所述第一材料层位于第一金属层顶部表面以外的第一晶圆表面，所述第二材料层位于第二金属层顶部表面以外的第二晶圆表面，且第一材料层和第二材料层的材料为绝缘材料或导电材料。
可选的，所述第一金属层顶部表面与第二金属层顶部表面相键合，第一金属层顶部表面与第二金属层顶部表面相接触。
与现有技术相比，本发明的技术方案具有以下优点：
本发明提供的半导体结构的制作方法中，在第一晶圆表面形成第一材料层，且所述第一材料层与第一金属层位于第一晶圆的同一面；在第二晶圆表面形成第二材料层，且所述第二材料层与第二金属层位于第二晶圆的同一面；对第一晶圆与第二晶圆进行对准处理以及键合处理，使第一材料层与第二材料层对准且表面相接触，所述第一金属层与第二金属层之间具有第一对准精度；在键合处理后，对第一材料层以及第二材料层进行加热处理，使第一材料层以及第二材料层相互熔融，加热处理后第一金属层与第二金属层之间具有第二对准精度。由于第一材料层以及第二材料层在熔融状态下具有表面张力，在所述表面张力的作用下使得第一材料层与第二材料层相互拉近，进而使得第一金属层与第二金属层相互拉近，使得第二对准精度大于第一对准精度，提高第一金属层与第二金属层之间、第一晶圆与第二晶圆之间的对准精度，减小甚至消除键合偏移问题，降低键合偏移问题带来的不良影响。
进一步，第一材料层和第二材料层的熔点大于键合处理的温度、且小于加热处理的温度，防止键合处理过程中第一材料层和第二材料层相互熔融，避免键合处理过程的温度对第一材料层和第二材料层产生不良影响，同时保证加热处理过程中第一材料层和第二材料层相互熔融。
进一步，本发明中第一温度为100℃至250℃，第二温度为200℃至350℃。若第一温度过低，即键合处理的温度过低，第一材料层与第二材料层表面之间的键合强度低，在后续工艺过程中容易发生分离问题；若第一温度过高，在较高温度下可能会导致第一材料层和第二材料层相互熔融；若第二温度过低，第一材料层和第二材料层熔融程度过低，所产生的表面张力过小，对提高第一金属层与第二金属层之间的对准精度的起到的有效效果较差；若第二温度过高，第一材料层和第二材料层变形严重，且会对半导体结构造成不良影响。进一步，在第一金属层顶部表面以外的第一晶圆表面形成第一材料层；在第二金属层顶部表面以外的第二晶圆表面形成第二材料层，避免相邻第一材料层之间、相邻第二材料层之间距离过小而造成的电连接问题。
更进一步，所述第一材料层覆盖于第一金属层顶部表面，所述第二材料层覆盖于第二金属层顶部表面，且所述第一材料层和第二材料层具有导电性；因此当第一材料层与第二材料层完全对准时，能够保证第一金属层与第二金属层完全对准，防止在第一晶圆表面形成第一材料层产生工艺误差、在第二晶圆表面形成第二材料层产生工艺误差，避免所述工艺误差对提高第一金属层与第二金属层之间的对准精度造成不良影响，进一步提高第二对准精度。
本发明还提供一种结构性能优越的半导体结构，表面具有第一材料层的第一晶圆与表面具有第二材料层的第二晶圆相键合，第一材料层与第二材料层对准且表面相接触，第一金属层与第二金属层之间具有第二对准精度，利用第一材料层和第二材料层，提高第一金属层与第二金属层之间的第二对准精度，使得第一晶圆与第二晶圆具有较高的对准精度，提高半导体结构的性能。
附图说明
图1为一实施例提供的半导体结构的结构示意图；
图2至图9为本发明另一实施例提供的半导体结构形成过程的剖面结构示意图；
图10至图15为本发明又一实施例提供的半导体结构形成过程的剖面结构示意图。
具体实施方式
由背景技术可知，现有技术形成的半导体结构的性能有待提高。
请参考图1，在一个实施例中，提供第一晶圆100，所述第一晶圆100内具有第一插塞103，所述第一晶圆100内还形成有与第一插塞103电连接的第一金属层102，且所述第一金属层102顶部高于第一晶圆100表面；提供第二晶圆101，所述第二晶圆101内具有第二插塞105，所述第二晶圆101内还形成有与第二插塞105电连接的第二金属层104，且所述第二金属层104顶部高于第二晶圆101表面。
请继续参考图1，对所述第一晶圆100以及第二晶圆101进行对准工艺，然后将所述第一晶圆100与第二晶圆101进行键合工艺，所述第二金属层102与第二金属层104紧密接触，以实现第一晶圆100和第二晶圆101之间的键合，且第一晶圆100与第二晶圆101之间电连接。
采用上述方法形成的半导体结构中，在键合完成后，第一金属层102与第二金属层104之间往往难以精确的对准，造成部分面积的第一金属层102和第二金属层104之间的位置错开，这就是所谓的键合偏移(bondingshift)。键合偏移主要是由对准精度低造成的。键合偏移的程度与对准精度有直接的关系，当对准精度越高时，键合偏移程度越小，当对准精度越低时，键合偏移程度越大；因此提高对准工艺的对准精度有利于减小键合偏移。
为此，本发明提供一种新的方法，在第一晶圆表面形成第一材料层，且第一材料层与第一金属层位于第一晶圆的同一面；在第二晶圆表面形成第二材料层，且第二材料层与第二金属层位于第二晶圆的同一面；对所述第一晶圆与第二晶圆进行对准处理以及键合处理，使第一材料层与第二材料层对准且表面相接触，所述第一金属层与第二金属层之间具有第一对准精度；在进行键合处理后，对所述第一材料层以及第二材料层进行加热处理，第一材料层以及第二材料层相互熔融，所述第一金属层与第二金属层之间具有第二对准精度。第一材料层和第二材料层相互熔融时会产生表面张力，在所述表面张力作用下使第一材料层和第二材料层相互拉近，进而使第一金属层与第二金属层相互拉近，使得第二对准精度大于第一对准精度，提高第一晶圆与第二晶圆的对准精度，减小甚至消除键合偏移，降低键合偏移带来的不良影响。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2至图9为本发明另一实施例提供的半导体结构制作过程的剖面结构示意图。
请参考图2，提供第一晶圆200，所述第一晶圆200具有第一面和与所述第一面相对的第二面，所述第一晶圆200内形成有第一金属层202，且第一晶圆200第一面暴露出第一金属层202顶部表面。
本实施例以第一金属层202顶部表面靠近的第一晶圆200的表面称为第一面为例做示范性说明，后续在第一晶圆200的第一面形成第一材料层。
所述第一晶圆200为单层结构或多层结构；所述第一晶圆200的材料包括硅、锗、锗化硅、碳化硅、砷化镓或氧化硅。所述第一晶圆200内还可以形成有半导体器件，例如，CMOS晶体管、PMOS晶体管、NMOS晶体管、电阻器、电容器或电感器。
本实施例中，所述第一晶圆200内形成有第一插塞201，且所述第一插塞201的底部与第一晶圆200的第二面齐平，所述第一插塞201的顶部表面与第一金属层202的底部表面电连接，其中，所述第一金属层202的底部表面指的是：第一金属层202远离第一晶圆200第一面的表面。
为了方便后续对准工艺的进行，本实施例中，所述第一晶圆200内还形成有第一对准结构203，后续提供的第二晶圆内也将形成有第二对准结构。在进行对准处理时，通过将第一对准结构203与第二对准结构进行对准，以完成第一晶圆200和第二晶圆之间的对准。
作为一个具体实施例，形成第一金属层202的工艺步骤包括：在所述第一晶圆200第一面形成图形化的光刻胶层；以所述图形化的光刻胶层为掩膜，刻蚀去除部分厚度的第一晶圆200直至暴露出第一插塞201的顶部表面，在所述第一晶圆200内形成凹槽；形成填充满所述凹槽的金属膜，且所述金属膜还覆盖于第一晶圆200的第一面；平坦化所述金属膜，去除位于第一晶圆200第一面的金属膜，形成填充满所述凹槽的第一金属层202，且所述第一金属层202顶部表面与第一晶圆200第一面齐平。
本实施例以所述第一金属层202顶部表面与第一晶圆200第一面齐平作为示例，在其他实施例中，所述第一金属层顶部表面也可以高于第一晶圆的第一面。所述第一金属层202的材料为Cu、Al、Au、W或Ag。
请参考图3，在所述第一晶圆200表面形成第一材料层206，且所述第一材料层206与第一金属层202位于第一晶圆200的同一面。
本实施例中，第一材料层206以及第一金属层202均位于第一晶圆200的第一面，所述第一材料层206覆盖于第一金属层202顶部表面，且所述第一材料层206具有导电性。
后续提供第二晶圆后，会在第二晶圆的第二金属层表面形成第二材料层，所述第一材料层206和第二材料层的材料为低熔点材料；在将第一晶圆200与第二晶圆进行键合之后，对第一晶圆200和第二晶圆进行加热处理，使第一材料层206和第二材料层处于熔融状态，所述熔融状态的第一材料层206和第二材料层之间具有表面张力，通过所述表面张力的作用使第一材料层206和第二材料层之间相互拉近，进而提高第一晶圆200和第二晶圆之间的对准精度，减小甚至避免键合偏移问题的发生。
本实施例中，第一材料层206材料的熔点与后续键合处理的温度以及加热处理的温度有直接的关系。具体的，为了保证在键合处理过程中，第一材料层206和第二材料层不会熔融，要求第一材料层206材料的熔点大于键合处理的温度；并且为了保证在加热处理过程中，第一材料层206和第二材料层相互熔融，要求第一材料层206材料的熔点小于加热处理的温度。
若第一材料层206材料的熔点过低，那么后续键合处理的温度也将相对比较低，导致第一晶圆200与第二晶圆之间的键合强度较差，第一晶圆200与第二晶圆之间容易分离；并且，由于半导体结构处于工作状态时会产生一定的热量，造成半导体结构的温度上升，若第一材料层206材料的熔点过低，那么在半导体结构处于工作状态时将容易造成第一材料层206熔融。
若第一材料层206材料的熔点过高，那么后续加热处理的温度也将相对比较高，在较高温度下进行的加热处理容易造成半导体结构内的器件失效。为此，本实施例中，所述第一材料层206材料的熔点范围为100℃至350℃。
所述第一材料层206材料包括锡银合金、锡铅合金、铋银合金、锡铋合金或锡铋铅合金。作为一个具体实施例，所述第一材料层206的材料为锡银的合金，第一材料层206的厚度为0.1微米至10微米。
采用电化学镀膜法形成所述第一材料层206。作为一个实施例，在电化学镀膜形成第一材料层206之前，在第一晶圆200表面形成第一种子层，所述第一种子层为电化学镀膜提供工艺基础。在一个实施例中，所述第一种子层的厚度为100埃至1000埃。
在一个实施例中，形成第一材料层206的工艺步骤包括：形成覆盖于第一晶圆200表面(即第一面)的第一种子层(未图示)，且所述第一种子层还覆盖于第一金属层202顶部表面；在所述第一种子层表面形成第一光刻胶层，且第一光刻胶层表面暴露出位于第一金属层202表面的第一种子层；在所述暴露出的第一种子层表面形成第一材料层206；去除所述第一光刻胶层以及位于第一光刻胶层底部的第一种子层。
本实施例中，所述第一材料层206仅覆盖于第一金属层202的顶部表面，也就说，所述第一材料层206与第一金属层202的尺寸一致。这样设置的好处在于：后续的工艺过程中，第一材料层206的尺寸有可能变大，本实施例中由于第一材料层206与第一金属层202尺寸一致，防止由于第一材料层206尺寸变大，而造成的相邻第一材料层206之间电连接的问题。
在其他实施例中，若相邻第一金属层之间的距离较大，那么形成的第一材料层的尺寸也可以大于第一金属层的尺寸，即第一材料层除覆盖于第一金属层顶部表面外，还可以覆盖于位于第一金属层附近的第一晶圆表面。
请参考图4，提供第二晶圆300，所述第二晶圆300具有第三面和与所述第三面相对的第四面，所述第二晶圆300内形成有第二金属层302，且第二晶圆300第三面暴露出第二金属层302顶部表面。
本实施例以第二金属层302顶部表面靠近第二晶圆300的表面为第三面为例做示范性说明，后续在进行第一晶圆200(请参考图3)与第二晶圆300进行键合处理时，实际是将第一晶圆200的第一面与第二晶圆300的第三面进行键合。
有关第二晶圆300的描述可参考前述第一晶圆200的有关描述，在此不再赘述。
本实施例中，所述第二晶圆300内形成有第二插塞301，且所述第二插塞301的底部位于第二晶圆300内，所述第二插塞301的顶部表面与第二金属层302的底部表面电连接，其中，所述第二金属层302的底部表面指的是：第二金属层302远离第二晶圆300第三面的表面。
本实施例以第二金属层302顶部表面与第二晶圆300第三面齐平作为示例。在其他实施例中，所述第二金属层顶部表面也可以高于第二晶圆的第三面。所述第二金属层302的材料为Cu、Al、Au、W或Ag。
所述第二晶圆300内还形成有第二对准结构303，后续在进行对准工艺时，通过将第一对准结构203(请参考图3)与第二对准结构303进行对准，以完成第一晶圆200和第二晶圆300之间的对准。
请参考图5，在所述第二晶圆300表面形成第二材料层306，且所述第二材料层306与第二金属层302位于第二晶圆300的同一面。
本实施例中，第二材料层306以及第二金属层302均位于第二晶圆300的第一面，所述第二材料层306覆盖于第二金属层302顶部表面，且所述第二材料层306具有导电性。
所述第二材料层306的材料为低熔点材料，有关第二材料层306的描述可参考前述第一材料层206的描述，在此不再赘述。第二材料层306的材料包括锡银合金、锡铅合金、铋银合金、锡铋合金或锡铋铅合金。
本实施例中，所述第二材料层306材料的熔点范围为100℃至350℃，为了降低工艺难度，所述第一材料层206与第二材料层306的材料为相同材料。在其他实施中，第二材料层和第一材料层也可以为不同材料。
本实施例以所述第二材料层306仅覆盖于第二金属层302顶部表面作示例，也就是说，第二材料层306的尺寸与第二金属层302尺寸相同。
请参考图6，对所述第一晶圆200与第二晶圆300进行对准处理，使第一材料层206与第二材料层306对准；在进行对准处理后，对所述第一晶圆200与第二晶圆300进行键合处理，使第一材料层206与第二材料层306对准且表面相接触，所述第一金属层202与第二金属层302之间具有第一对准精度。
对准精度反映第一金属层202与第二金属层302的对齐程度，对准精度指的是：第一金属层202与第二金属层302相互重合的顶部表面的尺寸为第一尺寸，第一金属层202或第二金属层302的尺寸为第二尺寸，第一尺寸与第二尺寸的比值可称为对准精度。当对准精度为100％时，表明第一金属层202与第二金属层302之间完全对准，完全对准指的是：第一金属层202与第二金属层302侧壁完全齐平。
在进行键合之前，通过使第一对准结构203和第二对准结构303之间对准，以进行对准处理。理想情况下，第一晶圆200和第二晶圆300之间的完全对准，即第一金属层202和第二金属层302的第一对准精度为100％。然而，由于受到对准工艺的限制以及晶圆尺寸越来越小，在进行对准之后，第一对准结构203和第二对准结构303之间的对准误差难以消除，造成第一材料层206和第二材料层306之间也具有对准误差，即第一材料层206和第二材料层306之间相互错开，第一材料层206和第二材料层306的侧壁表面不齐平，因此本实施例中第一对准精度有待提高。
本实施例中，将所述第一晶圆200的第一面与第二晶圆300的第三面进行键合。
采用热压键合工艺进行所述键合处理，即所述键合处理在第一温度下进行，且在进行所述键合处理过程中，对第一晶圆200背面(即第一晶圆200第二面)施加压力，所述压力方向为沿第一晶圆200背面指向第一晶圆200表面(即第一晶圆200第一面)。在所述键合处理后，第一材料层206与第二材料层306表面紧密接触。
若第一温度过低，则第一材料层206与第二材料层306之间接触不够紧密，在后续的工艺过程中第一材料层206与第二材料层306之间容易分离；若第一温度过高，则在键合处理过程中第一材料层206和第二材料层306会相互熔融，且在压力作用下，第一材料层206和第二材料层306之间表面张力起到的有益效果非常有限，即在表面张力作用下，第一材料层206和第二材料层306相互拉近的程度有限，不利于提高第一晶圆200和第二晶圆200之间的对准精度，因此第一材料层206的材料熔点大于第一温度。本实施例中，所述第一温度为100℃至250℃。
请参考图7，在进行键合处理后，对所述第一材料层206以及第二材料层306进行加热处理，第一材料层206以及第二材料层306相互熔融，所述第一金属层202与第二金属层302之间具有第二对准精度，且所述第二对准精度大于第一对准精度，使第一金属层202与第二金属层302对齐。
由于在键合处理后，第一金属层202与第二金属层302之间具有第一对准精度，且所述第一对准精度有待提高。为此本实施例提供加热处理，以期提高第一材料层206与第二材料层306之间的对准精度，从而提高第一金属层202与第二金属层302之间、第一晶圆200与第二晶圆300之间的对准精度，即第二对准精度大于第一对准精度，减小甚至消除键合偏移问题，降低或避免键合偏移带来的不良影响。
所述加热处理在第二温度下进行，且所述第二温度大于第一温度。本实施例中，所述第一材料层206和第二材料层306的材料熔点大于第一温度且小于第二温度。
若第二温度过低，则第一材料层206和第二材料层306在加热处理过程中难以达到熔融状态；若第二温度过高，有可能会破坏半导体结构内形成的器件。为此，本实施例中，所述第二温度为200℃至350℃。
由于第二温度大于第一材料层206和第二材料层306的材料熔点，因此在加热处理下第一材料层206和第二材料层306相互熔融；第一材料层206和第二材料层306在熔融状态下具有表面张力，在所述表面张力作用下，第一材料层206和第二材料层306相互拉近靠近，从而提高第一材料层206和第二材料层306之间的对准精度，提高第一金属层202与第二金属层302之间、第一晶圆200和第二晶圆300之间的对准精度，使得第二对准精度大于第一对准精度，减小甚至消除第一晶圆200和第二晶圆300之间的键合偏移，进而使第一金属层202和第二金属层302的侧壁齐平。
图7示出了一种加热处理后半导体结构的示意图，在加热处理后，第一材料层206和第二材料层306的尺寸几乎保持不变，且第一金属层202和第二金属层302的侧壁齐平，第二对准精度近似为100％，显著提高了第一晶圆200和第二晶圆300之间的对准精度，消除键合偏移问题。
图8示出了另一种加热处理后半导体结构的示意图，在加热处理后，第一材料层206和第二材料层306的尺寸有可能会变大，即第一材料层206的尺寸大于第一金属层202的尺寸，第二材料层306的尺寸大于第二金属层302的尺寸，且第一金属层202和第二金属层302的侧壁齐平。本实施例中，在加热处理之前第一材料层206仅覆盖于第一金属层202顶部表面，第二材料层306仅覆盖于第二金属层302顶部表面，因此相邻第一材料层206之间、相邻第二材料层306之间的距离保持较大，防止由于加热处理后第一材料层206和第二材料层306尺寸增加而造成的电连接问题。
图9示出了又一种加热处理后半导体结构的示意图，加热处理使第一金属层202和第二金属层302之间对齐。在加热处理过程中，受到第一材料层206和第二材料层306之间表面张力的作用，第一金属层202和第二金属层302之间相互拉近靠近；与加热处理之前相比，第一金属层202和第二金属层302之间的对准精度得到提高，使得第二对准精度大于第一对准精度，从而使第一晶圆200和第二晶圆300之间的键合偏移问题减小。
相应的，本实施例提供一种半导体结构，请参考图7，所述半导体结构包括：第一晶圆200，位于第一晶圆200内的第一金属层202，所述第一金属层202顶部表面被暴露出来，位于第一晶圆200表面的第一材料层206，且所述第一材料层206与第一金属层202位于第一晶圆200的同一面；第二晶圆300，位于第二晶圆300内的第二金属层302，所述第二金属层302顶部表面被暴露出来，位于第二晶圆300表面的第二材料层306，且所述第二材料层306与第二金属层302位于第二晶圆300的同一面；具有第一材料层206的第一晶圆200表面与具有第二材料层306的第二晶圆300表面相键合，第一材料层206与第二材料层306对准且表面相接触，所述第一金属层202与第二金属层302之间具有第二对准精度。第一金属层202顶部表面与第一晶圆200表面齐平，第一金属层202顶部表面也可以高于第一晶圆200表面；第二金属层302顶部表面与第二晶圆300表面齐平，第二金属层302顶部表面也可以高于第二晶圆300表面。
本实施例中，所述第一材料层206覆盖于第一金属层202顶部表面，所述第二材料层306覆盖于第二金属层302顶部表面，且所述第一材料层206和第二材料层306具有导电性。
在一实施例中，如图7所示，所述第一材料层206的尺寸与第一金属层202尺寸相同，第一材料层206仅覆盖于第一金属层202顶部表面；第二材料层306的尺寸与第二金属层302尺寸相同，第二材料层306仅覆盖于第二金属层302顶部表面；所述第一材料层206侧壁表面与第二材料层306侧壁表面完全对齐。
在另一实施例中，如图8所示，所述第一材料层206尺寸大于第一金属层202尺寸，所述第一材料层206除覆盖于第一金属层202顶部表面外，还覆盖于部分第一晶圆200表面；所述第二材料层306尺寸大于第二金属层302尺寸，所述第二材料层306除覆盖于第二金属层302顶部表面外，还覆盖于部分第二晶圆300表面；所述第一材料层206侧壁表面与第二材料层306侧壁表面完全对齐。
在其他实施例中，如图9所示，第一材料层206与第二材料层306侧壁表面未完全对齐。
本发明又一实施例还提供一种半导体结构的制作方法，图10至图15为本发明又一实施例提供的半导体结构制作过程的剖面结构示意图。
请参考图10，提供第一晶圆20，所述第一晶圆20包括第一面和与所述第一面相对的第二面，所述第一晶圆20内形成有第一金属层22，第一晶圆20第一面暴露出第一金属层22顶部表面；在所述第一晶圆20第一面形成第一材料层26，所述第一材料层26与第一金属层22位于第一晶圆20的同一面。
本实施例中，在第一金属层22顶部表面以外的第一晶圆20第一面形成第一材料层26，因此本实施例中不需要借助第一材料层26的导电性能以使第一金属层22和后续提供的第二金属层之间电连接，所述第一材料层26的材料可以为绝缘材料或导电材料。
所述第一金属层22顶部表面高于第一晶圆20第一面，则后续在键合处理后第一金属层22和提供的第二金属层之间的距离较小，有利于降低二次键合处理的工艺难度。在其他实施例中，第一金属层顶部表面也可以高于第一晶圆第一面。
后续提供第二晶圆后，会在第二晶圆表面形成第二材料层，所述第一材料层26和第二材料层的材料为低熔点材料。具体的，后续在对第一材料层26和第二材料层进行加热处理，使第一材料层26和第二材料层处于熔融状态，所述熔融状态的第一材料层26和第二材料层之间具有表面张力，通过所述表面张力使第一材料层26和第二材料层之间相互拉近，进而提高第一晶圆20和第二晶圆之间的对准精度。
本实施例中，第一材料层26材料的熔点与后续键合处理的温度以及加热处理的温度有直接的关系。有关分析可参考前一实施例的说明，在此不再赘述。本实施例中第一材料层26材料的熔点范围为100℃至350℃。作为一个具体实施例，所述第一材料层26的材料为锡银合金，所述第一材料层206的材料也可以为其他合适的低熔点合金。在其他实施例中，第一材料层的材料为绝缘材料时，第一材料层材料的熔点范围为100℃至350℃，第一材料层的材料可以为树脂，例如，环氧树脂或聚丙烯树脂。
若第一材料层26的厚度过薄，后续在键合处理时，第一金属层22与第二金属层之间也将发生键合处理，造成后续提供的加热处理难以进一步提高第一金属层22和第二金属层之间的对齐程度；若第一材料层26的厚度过厚，后续在键合处理后，第一金属层22顶部表面至第二金属层顶部表面之间的距离过大，导致后续二次键合处理的工艺难度过大。为此，本实施例中，第一材料层26的厚度大于第一金属层22顶部表面至第一晶圆20第一面的距离。作为一个具体实施例，所述第一金属层22顶部表面至第一晶圆20第一面的距离为0.05微米时，所述第一材料层26的厚度为0.1微米至10微米。
在一个实施例中，形成第一材料层206的工艺步骤包括：在所述第一晶圆20表面(即第一面)形成第一光刻胶层，所述第一光刻胶层覆盖于第一金属层22表面；在未被第一光刻胶层覆盖的第一晶圆20表面形成第一材料层26；去除所述第一光刻胶层。
请参考图11，提供第二晶圆30，所述第二晶圆30包括第三面和与所述第三面相对的第四面，所述第二晶圆30内形成有第二金属层32，第二晶圆30第三面暴露出第二金属层32顶部表面；在所述第二晶圆30第三面形成第二材料层36，所述第二材料层36与第二金属层32位于第二晶圆30的同一面。
本实施例中，在第二金属层32顶部表面以外的第二晶圆30第三面形成第二材料层36，所述第二材料层36的材料可以为绝缘材料或导电材料。
所述第二金属层32顶部表面高于第二晶圆30第三面，在其他实施例汇总，所述第二金属层32顶部表面也可以与第二晶圆30第三面齐平。所述第二材料层36的材料熔点范围为100℃至350℃。有关第二材料层36的描述可参考前述对第一材料层26的描述。
为了保证后续在键合处理后，第一金属层22顶部表面与第二金属层32顶部表面之间具有空隙，第一金属层22顶部表面至第一晶圆20第一面的距离为第一距离，第二金属层32顶部表面与第二晶圆30第三面的距离为第二距离，要求第一材料层26与第二材料层36的厚度之和、大于第一距离与第二距离之和。本实施例中，所述第二材料层36的厚度大于第二金属层32顶部表面至第二晶圆30第三面之间的距离。
本实施例中，所述第二材料层36与第一材料层26的尺寸、材料均相同，且第一材料层26与第一金属层22之间的距离与第二材料层36与第二金属层32之间的距离相等。
请参考图12，对所述第一晶圆20与第二晶圆30进行对准处理，使第一材料层26与第二材料层36对准；在进行对准处理后，对所述第一晶圆20与第二晶圆30进行键合处理，使第一材料层26与第二材料层36对准且表面相接触，所述第一金属层22与第二金属层32之间具有第一对准精度。
通过使第一对准结构23与第二对准结构33对准，以使第一晶圆20与第二晶圆30对准。
然而，由于受到对准工艺的工艺限制以及半导体结构尺寸的不断缩小，难以实现第一晶圆20与第二晶圆30之间完全对准，完全对准指的是：在进行对准处理之后，第一金属层22与第二金属层32侧壁齐平。在实际工艺中，键合处理后第一材料层26与第二材料层36的侧壁表面并未齐平，第一金属层22与第二金属层32侧壁之间具有一定的距离，第一对准精度有待提高。
采用热压键合法进行所述键合处理，所述键合处理在第一温度下进行。若第一温度过低，则第一材料层26与第二材料层36之间的键合强度过低，在后续的工艺过程中第一材料层26与第二材料层36之间容易分离；若第二温度过高，则在较高温度下容易造成第一材料层26和第二材料层36相互熔融，为此，本实施例中第一温度小于第一材料层26和第二材料层36的材料熔点。作为一个具体实施例，所述第一温度为100℃至250℃。
在进行所述键合处理过程中，对第一晶圆20背面(即第二面)施加第一压力，且所述第一压力方向沿第一晶圆20背面指向第一晶圆20表面(即第一面)。
若第一压力过小，第一材料层26与第二材料层36之间的键合强度差；若第一压力过大，可能会造成第一金属层22与第二金属层32顶部表面相互键合。为此，本实施例中第一压力的大小为1千牛至20千牛。
若在键合处理后，第一金属层22与第二金属层32之间紧密接触，第一金属层22与第二金属层32之间具有一定的键合强度；当后续第一材料层26和第二材料层36提供表面张力作用，第一材料层26和第二材料层36之间相互拉近时，由于第一金属层22与第二金属层32之间具有一定的键合强度，则第一金属层22和第二金属层32将很难相互移动，表面张力作用对提高第一晶圆20和第二晶圆30之间对准精度起到的有益效果差。
因此，本实施例中在进行键合处理之后，第一金属层22顶部表面与第二金属层32顶部表面之间具有间隙，防止第一金属层22顶部表面与第二金属层32顶部表面在键合处理作用下紧密接触。
请参考图13，在进行键合处理后，对所述第一材料层26以及第二材料层36进行加热处理，第一材料层26以及第二材料层36相互熔融，第一金属层22与第二金属层32之间具有第二对准精度，且第二对准精度大于第一对准精度，使第一金属层22与第二金属层32对齐。
所述加热处理在第二温度下进行，所述第二温度大于第一材料层26和第二材料层36的材料熔点，因此本实施例中，第一材料层26和第二材料层36的材料熔点大于第一温度且小于第二温度。
在加热处理过程中，第一材料层26以及第二材料层36处于熔融状态，第一材料层26与第二材料层36相互熔融，使得第一材料层26与第二材料层36之间具有表面张力；在所述表面张力作用下，第一材料层26与第二材料层36相互拉近，进而使得第一金属层22与第二金属层32相互拉近，提高第一材料层26与第二材料层36之间、第一金属层22与第二金属层32之间的对准精度，进而提高第一晶圆20与第二晶圆30之间的对准精度，使得第二对准精度大于第一对准精度，减小甚至消除键合偏移问题。
若第二温度过低，第一材料层26和第三材料层36难以达到熔融程度；若第二温度过高，半导体结构内的器件有可能受到损伤。为此，本实施例中，所述第二温度为200℃至350℃。
作为一个实施例，在加热处理后，第一材料层26与第二材料层36完全对准，即第一材料层26与第二材料层36侧壁齐平，使得第一金属层22与第二金属层32侧壁齐平，第二对准精度近似为100％。
在另一实施例中，第一材料层26和第二材料层36在熔融状态下具有的表面张力作用有限，则在加热处理后，第一材料层26与第二材料层36侧壁未达到完全对齐，即第一金属层22与第二金属层32未完全对准。相较于加热处理前，第一金属层22与第二金属层32之间的对准精度得到提高，从而使得第一晶圆20与第二晶圆30之间的对准精度提高；因此即使在加热处理后第一金属层22与第二金属层32未完全对准，相较于现有技术而言，本实施例仍提高了第一晶圆20与第二晶圆30之间的对准精度，减小了键合偏移。
请参考图14，在进行加热处理后，对所述第一晶圆20和第二晶圆30进行二次键合处理，使第一金属层22与第二金属层32顶部表面相接触，第一金属层22与第二金属层32之间仍具有第二对准精度。
由于在加热处理之后，第一金属层22顶部表面与第二金属层32顶部表面之间仍具有空隙，第一金属层22与第二金属层32之间未电连接；因此在加热处理后进行二次键合处理，使第一金属层22与第二金属层32顶部表面紧密接触。
采用热压键合工艺进行所述二次键合处理，即二次键合处理在第三温度下进行，且在进行二次键合处理过程中，对第一晶圆20背面(即第二面)施加第二压力，所述第二压力方向沿第一晶圆20背面指向第一晶圆20表面(即第一面)，且所述第二压力大于第一压力。
作为一个具体实施例，所述第二应力的大小为10千牛至100千牛。
若第三温度过低，则第一金属层22与第二金属层32顶部表面之间的键合强度过低；若第三温度过高，则在较高温度下容易对半导体结构内的器件造成损伤，且在较高温度下第一材料层26和第二材料层36容易达到熔融状态。为此，本实施例中第三温度为100℃至250℃。
与现有技术相比，本实施例明显提高了第一金属层22与第二金属层32之间、第一晶圆20与第二晶圆30之间的对准精度，减小甚至消除了键合偏移，降低了键合偏移带来的不良影响。
在一个实施例中，如图14所示，在二次键合处理之前，第一材料层26与第二材料层36之间、第一金属层22与第二金属层32之间完全对准，即第一金属层22与第二金属层32侧壁齐平；在二次键合处理之后，第一金属层22与第二金属层32侧壁齐平且顶部表面紧密接触。在二次键合处理过程中，第一材料层26和第二材料层36在第三温度和第二压力作用下，厚度减小且面积增加了。
在另一实施例中，如图15所示，在二次键合处理之前，第一材料层26与第二材料层36之间、第一金属层22与第二金属层32之间未完全对准，即第一金属层22侧壁与第二金属层32侧壁之间具有一定的距离；在二次键合处理之后，第一金属层22侧壁与第二金属层32侧壁表面相应也具有一定的距离。与现有技术相比，即使本实施例中第一金属层22与第二金属层32之间未完全对准，第一金属层22与第二金属层32之间、第一晶圆20与第二晶圆30之间的对准精度仍得到提高，减小了第一晶圆20与第二晶圆30的键合偏移，减小了键合偏移带来的不良影响。
同时，由于本实施例中第一材料层26与第一金属层22之间的距离、第二材料层36与第二金属层32之间的距离可以设置的比较远，防止第一材料层26、第二材料层36影响第一金属层22以及第二金属层32的电性能。并且，在由于在二次键合处理之后，第一材料层26和第二材料层36的尺寸将变大，而随着半导体结构尺寸的不断缩小，相邻第一金属层22之间、相邻第二金属层32之间的距离越来越小；本实施例未将第一材料层26形成在第一金属层22顶部表面，未将第二材料层36形成在第二金属层32顶部表面，避免由于第一材料层26和第二材料层36尺寸变大引起的电连接问题。
相应的，本实施例提供一种半导体结构，请参考图14，所述半导体结构包括：第一晶圆20，位于第一晶圆20内的第一金属层22，所述第一金属层22顶部表面被暴露出来，位于第一晶圆20表面的第一材料层26，且所述第一材料层26与第一金属层22位于第一晶圆20的同一面；第二晶圆30，位于第二晶圆30内的第二金属层32，所述第二金属层32顶部表面被暴露出来，位于第二晶圆30表面的第二材料层36，且所述第二材料层36与第二金属层32位于第二晶圆30的同一面；具有第一材料层26的第一晶圆20表面与具有第二材料层36的第二晶圆30表面相键合，第一材料层26与第二材料层36对准且表面相接触，所述第一金属层22与第二金属层32之间具有第二对准精度。
本实施例以第一金属层22顶部表面高于第一晶圆20表面、第二金属层32顶部表面高于第二晶圆30表面作示例。在其他实施例中第一金属层顶部表面可以与第一晶圆表面齐平，第二金属层顶部表面可以与第二晶圆表面齐平。
本实施例中，所述第一材料层26位于第一金属层22顶部表面以外的第一晶圆20表面，所述第二材料层36位于第二金属层32顶部表面以外的第二晶圆30表面，且第一材料层26和第二材料层36的材料为绝缘材料或导电材料所述第一金属层22顶部表面与第二金属层32顶部表面相键合，第一金属层22顶部表面与第二金属层32顶部表面相接触。
在一个实施例中，如图14所示，第一材料层26与第二材料层36侧壁齐平，第一金属层22与第二金属层32侧壁齐平，则第二对准精度近似为100％。在另一实施例中，如图15所示，第一材料层26与第二材料层36侧壁未完全齐平，第一金属层22与第二金属层32侧壁未完全齐平，部分面积的第一金属层22与第二金属层32相互错开。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体结构的制作方法，其特征在于，包括：
提供第一晶圆以及第二晶圆，所述第一晶圆内形成有第一金属层，且第一晶圆表面暴露出第一金属层顶部表面，所述第二晶圆内形成有第二金属层，且第二晶圆表面暴露出第二金属层顶部表面；
在所述第一晶圆表面形成第一材料层，且所述第一材料层与第一金属层位于第一晶圆的同一面；
在所述第二晶圆表面形成第二材料层，且所述第二材料层与第二金属层位于第二晶圆的同一面；
对所述第一晶圆与第二晶圆进行对准处理以及键合处理，使第一材料层与第二材料层对准且表面相接触，所述第一金属层与第二金属层之间具有第一对准精度；
在进行键合处理后，对所述第一材料层以及第二材料层进行加热处理，使第一材料层以及第二材料层相互熔融，所述第一金属层与第二金属层之间具有第二对准精度，且所述第二对准精度大于第一对准精度。
2.如权利要求1所述半导体结构的制作方法，其特征在于，所述第一材料层覆盖于第一金属层顶部表面，所述第二材料层覆盖于第二金属层顶部表面，且所述第一材料层和第二材料层具有导电性。
3.如权利要求2所述半导体结构的制作方法，其特征在于，所述第一材料层和第二材料层的材料包括锡银合金、锡铅合金、铋银合金、锡铋合金或锡铋铅合金。
4.如权利要求2所述半导体结构的制作方法，其特征在于，在进行所述键合处理过程中，对第一晶圆背面施加压力。
5.如权利要求2所述半导体结构的制作方法，其特征在于，形成第一材料层的工艺步骤包括：形成覆盖于第一晶圆表面的第一种子层，且所述第一种子层还覆盖于第一金属层顶部表面；在所述第一种子层表面形成第一光刻胶层，且第一光刻胶层表面暴露出位于第一金属层顶部表面的第一种子层；在所述暴露出的第一种子层表面形成第一导电层；去除所述第一光刻胶层以及位于第一光刻胶层底部的第一种子层。
6.如权利要求1所述半导体结构的制作方法，其特征在于，在所述第一金属层顶部表面以外的第一晶圆表面形成第一材料层；在第二金属层顶部表面以外的第二晶圆表面形成第二材料层，且第一材料层和第二材料层的材料为绝缘材料或导电材料。
7.如权利要求6所述半导体结构的制作方法，其特征在于，在进行所述键合处理之后，第一金属层顶部表面与第二金属层顶部表面之间具有间隙。
8.如权利要求6所述半导体结构的制作方法，其特征在于，在进行所述键合处理过程中，对第一晶圆背面施加第一压力。
9.如权利要求8所述半导体结构的制作方法，其特征在于，所述第一压力的大小为1千牛至20千牛。
10.如权利要求8所述半导体结构的制作方法，其特征在于，在进行所述加热处理后，还包括步骤：对所述第一晶圆与第二晶圆进行二次键合处理，使第一金属层与第二金属层顶部表面相接触。
11.如权利要求10所述半导体结构的制作方法，其特征在于，在进行所述二次键合处理过程中，对第一晶圆背面施加第二压力，所述第二压力方向为沿第一晶圆背面指向第一晶圆表面，且所述第二压力大于第一压力。
12.如权利要求11所述半导体结构的制作方法，其特征在于，所述第二压力的大小为10千牛至100千牛。
13.如权利要求1所述半导体结构的制作方法，其特征在于，所述键合处理在第一温度下进行，所述加热处理在第二温度下进行，且所述第一温度小于第二温度。
14.如权利要求13所述半导体结构的制作方法，其特征在于，所述第一材料层和第二材料层的材料熔点大于第一温度且小于第二温度。
15.如权利要求14所述半导体结构的制作方法，其特征在于，所述第一温度为100℃至250℃，所述第二温度为200℃至350℃。
16.如权利要求1所述半导体结构的制作方法，其特征在于，所述第一晶圆内形成有第一对准结构，所述第二晶圆内形成有第二对准结构，通过使所述第一对准结构与第二对准结构对准，以进行对准处理。
17.一种半导体结构，其特征在于，包括：
第一晶圆，位于第一晶圆内的第一金属层，所述第一金属层顶部表面被暴露出来，位于第一晶圆表面的第一材料层，且所述第一材料层与第一金属层位于第一晶圆的同一面；
第二晶圆，位于第二晶圆内的第二金属层，所述第二金属层顶部表面被暴露出来，位于第二晶圆表面的第二材料层，且所述第二材料层与第二金属层位于第二晶圆的同一面；
表面具有第一材料层的第一晶圆与表面具有第二材料层的第二晶圆相键合，第一材料层与第二材料层对准且表面相接触，所述第一金属层与第二金属层之间具有第二对准精度。
18.如权利要求17所述半导体结构，其特征在于，所述第一材料层覆盖于第一金属层顶部表面，所述第二材料层覆盖于第二金属层顶部表面，且所述第一材料层和第二材料层具有导电性。
19.如权利要求17所述半导体结构，其特征在于，所述第一材料层位于第一金属层顶部表面以外的第一晶圆表面，所述第二材料层位于第二金属层顶部表面以外的第二晶圆表面，且第一材料层和第二材料层的材料为绝缘材料或导电材料。
20.如权利要求19所述半导体结构，其特征在于，所述第一金属层顶部表面与第二金属层顶部表面相键合，第一金属层顶部表面与第二金属层顶部表面相接触。
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Publication number Priority date Publication date Assignee Title
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CN112599431A (zh) * 2020-12-15 2021-04-02 联合微电子中心有限责任公司 晶圆键合结构及键合方法
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CN113078090A (zh) * 2021-03-23 2021-07-06 长江存储科技有限责任公司 晶圆制备方法、键合方法、键合装置、键合设备
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US11488917B1 (en) 2021-07-01 2022-11-01 Ghangxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof
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US11955396B2 (en) 2020-11-27 2024-04-09 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

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US9764153B2 (en) * 2013-03-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming same
KR102393946B1 (ko) * 2016-10-07 2022-05-03 엑셀시스 코포레이션 직접-접합된 네이티브 상호접속부 및 능동 베이스 다이
US10580757B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Face-to-face mounted IC dies with orthogonal top interconnect layers
JP2019121704A (ja) * 2018-01-09 2019-07-22 トヨタ自動車株式会社 半導体装置
US10790262B2 (en) * 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
EP3828922A1 (en) 2019-11-26 2021-06-02 IMEC vzw A method for bonding semiconductor components
US11189600B2 (en) 2019-12-11 2021-11-30 Samsung Electronics Co., Ltd. Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding
US11830865B2 (en) * 2021-10-26 2023-11-28 Nanya Technology Corporation Semiconductor device with redistribution structure and method for fabricating the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3811186A (en) * 1972-12-11 1974-05-21 Ibm Method of aligning and attaching circuit devices on a substrate
US7875529B2 (en) * 2007-10-05 2011-01-25 Micron Technology, Inc. Semiconductor devices
CN102169845A (zh) * 2011-02-22 2011-08-31 中国科学院微电子研究所 一种用于三维封装的多层混合同步键合结构及方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7557452B1 (en) * 2000-06-08 2009-07-07 Micron Technology, Inc. Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating same
US6605524B1 (en) * 2001-09-10 2003-08-12 Taiwan Semiconductor Manufacturing Company Bumping process to increase bump height and to create a more robust bump structure
US7182241B2 (en) * 2002-08-09 2007-02-27 Micron Technology, Inc. Multi-functional solder and articles made therewith, such as microelectronic components
JP2004134648A (ja) * 2002-10-11 2004-04-30 Seiko Epson Corp 回路基板、ボール・グリッド・アレイの実装構造、及び電気光学装置、並びに電子機器
US7615476B2 (en) * 2005-06-30 2009-11-10 Intel Corporation Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages
US8748232B2 (en) * 2012-01-03 2014-06-10 Maxim Integrated Products, Inc. Semiconductor device having a through-substrate via
US9064820B2 (en) * 2012-04-05 2015-06-23 Mekiec Manufacturing Corporation (Thailand) Ltd Method and encapsulant for flip-chip assembly
JP5902107B2 (ja) * 2013-01-24 2016-04-13 オリジン電気株式会社 加熱接合装置及び加熱接合製品の製造方法
US9287188B2 (en) * 2013-02-05 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a seal ring structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3811186A (en) * 1972-12-11 1974-05-21 Ibm Method of aligning and attaching circuit devices on a substrate
US7875529B2 (en) * 2007-10-05 2011-01-25 Micron Technology, Inc. Semiconductor devices
CN102169845A (zh) * 2011-02-22 2011-08-31 中国科学院微电子研究所 一种用于三维封装的多层混合同步键合结构及方法

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109411374A (zh) * 2018-10-25 2019-03-01 德淮半导体有限公司 晶圆及其键合的对准方法
CN110112097A (zh) * 2019-05-21 2019-08-09 德淮半导体有限公司 晶圆键合结构以及晶圆键合结构的制作方法
CN112420531A (zh) * 2020-11-27 2021-02-26 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
US11955396B2 (en) 2020-11-27 2024-04-09 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
CN112599431A (zh) * 2020-12-15 2021-04-02 联合微电子中心有限责任公司 晶圆键合结构及键合方法
CN112786462B (zh) * 2020-12-25 2023-08-22 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
CN112786462A (zh) * 2020-12-25 2021-05-11 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
CN113078090A (zh) * 2021-03-23 2021-07-06 长江存储科技有限责任公司 晶圆制备方法、键合方法、键合装置、键合设备
CN113078090B (zh) * 2021-03-23 2024-04-12 长江存储科技有限责任公司 晶圆制备方法、键合方法、键合装置、键合设备
US11488917B1 (en) 2021-07-01 2022-11-01 Ghangxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof
CN115565976A (zh) * 2021-07-01 2023-01-03 长鑫存储技术有限公司 半导体结构及半导体结构的制作方法
WO2023272944A1 (zh) * 2021-07-01 2023-01-05 长鑫存储技术有限公司 半导体结构及半导体结构的制作方法
WO2023272943A1 (zh) * 2021-07-01 2023-01-05 长鑫存储技术有限公司 半导体结构及半导体结构的制作方法
CN115565976B (zh) * 2021-07-01 2024-06-07 长鑫存储技术有限公司 半导体结构及半导体结构的制作方法
CN113793808A (zh) * 2021-08-04 2021-12-14 清华大学 金属凸点及其制造方法和使用方法
CN115939107A (zh) * 2023-02-20 2023-04-07 青岛物元技术有限公司 晶圆到晶圆封装位移检测结构及位移补偿方法

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