CN105225971B - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
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- CN105225971B CN105225971B CN201510363009.3A CN201510363009A CN105225971B CN 105225971 B CN105225971 B CN 105225971B CN 201510363009 A CN201510363009 A CN 201510363009A CN 105225971 B CN105225971 B CN 105225971B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014-132430 | 2014-06-27 | ||
| JP2014132430A JP6249892B2 (ja) | 2014-06-27 | 2014-06-27 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105225971A CN105225971A (zh) | 2016-01-06 |
| CN105225971B true CN105225971B (zh) | 2018-12-04 |
Family
ID=54839996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510363009.3A Active CN105225971B (zh) | 2014-06-27 | 2015-06-26 | 半导体装置的制造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9437460B2 (enExample) |
| JP (1) | JP6249892B2 (enExample) |
| CN (1) | CN105225971B (enExample) |
| DE (1) | DE102015210603B4 (enExample) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112017000083T5 (de) * | 2016-03-18 | 2018-04-26 | Fuji Electric Co., Ltd. | Halbleitervorrichtung, metallelektrodenelement und verfahren zum herstellen der halbleitervorrichtung |
| US10347549B2 (en) * | 2016-04-30 | 2019-07-09 | Littelfuse, Inc. | Power semiconductor device module having mechanical corner press-fit anchors |
| US10062621B2 (en) * | 2016-04-30 | 2018-08-28 | Ixys, Llc | Power semiconductor device module having mechanical corner press-fit anchors |
| JP6683266B2 (ja) * | 2017-01-17 | 2020-04-15 | 富士電機株式会社 | 半導体装置 |
| JP6816825B2 (ja) * | 2017-06-21 | 2021-01-20 | 三菱電機株式会社 | 半導体装置、電力変換装置および半導体装置の製造方法 |
| CN107946273A (zh) * | 2017-12-22 | 2018-04-20 | 江苏宏微科技股份有限公司 | 一种插接功率模块封装装置 |
| JP7107120B2 (ja) * | 2018-09-14 | 2022-07-27 | 富士電機株式会社 | 半導体装置、半導体装置の製造方法 |
| JP7279354B2 (ja) * | 2018-12-17 | 2023-05-23 | 富士電機株式会社 | 半導体素子及び半導体素子の識別方法 |
| JP7293936B2 (ja) | 2019-07-19 | 2023-06-20 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
| JP7404834B2 (ja) * | 2019-12-06 | 2023-12-26 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
| CN111769090A (zh) * | 2020-07-21 | 2020-10-13 | 无锡利普思半导体有限公司 | 塑封功率模块、塑封模具及塑封方法 |
| JP7666045B2 (ja) * | 2021-03-19 | 2025-04-22 | 富士電機株式会社 | 半導体装置 |
| JP7692720B2 (ja) * | 2021-04-06 | 2025-06-16 | 三菱重工業株式会社 | パワーモジュール、及びパワーモジュールの製造方法 |
| JP7484800B2 (ja) * | 2021-04-08 | 2024-05-16 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
| US11901273B2 (en) * | 2021-07-26 | 2024-02-13 | Infineon Technologies Ag | Power module with press-fit contacts |
| US12494418B2 (en) * | 2021-07-26 | 2025-12-09 | Infineon Technologies Ag | Power module with press-fit contacts |
| DE102021121797A1 (de) * | 2021-08-23 | 2023-02-23 | Infineon Technologies Ag | Leistungshalbleitermodul mit buchse oder einpresspin und verfahren zu seiner herstellung |
| US12438068B2 (en) | 2022-01-18 | 2025-10-07 | Infineon Technologies Austria Ag | Stacked module arrangement |
| US20240170378A1 (en) * | 2022-11-17 | 2024-05-23 | Semiconductor Components Industries, Llc | Power module package with molded via and dual side press-fit pin |
| WO2024110052A1 (en) * | 2022-11-25 | 2024-05-30 | Huawei Digital Power Technologies Co., Ltd. | Molded power module |
| DE102024202665A1 (de) * | 2024-03-20 | 2025-09-25 | Volkswagen Aktiengesellschaft | Verfahren zur Herstellung einer leistungselektronischen Einrichtung, leistungselektronische Einrichtung und Kraftfahrzeug |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263194A (zh) * | 2011-04-13 | 2011-11-30 | 日月光半导体制造股份有限公司 | 半导体封装与制造半导体封装的方法 |
| CN103824821A (zh) * | 2014-03-11 | 2014-05-28 | 湖南进芯电子科技有限公司 | 一种塑料密闭封装的开关电源模块及其制备方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5118027A (en) * | 1991-04-24 | 1992-06-02 | International Business Machines Corporation | Method of aligning and mounting solder balls to a substrate |
| JP4626098B2 (ja) * | 2001-06-15 | 2011-02-02 | イビデン株式会社 | プリント配線板の製造方法 |
| JP5358077B2 (ja) * | 2007-09-28 | 2013-12-04 | スパンション エルエルシー | 半導体装置及びその製造方法 |
| DE102008005547B4 (de) * | 2008-01-23 | 2013-08-29 | Infineon Technologies Ag | Leistungshalbleitermodul und Schaltungsanordnung mit einem Leistungshalbleitermodul |
| DE102008029829B4 (de) * | 2008-06-25 | 2012-10-11 | Danfoss Silicon Power Gmbh | Vertikal nach oben kontaktierender Halbleiter und Verfahren zu dessen Herstellung |
| JP5101467B2 (ja) * | 2008-11-26 | 2012-12-19 | 三菱電機株式会社 | 電力用半導体モジュール |
| JP5012772B2 (ja) | 2008-11-28 | 2012-08-29 | 三菱電機株式会社 | 半導体装置の製造方法および半導体装置 |
| JP5245880B2 (ja) * | 2009-02-04 | 2013-07-24 | 三菱電機株式会社 | 電力用半導体モジュールとその製造方法 |
| JP5262793B2 (ja) | 2009-02-13 | 2013-08-14 | 三菱電機株式会社 | 電力用半導体装置とその製造方法 |
| JP5268786B2 (ja) * | 2009-06-04 | 2013-08-21 | 三菱電機株式会社 | 半導体モジュール |
| JP2011187819A (ja) | 2010-03-10 | 2011-09-22 | Mitsubishi Electric Corp | 樹脂封止型パワーモジュールおよびその製造方法 |
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2014
- 2014-06-27 JP JP2014132430A patent/JP6249892B2/ja active Active
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2015
- 2015-03-23 US US14/665,577 patent/US9437460B2/en active Active
- 2015-06-10 DE DE102015210603.9A patent/DE102015210603B4/de active Active
- 2015-06-26 CN CN201510363009.3A patent/CN105225971B/zh active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263194A (zh) * | 2011-04-13 | 2011-11-30 | 日月光半导体制造股份有限公司 | 半导体封装与制造半导体封装的方法 |
| CN103824821A (zh) * | 2014-03-11 | 2014-05-28 | 湖南进芯电子科技有限公司 | 一种塑料密闭封装的开关电源模块及其制备方法 |
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| US9437460B2 (en) | 2016-09-06 |
| DE102015210603A1 (de) | 2015-12-31 |
| CN105225971A (zh) | 2016-01-06 |
| JP6249892B2 (ja) | 2017-12-20 |
| US20150380274A1 (en) | 2015-12-31 |
| JP2016012604A (ja) | 2016-01-21 |
| DE102015210603B4 (de) | 2019-05-23 |
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