CN105070755A - 基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管 - Google Patents
基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管 Download PDFInfo
- Publication number
- CN105070755A CN105070755A CN201510490489.XA CN201510490489A CN105070755A CN 105070755 A CN105070755 A CN 105070755A CN 201510490489 A CN201510490489 A CN 201510490489A CN 105070755 A CN105070755 A CN 105070755A
- Authority
- CN
- China
- Prior art keywords
- sigesn
- source
- gesn
- effect transistor
- raceway groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 title claims abstract description 46
- 230000005641 tunneling Effects 0.000 title claims abstract description 30
- 230000005669 field effect Effects 0.000 title claims abstract description 28
- 229910005898 GeSn Inorganic materials 0.000 title claims abstract description 25
- 239000002131 composite material Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 27
- 230000008569 process Effects 0.000 claims description 21
- 230000008020 evaporation Effects 0.000 claims description 11
- 238000001704 evaporation Methods 0.000 claims description 11
- 239000007787 solid Substances 0.000 claims description 11
- 229910052718 tin Inorganic materials 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 125000001309 chloro group Chemical group Cl* 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 238000001451 molecular beam epitaxy Methods 0.000 claims 2
- 230000004888 barrier function Effects 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract 1
- 230000008901 benefit Effects 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 231100000252 nontoxic Toxicity 0.000 description 1
- 230000003000 nontoxic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了一种基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管,主要解决现有基于IV族材料的隧穿场效应晶体管性能差的问题。其包括衬底(1)、源极(2)、沟道(3)和漏极(4)。沟道采用Sn组分为[0.05,0.12]的单晶GeSn材料;源极和漏极均采用Ge组分为[0.2,0.5],Sn组分为[0.1,0.2]的SiGeSn复合材料;源极、沟道、漏极依次竖直分布,且沟道外部依次包裹有绝缘介质(5)与栅电极(6)。本发明通过源极SiGeSn与沟道GeSn两种材料相互接触,形成II型异质隧穿结,降低了隧穿势垒高度,增大了隧穿几率和器件的隧穿电流,可用于制作大规模集成电路。
Description
技术领域
本发明属于微电子器件技术领域,特别涉及一种II型异质结隧穿场效应晶体管TFET,可用于制作大规模集成电路。
背景技术
随着集成电路的进一步发展,芯片特征尺寸的进一步缩小,单个芯片上集成的器件数目的进一步增多,功耗越来越受到人们的关注。根据ITRS数据显示,当特征尺寸缩小到32nm节点时,功耗会是预计趋势的8倍,即随着特征尺寸的逐步缩小,传统的MOS器件就功耗方面将不能满足需求。另外,场效应晶体管MOSFET尺寸的减小面临着室温下亚阈值斜率最小为60mv/decade的限制。基于量子隧穿效应的隧穿场效应晶体管TFET与MOSFET相比,没有亚阈值斜率最小为60mv/decade的限制,并且可以有效的降低功耗。因此,如何提高隧穿几率、增大隧穿电流成为TFET研究的重点。理论和实验已经证明II型异质结TFET比同质结TFET具有更高的隧穿电流及器件性能。
目前,用于隧穿场效应晶体管的半导体材料主要是III-V族材料,由于其具有较高的电子迁移率,且材料来源相对丰富,容易实现异质结,已经成功制备了许多高性能器件。这种III-V族材料存在三方面的缺点,一是污染环境,二是成本非常高,三是与Si基技术不兼容。
为了解决III-V族材料的不足,近年来由各国科学家开始对IV族材料体系在隧穿场效应晶体管方面的应用进行研究。IV族材料体系具有无毒、廉价、且易实现等优点,但是目前将IV族材料体系用于隧穿场效应晶体管仅限于Si、Ge材料,由于Si及SiGe为间接带隙材料且带隙较大,使得目前应用IV族材料体系的隧穿场效应晶体管与III-V族材料相比,性能差距较大。
发明内容
本发明的目的在于针对上述已有技术的不足,根据IV族材料体系中GeSn、SiGeSn材料的特性,提供一种SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管,以调节能带结构,减小带隙宽度,降低隧穿势垒,增大隧穿电流,提高器件的整体性能。
本发明的技术方案是这样实现的:
理论研究和实验证明,通过材料组分的调节,无论是GeSn材料,还是SiGeSn材料都能够由间接带隙材料转变为直接带隙材料,根据此原理本发明基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管,包括:衬底、源极、沟道、漏极、绝缘介质薄膜及栅电极,其特征在于:
所述源极和漏极,均采用通式为Si1-y-zGeySnz的SiGeSn复合材料,其中y为Ge的组分,z为Sn的组分,且0.1≤z≤0.2,0.2≤y≤0.5;
所述沟道,采用通式为Ge1-xSnx的GeSn单晶材料,其中x为Sn的组分,且0.05≤x≤0.12;
所述源极、沟道和漏极,在衬底上依次由下至上竖直分布,在源极与沟道的接触处形成II型异质隧穿结,所述绝缘介质薄膜和栅电极设置在沟道的外围。
本发明制作上述基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管,包括如下步骤:
1)利用分子束外延工艺,在衬底上生长Ge组分为0.2~0.5,Sn组分为0.1~0.2的SiGeSn复合材料,形成源极层;
2)利用分子束外延工艺,在源极层上生长Sn组分为0.05~0.12的单晶GeSn材料,形成沟道层;
3)利用分子束外延工艺,在沟道层上生长Ge组分为0.2~0.5,Sn组分为0.1~0.2的SiGeSn复合材料,形成漏极层;
4)利用刻蚀工艺,将源极层、沟道层和漏极层四周多余部分刻蚀掉,在中间形成源极区、沟道区和漏极区的竖直分布结构;
5)对源极区、沟道区和漏极区分别进行离子注入,即在源极区中注入能量为20KeV、剂量为1019cm-3的B元素,形成P+掺杂的源极;在沟道区中注入能量为20KeV、剂量为1015cm-3的B元素,形成P-掺杂的沟道;在漏极区中注入能量为20KeV、剂量为1019cm-3的P元素,形成N+掺杂漏极;
6)利用原子层淀积工艺,在240~260℃的温度环境下,在沟道四周环绕依次淀积绝缘介质薄膜和栅电极。
本发明的具有如下优点:
本发明由于源极采用SiGeSn单晶材料,沟道采用GeSn单晶材料,使得源极与沟道接触形成所形成的II型异质结,减小了隧穿势垒,增大了隧穿几率和隧穿电流,进而提升了隧穿场效应晶体管的整体性能。
附图说明
图1为本发明场效应晶体管的结构图;
图2为本发明场效应晶体管的制作流程示意图。
具体实施方式
为了使本发明的目的及优点更加清楚明白,以下结合附图和实施例对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅用于以解释本发明,并不用于限定本发明。
参照图1,本发明基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管包括:衬底1、源极2、沟道3、漏极4、绝缘介质薄膜5及栅电极6,其中源极2、沟道3、漏极4由下而上竖直分布于衬底1上,绝缘介质薄膜5环绕包裹于沟道3四周,栅电极6环绕包裹于绝缘介质薄膜5四周。
所述源极2和漏极4均采用通式为Si1-y-zGeySnz的SiGeSn复合材料,其中y为Ge组分,z为Sn组分,0.1≤z≤0.2,0.2≤y≤0.5。
所述沟道3采用通式为Ge1-xSnx的单晶GeSn材料,其中x为Sn的组分,0.05≤x≤0.12。
参照图2,本发明制作基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管的方法,给出如下三种实施例。
实施例1:制作基于Si0.47Ge0.33Sn0.20-Ge0.92Sn0.08材料的II型异质结隧穿场效应晶体管。
步骤1:外延源极层
利用分子束外延工艺,在Ge衬底1上,以固体Si、Ge和Sn作为蒸发源,在压强为10-4pa,温度为180℃的条件下,生长Ge组分为0.33、Sn组分为0.20的SiGeSn复合材料,形成源极层,如图2a;
步骤2:外延沟道层
利用分子束外延工艺,在源极层上,以固体Ge和Sn作为蒸发源,在压强为10-4pa,温度为180℃的条件下,生长Sn组分为0.08的GeSn单晶,形成沟道层,如图2b;
步骤3:外延漏极层
利用分子束外延工艺,在沟道层上,以固体Si、Ge和Sn作为蒸发源,在压强为10-4pa,温度为180℃的条件下,生长Ge组分为0.33、Sn组分为0.20的SiGeSn复合材料,形成漏极层如图2c。
步骤4:刻蚀形成源极区、沟道区和漏极区
利用刻蚀工艺,采用氯基原子团作为刻蚀剂,在光刻胶的掩蔽作用下,将源极层、沟道层和漏极层四周多余部分刻蚀,在中间形成自下而上的源极区、沟道区和漏极区竖直分布结构,如图2d。
步骤5:离子注入形成源极、沟道和漏极
在源极区中注入能量为20KeV、剂量为1019cm-3的B元素,形成P+掺杂的源极2;
在沟道区中注入能量为20KeV、剂量为1015cm-3的B元素,形成P-掺杂的沟道3;
在漏极区中注入能量为20KeV、剂量为1019cm-3的P元素,形成N+掺杂漏极4,如图2e;
步骤6:淀积绝缘介质薄膜和栅电极
利用原子层淀积工艺,在环境温度为240℃的N2、O2氛围下,先在沟道3四周环绕淀积绝缘介质SiO2形成绝缘介质薄膜5;再在绝缘介质薄膜5的四周环绕淀积金属薄膜形成栅电极6,从而实现在沟道3四周环绕依次生成绝缘介质薄膜5和栅电极6的结构,如图2f,完成器件制作。
实施例2:制作基于Si0.40Ge0.40Sn0.20-Ge0.90Sn0.10材料的II型异质结隧穿场效应晶体管
步骤一:利用分子束外延工艺,在Si衬底1上,以固体Si、Ge和Sn作为蒸发源,在压强为10-4pa,温度为180℃的条件下,生长Ge组分为0.40、Sn组分为0.20的SiGeSn复合材料,形成源极层,如图2a。
步骤二:利用分子束外延工艺,在源极层上,以固体Ge和Sn作为蒸发源,在压强为10-4pa,温度为180℃的条件下,生长Sn组分为0.10的GeSn单晶,形成沟道层,如图2b。
步骤三:利用分子束外延工艺,在沟道层上,以固体Si、Ge和Sn作为蒸发源,在压强为10-4pa,温度为180℃的条件下,生长Ge组分为0.40、Sn组分为0.20的SiGeSn复合材料,形成漏极层,如图2c。
步骤四:在中间形成源极区、沟道区和漏极区竖直分布的结构,如图2d。
本步骤的具体实现与实施例1的步骤4相同。
步骤五:对源极区、沟道区和漏极区进行离子注入,如图2e
本步骤的具体实现与实施例1的步骤5相同。
步骤六:利用原子层淀积工艺,在250℃环境下,在N2、O2氛围下,先在沟道3四周环绕淀积绝缘介质Al2O3形成绝缘介质薄膜5;再在绝缘介质薄膜5的四周环绕淀积金属薄膜形成栅电极6,从而实现在沟道3四周环绕依次生成绝缘介质薄膜5和栅电极6的结构,如图2f。
实施例3:制作基于Si0.30Ge0.50Sn0.20-Ge0.88Sn0.12材料的II型异质结隧穿场效应晶体管。
第一步:外延源极层
利用分子束外延工艺,在SOI衬底1上,以固体Si、Ge和Sn作为蒸发源,在压强为10-4pa,温度为180℃的条件下,生长Ge组分为0.50、Sn组分为0.20的SiGeSn复合材料,形成源极层,如图2a;
第二步:外延沟道层
利用分子束外延工艺,在源极层上,以固体Ge和Sn作为蒸发源,在压强为10-4pa,温度为180℃的条件下,生长Sn组分为0.12的GeSn单晶,形成沟道层,如图2b。
第三步:外延漏极层
利用分子束外延工艺,在沟道层上,以固体Si、Ge和Sn作为蒸发源,在压强为10-4pa,温度为180℃的条件下,生长Ge组分为0.50、Sn组分为0.20的SiGeSn复合材料,形成漏极层,如图2c;
第四步:刻蚀形成源极区、沟道区和漏极区,如图2d。
本步骤的具体实现与实施例1的步骤4相同。
第五步:离子注入形成源极、沟道和漏极,如图2e
本步骤的具体实现与实施例1的步骤5相同。
第六步:淀积绝缘介质薄膜和栅电极
利用原子层淀积工艺,在260℃环境下,在NH3氛围下,先在沟道3四周环绕淀积绝缘介质HfO2形成绝缘介质薄膜5,再在HfO2绝缘介质薄膜5的四周环绕淀积金属薄膜形成栅电极6,从而实现在沟道3四周环绕依次生成绝缘介质薄膜5和栅电极6的结构,如图2f。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (8)
1.基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管,包括:衬底(1)、源极(2)、沟道(3)、漏极(4)、绝缘介质薄膜(5)及栅电极(6),其特征在于:
所述源极(2)和漏极(4),均采用通式为Si1-y-zGeySnz的SiGeSn复合材料,其中y为Ge的组分,z为Sn的组分,且0.1≤z≤0.2,0.2≤y≤0.5;
所述沟道(3),采用通式为Ge1-xSnx的GeSn单晶材料,其中x为Sn的组分,且0.05≤x≤0.12;
所述源极(2)、沟道(3)和漏极(4),在衬底(1)上依次由下至上竖直分布,在源极(2)与沟道(3)的接触处形成II型异质隧穿结,所述绝缘介质薄膜(5)和栅电极(6)设置在沟道(3)的外围。
2.如权利要求1所述的基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管,其特征在于,衬底(1)采用的单晶Ge材料或其他单晶材料。
3.如权利要求1所述的基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管,其特征在于:绝缘介质薄膜(5)包裹在沟道(3)的外部,栅电极(6)包裹在绝缘介质薄膜(5)的外部,形成由内而外逐层环绕包裹结构。
4.基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管的制作方法,包括如下步骤:
1)利用分子束外延工艺,在衬底(1)上生长Ge组分为0.2~0.5,Sn组分为0.1~0.2的SiGeSn复合材料,形成源极层;
2)利用分子束外延工艺,在源极层上生长Sn组分为0.05~0.12的单晶GeSn材料,形成沟道层;
3)利用分子束外延工艺,在沟道层上生长Ge组分为0.2~0.5,Sn组分为0.1~0.2的SiGeSn复合材料,形成漏极层;
4)利用刻蚀工艺,将源极层、沟道层和漏极层四周多余部分刻蚀掉,在中间形成源极区、沟道区和漏极区的竖直分布结构;
5)对源极区、沟道区和漏极区分别进行离子注入,即在源极区中注入能量为20KeV、剂量为1019cm-3的B元素,形成P+掺杂的源极(2);在沟道区中注入能量为20KeV、剂量为1015cm-3的B元素,形成P-掺杂的沟道(3);在漏极区中注入能量为20KeV、剂量为1019cm-3的P元素,形成N+掺杂漏极(4);
6)利用原子层淀积工艺,在240~260℃的温度环境下,在沟道(3)四周环绕依次淀积绝缘介质薄膜(5)和栅电极(6)。
5.如权利要求4所述的方法:其中所述步骤1)和步骤3)的分子束外延,以固体Si、Ge和Sn作为蒸发源,温度为180℃,在10-4pa的压强下外延SiGeSn层。
6.如权利要求4所述的方法:其中所述步骤2)的分子束外延,是以固体Ge和Sn作为蒸发源,温度为180℃,在10-4pa的压强下外延GeSn层。
7.如权利要求4所述的方法,其中所述步骤4)的刻蚀工艺,是利用氯基原子团,在光刻胶的掩蔽作用下,刻蚀GeSn和SiGeSn。
8.如权利要求4所述的方法:其中所述步骤6)的原子层淀积工艺,是先在沟道(3)四周环绕淀积绝缘介质形成绝缘介质薄膜(5),再在绝缘介质薄膜(5)的四周环绕淀积金属薄膜形成栅电极(6)。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510490489.XA CN105070755A (zh) | 2015-08-11 | 2015-08-11 | 基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510490489.XA CN105070755A (zh) | 2015-08-11 | 2015-08-11 | 基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN105070755A true CN105070755A (zh) | 2015-11-18 |
Family
ID=54500081
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510490489.XA Pending CN105070755A (zh) | 2015-08-11 | 2015-08-11 | 基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105070755A (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109326510A (zh) * | 2017-07-31 | 2019-02-12 | 台湾积体电路制造股份有限公司 | 半导体装置及其形成方法 |
CN113517348A (zh) * | 2021-06-28 | 2021-10-19 | 西安电子科技大学芜湖研究院 | 一种直接带隙GeSn增强型nMOS器件及其制备方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103311306A (zh) * | 2013-06-26 | 2013-09-18 | 重庆大学 | 带有InAlP盖层的GeSn沟道金属氧化物半导体场效应晶体管 |
CN103824885A (zh) * | 2014-02-20 | 2014-05-28 | 重庆大学 | 带有源应变源的GeSnn沟道隧穿场效应晶体管 |
CN103824880A (zh) * | 2014-02-20 | 2014-05-28 | 重庆大学 | 双轴张应变GeSn n沟道隧穿场效应晶体管 |
CN104737295A (zh) * | 2012-11-16 | 2015-06-24 | 英特尔公司 | Cmos架构的隧穿场效应晶体管(tfet)以及制造n型和p型tfet的方法 |
US20150200288A1 (en) * | 2014-01-16 | 2015-07-16 | Xin-Gui ZHANG | Tunneling field effect transistor |
-
2015
- 2015-08-11 CN CN201510490489.XA patent/CN105070755A/zh active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104737295A (zh) * | 2012-11-16 | 2015-06-24 | 英特尔公司 | Cmos架构的隧穿场效应晶体管(tfet)以及制造n型和p型tfet的方法 |
CN103311306A (zh) * | 2013-06-26 | 2013-09-18 | 重庆大学 | 带有InAlP盖层的GeSn沟道金属氧化物半导体场效应晶体管 |
US20150200288A1 (en) * | 2014-01-16 | 2015-07-16 | Xin-Gui ZHANG | Tunneling field effect transistor |
CN103824885A (zh) * | 2014-02-20 | 2014-05-28 | 重庆大学 | 带有源应变源的GeSnn沟道隧穿场效应晶体管 |
CN103824880A (zh) * | 2014-02-20 | 2014-05-28 | 重庆大学 | 双轴张应变GeSn n沟道隧穿场效应晶体管 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109326510A (zh) * | 2017-07-31 | 2019-02-12 | 台湾积体电路制造股份有限公司 | 半导体装置及其形成方法 |
US11251087B2 (en) | 2017-07-31 | 2022-02-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including a Fin-FET and method of manufacturing the same |
US11373910B2 (en) | 2017-07-31 | 2022-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including a Fin-FET and method of manufacturing the same |
US11728414B2 (en) | 2017-07-31 | 2023-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device including a Fin-FET and method of manufacturing the same |
CN113517348A (zh) * | 2021-06-28 | 2021-10-19 | 西安电子科技大学芜湖研究院 | 一种直接带隙GeSn增强型nMOS器件及其制备方法 |
CN113517348B (zh) * | 2021-06-28 | 2023-08-04 | 西安电子科技大学芜湖研究院 | 一种直接带隙GeSn增强型nMOS器件及其制备方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102272933B (zh) | 隧道场效应晶体管及其制造方法 | |
JP6317076B2 (ja) | 量子井戸閉じ込めのための歪み層を有するデバイスおよびその製造方法 | |
CN102184955B (zh) | 互补隧道穿透场效应晶体管及其形成方法 | |
CN102074583B (zh) | 一种低功耗复合源结构mos晶体管及其制备方法 | |
CN103094338B (zh) | 半导体器件及其制造方法 | |
CN102142461B (zh) | 栅控肖特基结隧穿场效应晶体管及其形成方法 | |
CN103579324B (zh) | 一种三面源隧穿场效应晶体管及其制备方法 | |
CN102664192B (zh) | 一种自适应复合机制隧穿场效应晶体管及其制备方法 | |
CN102945861B (zh) | 条形栅调制型隧穿场效应晶体管及其制备方法 | |
WO2012085715A1 (en) | Nanowire field -effect device with multiple gates | |
WO2014055314A2 (en) | Predisposed high electron mobility transistor | |
CN102208446B (zh) | 隧穿电流放大晶体管 | |
CN103560144B (zh) | 抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法 | |
CN103985745A (zh) | 抑制输出非线性开启的隧穿场效应晶体管及制备方法 | |
CN103311305A (zh) | 硅基横向纳米线多面栅晶体管及其制备方法 | |
CN102810555A (zh) | 一种锗锡隧穿场效应晶体管及其制备方法 | |
CN105047719A (zh) | 基于InAsN-GaAsSb材料的交错型异质结隧穿场效应晶体管 | |
CN105633147A (zh) | 隧穿场效应晶体管及其制造方法 | |
CN105070755A (zh) | 基于SiGeSn-GeSn材料的II型异质结隧穿场效应晶体管 | |
CN105118858A (zh) | 纵向隧穿场效应晶体管 | |
US20150129926A1 (en) | Semiconductor device and manufacturing method thereof | |
CN103730507A (zh) | 双轴张应变GeSnn沟道金属氧化物半导体场效应晶体管 | |
CN102117834B (zh) | 一种带杂质分凝的复合源mos晶体管及其制备方法 | |
CN102117833B (zh) | 一种梳状栅复合源mos晶体管及其制作方法 | |
CN103681868B (zh) | 带有源漏应变源的GeSn n沟道金属氧化物半导体场效应晶体管 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20151118 |