CN102208446B - 隧穿电流放大晶体管 - Google Patents

隧穿电流放大晶体管 Download PDF

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CN102208446B
CN102208446B CN2011100987306A CN201110098730A CN102208446B CN 102208446 B CN102208446 B CN 102208446B CN 2011100987306 A CN2011100987306 A CN 2011100987306A CN 201110098730 A CN201110098730 A CN 201110098730A CN 102208446 B CN102208446 B CN 102208446B
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CN102208446A (zh
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黄如
詹瞻
黄芊芊
王阳元
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Peking University
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

本发明公布了一种隧穿电流放大晶体管，属于CMOS超大规模集成电路(ULSI)中场效应晶体管逻辑器件领域。该隧穿电流放大晶体管包括半导体衬底、发射极、漏极、浮空隧穿基极以及控制栅，所述漏极、浮空隧穿基极以及控制栅构成一个常规的TFET结构，而发射极的掺杂类型与浮空隧穿基极相反，发射极的位置相对于漏极在浮空隧穿基极的另一侧，并且发射极与浮空隧穿基极之间的半导体类型与浮空隧穿基极相同。与现有的TFET相比，本发明隧穿电流放大晶体管可以有效的提高器件的导通电流，提高器件的驱动能力。

Description

隧穿电流放大晶体管
技术领域
本发明属于CMOS超大规模集成电路(ULSI)中场效应晶体管逻辑器件领域，具体涉及一种利用PN结放大带带隧穿电流的场效应晶体管——隧穿电流放大晶体管。
背景技术
集成电路50多年来的发展可以以摩尔总结的规律来描述，而未来集成电路产业与系统发展的驱动力应当是降低功耗，即不以提高集成度为技术节点，而以提高性能/功耗比为标尺。当集成电路的功耗成为不可忽视的问题的时候，以低功耗设计为宗旨的绿色纳米器件便应允而生。传统MOSFET，因为受到热电势的限制，亚阈值斜率理论极限是60mV/dec，而且随着器件尺寸的降低，阈值电压降低，器件的静态漏泄电流不可避免地恶化，引起静态功耗增加，因此已经不能满足以后低功耗设计的需要。TFET(Tunneling FET)通过栅电极控制沟道能带位置，利用带带隧穿为TFET提供导通电流。这种不同于MOSFET的载流子产生机制克服了源端载流子费米分布对亚阈值特性的限制，可以进一步降低器件亚阈值斜率，降低器件静态漏泄电流进而降低器件静态功耗。但是由于存在隧穿势垒，隧穿效率的低下始终是一个难以克服的难题。窄禁带半导体的应用虽然克服了隧穿电流大小的问题，但是随之而来的漏泄电流，以及新材料带来的成本的提高都是其大规模应用的屏障。
发明内容
本发明的目的在于提供一种隧穿电流放大晶体管，该器件同时具备低漏泄电流，陡直亚阈斜率，高导通电流等优点。
本发明提供的隧穿电流放大晶体管包括半导体衬底，发射极，漏极，浮空隧穿基极以及控制栅。
所述漏极，浮空隧穿基极以及控制栅构成一个常规的TFET结构，而发射极的掺杂类型与浮空隧穿基极相反。这样发射极可以提供另一种载流子来放大浮空隧穿基极的电流。
所述发射极位置一般放置于相对于漏极在浮空隧穿基极的另一侧。一般来说发射极与浮空隧穿基极之间的半导体类型需要与浮空隧穿基极相同。可以通过选择合适的半导体衬底类型，也可以通过阱注入来实现，掺杂浓度一般不超过1e19cm-3。
所述浮空隧穿基极一般采用重掺杂以提供高的隧穿效率，发射极也采用重掺杂以提供高的电流放大能力。
本发明可以应用于硅基半导体材料，也可以应用于其他半导体材料，比如锗，砷化镓，磷化铟。也可以在器件的某一块采用其他半导体材料来形成异质结。
本发明隧穿电流放大晶体管是利用PN结放大带带隧穿电流，以N型器件为例，随着栅电压的增加，浮空隧穿基极与沟道之间电场增加，在强场作用下，浮空隧穿基极价带中的电子开始向沟道导带隧穿。这种隧穿过程向浮空隧穿基极注入空穴电流，同时向沟道注入电子电流。在隧穿电流比较小的时候，向浮空隧穿基极注入的空穴电流在发射极被复合，空穴电流再次被转换成电子电流。当隧穿电流比较大的时候，浮空隧穿基极注入的空穴会在发射极引入一定放大倍数的电子电流。放大倍数大致等于发射结两端的掺杂浓度之比。引入的电子电流会漂移到漏极被漏极收集，从而增加了导通电流大小。当栅电压归零的时候，隧穿电流被抑制，从而浮空隧穿基极注入空穴电流被截断，器件立即进入关态。
与现有的TFET相比，本发明隧穿电流放大晶体管可以有效的提高器件导通电流，提高器件的驱动能力。
附图说明
图1为本发明提出了的一种隧穿电流放大晶体管结构示意图。
图2为制备本发明隧穿电流放大晶体管的主要工艺步骤。其中图2a为有源区阱注入并推进的工艺过程。图2b为发射极与漏极注入的工艺过程。图2c为光刻浮空隧穿基极注入窗口工艺过程，图2d刻蚀多晶硅并且进行浮空隧穿基极注入，图2e为结激活过程，图2f为最终形成的隧穿电流放大晶体管结构示意图。
图中，1——多晶硅；2——栅氧；3——浮空隧穿基极；4——发射结；5——半导体衬底；6——阱；7——漏结；8——二氧化硅；9——金属接触；10——光刻胶。
具体实施方式
以下结合附图，通过具体的实施例对本发明所述的隧穿电流放大晶体管的实施方法做进一步的说明
具体实施步骤如图2所示：
1，在衬底5上生长栅氧化层2，淀积氮化硅光刻有源区，然后进行阱注入，接着进行阱推进，如图2a所示(阱的目的是提供发射极与浮空隧穿基极之间所需要的半导体材料，如果半导体衬底本身满足需要，那么可以省略阱注入这一工艺步骤)。
2，淀积多晶硅，多晶硅注入，然后光刻出发射极与漏注入窗口，以多晶硅为硬掩膜进行发射极与漏极的注入，如图2b所示。
3，涂光刻胶，然后光刻出浮空隧穿基极的注入窗口。如图2c所示。
4，刻蚀多晶硅，然后进行浮空隧穿基极注入。如图2d。
5，去胶，然后高温激活发射极，漏极以及浮空隧穿基极掺杂的杂质，如图2e所示。
6，全片淀积多晶硅，光刻接触孔，然后溅射金属，光刻出发射极，漏极，栅接触电极，
最终形成隧穿电流放大晶体管，如图2f所示。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (3)

1.一种隧穿电流放大晶体管，其特征在于，包括半导体衬底、发射极、漏极、浮空隧穿基极以及控制栅，发射极和漏极分别位于浮空隧穿基极的两侧，浮空隧穿基极和漏极之间为沟道区，在所述沟道区上设有栅介质层，在栅介质层上设有控制栅，所述漏极、浮空隧穿基极以及控制栅构成一个TFET结构，而发射极的掺杂类型与浮空隧穿基极相反。
2.如权利要求1所述的隧穿电流放大晶体管，其特征在于，发射极与浮空隧穿基极之间的半导体类型与浮空隧穿基极相同，该发射极与浮空隧穿基极之间的半导体掺杂浓度不高于1e19cm-3。
3.如权利要求1所述的隧穿电流放大晶体管，其特征在于，控制栅的栅介质层材料采用二氧化硅。
CN2011100987306A 2011-04-20 2011-04-20 隧穿电流放大晶体管 Active CN102208446B (zh)

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PCT/CN2011/074686 WO2012142781A1 (zh) 2011-04-20 2011-05-26 隧穿电流放大晶体管
US13/255,087 US8895980B2 (en) 2011-04-20 2011-05-26 Tunneling current amplification transistor
DE112011103129T DE112011103129T5 (de) 2011-04-20 2011-05-26 Verstärkungstransistor vom Typ Tunnelstrom

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CN103456636A (zh) * 2012-06-05 2013-12-18 上海华虹Nec电子有限公司 解决晶体管的IdVg曲线双峰现象的方法
CN103996713B (zh) * 2014-04-22 2017-02-15 北京大学 垂直沟道双机制导通纳米线隧穿晶体管及制备方法
CN104485354B (zh) * 2014-12-08 2017-10-27 沈阳工业大学 Soi衬底折叠栅绝缘隧穿增强晶体管及其制造方法
CN104409490B (zh) * 2014-12-08 2017-10-20 沈阳工业大学 Soi衬底双栅绝缘隧穿基极双极晶体管及其制造方法
CN104465737B (zh) * 2014-12-08 2017-07-21 沈阳工业大学 体硅双栅绝缘隧穿基极双极晶体管及其制造方法
CN104465776B (zh) * 2014-12-12 2017-09-15 西安邮电大学 一种双栅电极的半导体器件其制造方法及应用
CN104465775B (zh) * 2014-12-12 2018-01-05 西安邮电大学 基于陷阱产生机制的双漏区半导体器件其制造方法及应用
CN104485358B (zh) * 2014-12-12 2018-01-05 西安邮电大学 一种基于陷阱产生机制的半导体器件其制造方法及应用

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