CN106783986B - 一种硅基异质结遂穿场效应晶体管 - Google Patents

一种硅基异质结遂穿场效应晶体管 Download PDF

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CN106783986B
CN106783986B CN201611077051.XA CN201611077051A CN106783986B CN 106783986 B CN106783986 B CN 106783986B CN 201611077051 A CN201611077051 A CN 201611077051A CN 106783986 B CN106783986 B CN 106783986B
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刘丽蓉
王勇
丁超
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Shenzhen Youbikang Technology Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391Gated diode structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

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Abstract

本发明公布了一种硅基异质结遂穿场效应晶体管结构,该器件结构包括:一N型掺杂的硅半导体层;一本征的硅基半导体层;一P型硅锗过渡层;一P型锗半导体层;一在N型掺杂的硅半导体层上形成的漏电极;一在P型锗半导体材料上形成的源电极;一在I型半导体层上生长的氧化铪介质层;一在氧化铪介质层上形成的栅金属电极。

Description

一种硅基异质结遂穿场效应晶体管
技术领域
本发明属于微电子领域,具体涉及一种硅基异质结遂穿场效应晶体管结构。
背景技术
基于硅基CMOS技术的现代集成电路随着CMOS器件的特征尺寸的不断缩小,在集成度、功耗和器件特性方面不断进步。在CMOS技术节点进入10纳米以后,面临着工艺与物理特性两方面的挑战,锗材料以其高电子迁移率特性和与硅工艺兼容特性,被认为是替代硅作为器件沟道材料的可选项之一,成为当前的研究热点和技术攻关的重要方向。另一方面采用遂穿效应研制的遂穿场效应晶体管(TFET),以其低功耗、低亚阈值摆副的特点成为存储器单元应用器件的重要研究方向。在此背景下,将硅锗或者锗材料用于提高硅基遂穿场效应晶体管特性的研究备受科技领域和工业领域的关注,成为提高遂穿场效应晶体管器件性能的重要技术突破方向。
发明内容
本发明的目的在于提出一种硅基异质结沟道的场效应晶体管结构,以提供硅基TFET器件无法达到的最大饱和电流的同时,保持器件的电流开关比。
本发明提供一种硅基异质结遂穿场效应晶体管结构,具体包括:
一N型掺杂的硅半导体层;
一本征的硅基半导体层;
一P型硅锗过渡层;
一P型锗半导体层;
一在本征半导体层上生长的氧化铪介质层;
一在氧化铪介质层上形成的栅金属电极;
一在P型锗半导体材料上形成的源电极;
一在N型掺杂的硅半导体层上形成的漏电极。
根据所述的一种硅基异质结遂穿场效应晶体管结构,其特征在于P型硅锗过渡层厚度为16纳米,材料结构为Si0.8Ge0.2(4纳米),Si0.5Ge0.5(4纳米),Si0.3Ge0.7(4纳米),Si0.2Ge0.8(4纳米),掺杂浓度为5×1019cm-3
根据所述的一种硅基异质结遂穿场效应晶体管结构,其特征在于P型锗半导体层的厚度为5纳米,掺杂浓度为5×1019cm-3
根据案所述的一种硅基异质结遂穿场效应晶体管结构,其特征在于本征半导体层上的氧化铪介质层厚度为3纳米。
根据所述的一种硅基异质结遂穿场效应晶体管结构,其特征在于栅金属电极为钨金属,采用ICP刻蚀的方法在垂直结构侧壁形成金属电极。
有益效果
通过本方发明的实施,本发明可以通过硅锗与硅半导体能嗲结构的差异,将源端材料的价带提高,高于漏端材料的价带,从而实现PN结遂穿势垒和遂穿距离的减少,提高器件电子遂穿效率,提高器件的最大饱和电流;另一方面,通过PN结中间加入本征层,降低器件在零偏压下的泄露电流;从而提高器件的电流开关比。
附图说明:
为了全面理解实施例的优势,参考图如下:
图1:本实施例的器件结构。
具体实施例:
下面详细讨论本发明实施例的制造和使用。本实施例仅仅是说明性的,不能用于限制本发明的范围。
本发明提供一种硅基异质结遂穿场效应晶体管结构,具体包括:
一100纳米厚度的N型掺杂的硅半导体层(101);
一在N型掺杂硅半导体层(101)上生长的10纳米厚度的本征的硅基半导体层(102);
一在本征硅基半导体层(102)上生长的P型硅锗过渡层(103);
一在P型硅锗过渡层(103)上生长的P型锗半导体层(104);
一在本征半导体层上生长的氧化铪介质层(105);
一在氧化铪介质层(105)上形成的栅金属电极(106);
一在P型锗半导体材料(104)上形成的源电极(107);
一在N型掺杂的硅半导体层(101)上形成的漏电极(108)。
根据所述的一种硅基异质结遂穿场效应晶体管结构,其特征在于P型硅锗过渡层(103)厚度为16纳米,材料结构为Si0.8Ge0.2(4纳米),Si0.5Ge0.5(4纳米),Si0.3Ge0.7(4纳米),Si0.2Ge0.8(4纳米),掺杂浓度为5×1019cm-3
根据所述的一种硅基异质结遂穿场效应晶体管结构,其特征在于P型锗半导体层(104)的厚度为5纳米,掺杂浓度为5×1019cm-3
根据案所述的一种硅基异质结遂穿场效应晶体管结构,其特征在于本征半导体层上的氧化铪介质层(105)厚度为3纳米。
根据所述的一种硅基异质结遂穿场效应晶体管结构,其特征在于栅金属电极(106)为钨金属,采用ICP刻蚀的方法在垂直结构侧壁形成金属电极。

Claims (1)

1.一种硅基异质结遂穿场效应晶体管结构,包括:
一N型掺杂的硅半导体层;
一本征的硅基半导体层;
一P型硅锗过渡层;
一P型锗半导体层;
一在本征半导体层上生长的氧化铪介质层;
一在氧化铪介质层上形成的栅金属电极;
一在P型锗半导体材料上形成的源电极;
一在N型掺杂的硅半导体层上形成的漏电极;
P型硅锗过渡层厚度为16纳米,材料结构为4纳米的Si0.8Ge0.2,4纳米的Si0.5Ge0.5,4纳米的Si0.3Ge0.7,4纳米的Si0.2Ge0.8,掺杂浓度为5×1019cm-3
P型锗半导体层的厚度为5纳米,掺杂浓度为5×1019cm-3
本征半导体层上的氧化铪介质层厚度为3纳米;
栅金属电极为钨金属,采用ICP刻蚀的方法在垂直结构侧壁形成金属电极。
CN201611077051.XA 2016-11-29 2016-11-29 一种硅基异质结遂穿场效应晶体管 Active CN106783986B (zh)

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CN103262249A (zh) * 2010-12-17 2013-08-21 英特尔公司 隧道场效应晶体管
CN105047703A (zh) * 2014-04-30 2015-11-11 台湾积体电路制造股份有限公司 隧道场效应晶体管及其制造方法
CN105633147A (zh) * 2014-10-27 2016-06-01 中国科学院微电子研究所 隧穿场效应晶体管及其制造方法

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CN103262249A (zh) * 2010-12-17 2013-08-21 英特尔公司 隧道场效应晶体管
CN105047703A (zh) * 2014-04-30 2015-11-11 台湾积体电路制造股份有限公司 隧道场效应晶体管及其制造方法
CN105633147A (zh) * 2014-10-27 2016-06-01 中国科学院微电子研究所 隧穿场效应晶体管及其制造方法

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