CN1050701C - 半导体器件中的晶体管及其制造方法 - Google Patents

半导体器件中的晶体管及其制造方法 Download PDF

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Publication number
CN1050701C
CN1050701C CN96108211A CN96108211A CN1050701C CN 1050701 C CN1050701 C CN 1050701C CN 96108211 A CN96108211 A CN 96108211A CN 96108211 A CN96108211 A CN 96108211A CN 1050701 C CN1050701 C CN 1050701C
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CN
China
Prior art keywords
groove
soi layer
liner
forms
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN96108211A
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English (en)
Chinese (zh)
Other versions
CN1148273A (zh
Inventor
黄儁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of CN1148273A publication Critical patent/CN1148273A/zh
Application granted granted Critical
Publication of CN1050701C publication Critical patent/CN1050701C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
CN96108211A 1995-06-20 1996-06-19 半导体器件中的晶体管及其制造方法 Expired - Fee Related CN1050701C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR16420/95 1995-06-20
KR1019950016420A KR100227644B1 (ko) 1995-06-20 1995-06-20 반도체 소자의 트랜지스터 제조방법

Publications (2)

Publication Number Publication Date
CN1148273A CN1148273A (zh) 1997-04-23
CN1050701C true CN1050701C (zh) 2000-03-22

Family

ID=19417585

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96108211A Expired - Fee Related CN1050701C (zh) 1995-06-20 1996-06-19 半导体器件中的晶体管及其制造方法

Country Status (4)

Country Link
JP (1) JPH098308A (enrdf_load_stackoverflow)
KR (1) KR100227644B1 (enrdf_load_stackoverflow)
CN (1) CN1050701C (enrdf_load_stackoverflow)
TW (1) TW301034B (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3408437B2 (ja) 1998-10-30 2003-05-19 シャープ株式会社 半導体装置の製造方法
KR100343472B1 (ko) * 2000-08-31 2002-07-18 박종섭 모스 트랜지스터의 제조방법
US6780686B2 (en) * 2002-03-21 2004-08-24 Advanced Micro Devices, Inc. Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions
US7022575B2 (en) * 2003-10-29 2006-04-04 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0487220A2 (en) * 1990-11-19 1992-05-27 Mitsubishi Denki Kabushiki Kaisha SOI-Field effect transistor and method of manufacturing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02185068A (ja) * 1989-01-12 1990-07-19 Toshiba Corp 電界効果型トランジスタの製造方法
JPH0766972B2 (ja) * 1989-06-22 1995-07-19 三菱電機株式会社 半導体装置の製造方法
JPH03155166A (ja) * 1989-11-14 1991-07-03 Fuji Electric Co Ltd 薄膜半導体素子
JPH05259457A (ja) * 1992-03-16 1993-10-08 Sharp Corp 薄膜トランジスタ

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0487220A2 (en) * 1990-11-19 1992-05-27 Mitsubishi Denki Kabushiki Kaisha SOI-Field effect transistor and method of manufacturing the same

Also Published As

Publication number Publication date
KR100227644B1 (ko) 1999-11-01
KR970004069A (ko) 1997-01-29
JPH098308A (ja) 1997-01-10
CN1148273A (zh) 1997-04-23
TW301034B (enrdf_load_stackoverflow) 1997-03-21

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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20000322