CN1148273A - 半导体器件中的晶体管及其制造方法 - Google Patents
半导体器件中的晶体管及其制造方法 Download PDFInfo
- Publication number
- CN1148273A CN1148273A CN96108211A CN96108211A CN1148273A CN 1148273 A CN1148273 A CN 1148273A CN 96108211 A CN96108211 A CN 96108211A CN 96108211 A CN96108211 A CN 96108211A CN 1148273 A CN1148273 A CN 1148273A
- Authority
- CN
- China
- Prior art keywords
- soi layer
- groove
- liner
- transistor
- soi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000012212 insulator Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000005530 etching Methods 0.000 description 3
- 230000005284 excitation Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
一种半导体器件中的晶体管及其制造方法,能提高其激励速度,其中利用了内部形成有厚的SOI(绝缘体上的硅)层的一个晶片,通过形成较沟道和LDD区(轻掺杂漏区)更厚的结区,可降低结区本身的电阻。
Description
本发明涉及半导体器件中的晶体管及其制造方法,特别是涉及这样一种半导体器件中的晶体管及其制造方法,其利用其中形成有厚的SOI(绝缘体的上硅)层的晶片形成一个较沟道和LDD区(轻掺杂漏区)更厚的结区,能改善激励速度。
目前,随着半导体器件的集成度越来越高,SOI晶体管能用作下一代的晶体管。SOI晶体管作为一种器件,其电性能,例如击穿特性和阈值电压,与通常的MOS(金属氧化物半导体)晶体管相比,有了明显的改进。这种SOI晶体管是在SOI晶片上形成的。就SOI晶片的结构看,其中的SOI层(例如下面的硅基片)、绝缘层和上面的硅层(SOI层),其叠置情况是与通常所用的体型(bulk-type)晶片不同的。制造半导体器件中的晶体管的一般方法可参看图1A和图1B来说明。
如图1A所示,一个衬垫氧化膜4和多晶硅层5相继形成在SOI晶片20上,晶片20中形成有叠层结构的硅基片1、绝缘层2和SOI层3。然后使多晶硅层5和衬垫氧化膜4成型,以形成门极5A。注入低浓度的杂质离子,以便在门极5A两侧的SOI层3中形成一LDD区7。然后,如图1B所示,在门板5A的两侧壁处形成氧化膜衬垫6,接着通过注入高浓度杂质离子在暴露的SOI层3中形成结区8。由于形成的SOI层3很薄,从500至1500(埃),因此结区8本身内的电阻增大。结果,晶体管的激励速度降低,使器件的特性变坏。
因此,本发明的目的是提供一种半导体器件中的晶体管及其制造方法,其利用其中形成有厚的SOI层的晶片形成一个较沟道和LDD区更厚的结区,能解决上述问题。
为达到上述目的,本发明的半导体器件的特点在于包括:一个SOI晶片,具有一硅基片、一绝缘层和一SOI层,其中在SOI层的选择区域上形成有一沟槽;一个门氧化膜,在沟槽内形成,以使SOI层的侧面部分暴露;一个门极,形成在门氧化膜上,而在门极的两侧壁处形成有衬垫;LDD区,形成在衬垫下的SOI层中;以及结区,形成在LDD区外侧部分处SOI层中。
本发明的制造半导体器件中晶体管的方法,其特点在于包括以下步骤:在SOI晶片的SOI层中形成一沟槽;在SOI晶片的整个上部上相继形成门氧化膜和多晶硅层;使多晶硅层和门氧化膜相继成型而在沟槽内形成门极;注入低浓度杂质离子而在暴露的SOI层处形成LDD区;在门极两侧壁上形成衬垫; 以及注入高浓度杂质离子而在暴露的SOI层处形成结区。
为了更充分了解本发明的特点和目的,以下结合附图更详细地加以说明。附图中:
图1A和图1B是为说明制造半导体器件中晶体管的一般方法的器件剖面图;
图2A至图2E是为说明制造半导体器件中晶体管的本发明方法的器件剖视图。
全部附图中同样的标号表示相同的部分。
以下参看附图详细地说明本发明。
图2A至图2E为器件剖面图,用以说明本发明的制造半导体器件中晶体管的方法。
参见图2A,第一光阻材料9覆盖在SOI晶片20A上,晶片20A中以叠层结构形成有硅基片10、绝缘层12和SOI层13,其中SOI层13形成为3000至5000的厚度。使第一光阻材料9成型,以使其中将要形成沟道和LDD区的SOI层13的一部分暴露,然后将其蚀刻到所需的深度,从而形成沟槽11。以氧化膜和氮化膜形成绝缘层。当蚀刻过程完成后,留在沟槽11下面的SOI层13的厚度A为500至1500。
图2B示出器件的一个剖面图,其中,当去除第一光阻材料9之后,在SOI层13的整个上部上相继形成门氧化膜14、多晶硅层15和第二光阻材料16,然后利用供形成门极用的掩膜第二光阻材料16成型。
图2C示出器件的一个剖面图,其中,在利用成型的第二光阻材料16作为掩膜而相继蚀刻多晶硅层15和门氧化膜14之后,除去成型了的第二光阻材料16,从而形成门极15A。
图2D示出器件的一个剖面图,其中,通过注入低浓度的杂质离子,在沟槽11内暴露的SOI层13处形成LDD区17。
参见图2E,在SOI层的整个上部上形成氧化膜。通过覆盖-蚀刻该氧化膜而使门极15A的表面曝光,从而在门极15A的两侧壁和LDD区17的上部形成氧化膜衬垫16。利用衬垫16和门极15A作为掩膜,通过注入高浓度的杂质离子而形成结区18。通过控制沟槽区的长度可以改变LDD区的长度,而衬垫尺寸则可以在内部延伸,从沟槽壁延伸出,且可以延伸到沟槽壁之外。
由以上过程制出的SOI晶体管,其沟道可保持为常规晶体管的沟道厚度,因为其中要形成沟道和LDD区的部分向沟槽结构部分蚀刻到所需要的深度。这一过程通过使结区形成与SOI层的厚度相同的深度,还能降低其自身电阻。
按照以上所述的本发明。晶体管中沟道区的厚度可减至最小,其中利用了内部形成有厚的SOI层的一个晶片,将内部要形成沟道和LDD区的SOI层的那一部分向沟槽结构部分蚀刻到所需要的深度,然后使结区形成具有较沟道和LDD区更厚的厚度。本发明有突出的效果,它能使沟道区的厚度减至最小,并通过增加结区的结的深度从而降低结区的电阻,还能提高晶体管的激励速度。
尽管以上仅描述了具有本发明原理的带有特殊性的一个较佳实施例,但是应当了解,本发明并不限于这一实施例。在本发明的精神和范围内可以作出各种适当的变化,以进一步实施本发明。
Claims (12)
1.一种半导体器件中的晶体管,包括:
一个SOI晶片,具有一硅基片、一绝缘层和一SOI层,其中在所述SOI层的选择区域上形成有一沟槽;
一个门氧化膜,在所述沟槽内形成,以使所述SOI层的侧面部分暴露;
一个门极,形成在所述门氧化膜上,而在所述门极的两侧壁处形成有衬垫;
LDD区,形成在所述衬垫下的所述SOI层中;以及
结区,形成在所述LDD区外侧部分处的所述SOI层中。
2.如权利要求1所述的晶体管,其特征在于,所述SOI层的总厚度为3000至5000,而留在所述沟槽下的所述SOI层的厚度为500至1500。
3.如权利要求1所述的晶体管,其特征在于,所述绝缘层是由氧化膜或氮化膜形成的。
4.如权利要求1所述的晶体管,其特征在于,所述衬垫是在与所述沟槽的侧壁隔开的部分中形成的。
5.如权利要求1所述的晶体管,其特征在于,所述衬垫形成为所述沟槽的侧壁。
6.如权利要求1所述的晶体管,其特征在于,所述衬垫形成为延伸到所述沟槽之外。
7.一种制造半导体器件中晶体管的方法,包括以下步骤:
在SOI晶片的SOI层中形成一沟槽;
在所述SOI晶片的整个上部上相继形成门氧化膜和多晶硅层;
使所述多晶硅层和所述门氧化膜相继成型而在沟槽内形成门极;
注入低浓度杂质离子而在暴露的SOI层处形成LDD区;
在所述门极两侧壁上形成衬垫;以及
注入高浓度杂质离子而在暴露的SOI层处形成结区。
8.如权利要求7所述的制造晶体管的方法,其特征在于,使所述SOI层的总厚度为3000至5000,而使留在所述构槽下的所述SOI层的厚度为500至1500。
9.如权利要求7所述的制造晶体管的方法,其特征在于,以一氧化膜或氮化膜形成所述绝缘层。
10.如权利要求7所述的制造晶体管的方法,其特征在于,在与所述沟槽的侧壁隔开的部分中形成所述衬垫。
11.如权利要求7所述的制造晶体管的方法,其特征在于,使所述衬垫形成为所述沟槽的侧壁。
12.如权利要求7所述的制造晶体管的方法,其特征在于,使所述衬垫延伸到所述沟槽之外。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR16420/95 | 1995-06-20 | ||
KR1019950016420A KR100227644B1 (ko) | 1995-06-20 | 1995-06-20 | 반도체 소자의 트랜지스터 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1148273A true CN1148273A (zh) | 1997-04-23 |
CN1050701C CN1050701C (zh) | 2000-03-22 |
Family
ID=19417585
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN96108211A Expired - Fee Related CN1050701C (zh) | 1995-06-20 | 1996-06-19 | 半导体器件中的晶体管及其制造方法 |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPH098308A (zh) |
KR (1) | KR100227644B1 (zh) |
CN (1) | CN1050701C (zh) |
TW (1) | TW301034B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1316576C (zh) * | 2003-10-29 | 2007-05-16 | 三洋电机株式会社 | 半导体装置的制造方法 |
CN100399582C (zh) * | 2002-03-21 | 2008-07-02 | 先进微装置公司 | 完全耗尽型绝缘层上硅结构的掺杂方法和包含所形成掺杂区的半导体器件 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3408437B2 (ja) | 1998-10-30 | 2003-05-19 | シャープ株式会社 | 半導体装置の製造方法 |
KR100343472B1 (ko) * | 2000-08-31 | 2002-07-18 | 박종섭 | 모스 트랜지스터의 제조방법 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02185068A (ja) * | 1989-01-12 | 1990-07-19 | Toshiba Corp | 電界効果型トランジスタの製造方法 |
JPH0766972B2 (ja) * | 1989-06-22 | 1995-07-19 | 三菱電機株式会社 | 半導体装置の製造方法 |
JPH03155166A (ja) * | 1989-11-14 | 1991-07-03 | Fuji Electric Co Ltd | 薄膜半導体素子 |
JP2660451B2 (ja) * | 1990-11-19 | 1997-10-08 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JPH05259457A (ja) * | 1992-03-16 | 1993-10-08 | Sharp Corp | 薄膜トランジスタ |
-
1995
- 1995-06-20 KR KR1019950016420A patent/KR100227644B1/ko not_active IP Right Cessation
-
1996
- 1996-06-06 TW TW085106813A patent/TW301034B/zh active
- 1996-06-13 JP JP8152113A patent/JPH098308A/ja active Pending
- 1996-06-19 CN CN96108211A patent/CN1050701C/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100399582C (zh) * | 2002-03-21 | 2008-07-02 | 先进微装置公司 | 完全耗尽型绝缘层上硅结构的掺杂方法和包含所形成掺杂区的半导体器件 |
CN1316576C (zh) * | 2003-10-29 | 2007-05-16 | 三洋电机株式会社 | 半导体装置的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1050701C (zh) | 2000-03-22 |
TW301034B (zh) | 1997-03-21 |
KR970004069A (ko) | 1997-01-29 |
JPH098308A (ja) | 1997-01-10 |
KR100227644B1 (ko) | 1999-11-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3513212B2 (ja) | 半導体装置の製法 | |
US5397715A (en) | MOS transistor having increased gate-drain capacitance | |
US20020003256A1 (en) | MOS semiconductor device and method of manufacturing the same | |
EP0749165A2 (en) | Thin film transistor in insulated semiconductor substrate and manufacturing method thereof | |
KR930011895B1 (ko) | 집적회로소자 및 그 제조방법 | |
JP3207181B2 (ja) | 電界効果トランジスタ | |
US4316203A (en) | Insulated gate field effect transistor | |
EP0782182A2 (en) | MOS transistor and manufacturing method of the same | |
JP3206026B2 (ja) | 高電圧用misfetを備える半導体装置 | |
CN1050700C (zh) | 半导体器件中的晶体管及其制造方法 | |
WO2001043197A2 (en) | Source/drain-on-insulator (s/doi) field effect transistors and method of fabrication | |
US5661048A (en) | Method of making an insulated gate semiconductor device | |
JPH07326742A (ja) | 半導体装置およびその製造方法 | |
US5418391A (en) | Semiconductor-on-insulator integrated circuit with selectively thinned channel region | |
EP0114491B1 (en) | Semiconductor integrated circuit device with output stage | |
CN1050701C (zh) | 半导体器件中的晶体管及其制造方法 | |
JPH0653513A (ja) | 半導体装置および半導体集積回路装置 | |
CN1146048C (zh) | Cmos器件及其制造方法 | |
JPH07326752A (ja) | モスフェット(mosfet)及びその製造方法 | |
JPH0454970B2 (zh) | ||
US6440787B1 (en) | Manufacturing method of semiconductor device | |
JPH0513756A (ja) | Mis型半導体装置およびその製造方法 | |
US20050142720A1 (en) | Method for fabricating MOS field effect transistor | |
KR0147372B1 (ko) | 반도체장치 및 그 제조방법 | |
JPH11135739A (ja) | Dramチップの改良された製造法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20000322 |