CN1170963A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN1170963A
CN1170963A CN97113870A CN97113870A CN1170963A CN 1170963 A CN1170963 A CN 1170963A CN 97113870 A CN97113870 A CN 97113870A CN 97113870 A CN97113870 A CN 97113870A CN 1170963 A CN1170963 A CN 1170963A
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金载甲
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MagnaChip Semiconductor Ltd
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    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

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Abstract

本发明公开了向形成第2P沟的衬底施加负电压时,第1P沟与第2P沟间的阈值电压差最小化的同时,也能使工序最简化的半导体装置及其制造方法。该半导体装置包括:元件分离用绝缘膜;半导体衬底;N型埋入层;P型第1沟区域;P型第2沟区域;N型第1沟区域;N型第2沟区域;分别在第2沟表面附近及第1沟表面附近设置P型第1及第2掺杂区域,第1掺杂区域的浓度比第2掺杂区域的浓度低。

Description

半导体装置及 其制造方法
本发明涉及半导体装置及其制造方法，尤其是涉及具体的具有三重沟构造的半导体装置及其制造方法。
一般，为与半导体装置的高集成化及功能的复杂化相适应，对集成电路有了特殊的性能要求。其中之一是，在P型衬底和上述P型衬底内形成的N沟内分别形成P沟，在二个P沟内形成N型MOS晶体管，因而能够使形成的NMOS晶体管特性各不相同。上述P型衬底形成的P沟称为第1P沟，N沟内形成的P沟称为第2P沟。
特别地，在DRAM的情况下，给存储单元区域的衬底附加一定值的负电压(negative voltage)时，则寄生结合电容减小，读出安全系数增加，并且能够消除结合区域的漏泄电流，增加数据的保存时间(retention time)。
然而，上述构造的半导体装置，N沟内形成的第2P沟与第1P沟电气绝缘，且第2沟与第1P沟不同，衬底加有负电压，故存在第2P沟内的晶体管阈值电压增加的问题。
而且，第2P沟是在N沟内形成的，故存在第2P沟的特性不良的问题。
因此，本发明的目的是提供一种向第2P沟形成的衬底施加负电压时，第1P沟与第2P沟间的阈值电压差最小化的同时，也能够使工序最简化的半导体装置及其制造方法。
本发明的另一目的是提供一种不在N沟内形成第2P沟，而能够改善沟特性的半导体装置及其制造方法。
本发明的半导体装置，包括：在单位元件中形成用于定义第1、第2及第3活性区域的元件分离用绝缘膜并掺杂P型杂质的半导体衬底；从部分包含上述第1活性区域和其两侧的元件分离绝缘膜区域表面到所定深度形成的N型埋入层；在上述第1活性区域邻接的第2活性区域下部形成的P型第1沟区域；从部分包含上述第1活性层区域和其两侧的元件分离绝缘膜区域表面到所定深度的P型第2沟区域(这里，上述P型第2沟区域与上述埋入层互相以所定间隔成分离的状态存在)；在部分包含的上述第2活性区域邻接的第3活性区域及其两侧的元件分离绝缘膜区域下部形成的N型第1沟区域；定义上述第1活性区域与第2活性区域的元件分离绝缘膜下部形成的N型第2沟区域；分别在上述第1活性区域的上述第2沟表面附近及上述第2活性区域的上述第1沟表面附近设置用于调节阈值电压的P型第1及第2掺杂区域，上述第1掺杂区域的浓度比上述第2掺杂区域的浓度低。
另外，本发明的半导体元件制造方法，包括：在P型半导体衬底的单位元件内形成用于定义第1、第2及第3三个部分活性区域的元件分离用绝缘膜阶段；从部分包含上述第1活性区域及其两侧的元件分离绝缘膜区域表面到所定深度形成N型埋入层阶段；在部分包含定义上述第1活性区域邻接的第2活性区域的元件分离绝缘膜下部区域和上述第2活性区域邻接的第3活性区域及其两侧的元件分离绝缘膜的下部区域形成N型第1沟区域及N型第2沟区域阶段；在部分包含上述第1活性区域及其两侧的元件分离绝缘膜区域的下部形成P型第3沟区域、在上述第2活性区域的下部形成P型第4沟区域阶段；在上述第1活性区域的上述第3沟表面附近及上述第2活性区域的上述第4沟表面附近形成用于调节阈值电压的P型第1及第2掺杂区域。这时，形成上述第1掺杂区域的浓度比上述第2掺杂区域的浓度低。
基于上述过程形成的半导体元件，给第1P沟施加接地电压，第2P沟施加负电压。第2P沟形成的阈值电压调节区域比第1P沟的阈值电压调节区域具有较低的浓度，故第2P沟的阈值电压比第1P沟的电压低。
另外，本发明的第2P沟并非最适合于在N沟内，而是在由N沟及N型埋入层包围的半导体衬底内部形成。
图1A至图1D是说明本发明的半导体装置及其制造方法的剖面图。
下面参照附图说明本发明的实施例。
首先，参照图1A，在半导体衬底，例如包含P型杂质的半导体衬底1，形成用于定义活性区域的元件分离用绝缘膜2。在整个结构物表面，以公知的氧化膜方式，形成保护衬底的屏蔽氧化膜100。为使以后在N沟内形成第2P沟的预定部分露出，形成有感光膜的第1掩膜图形110。这时，第1掩膜图形110的厚度最好是3～5μm。然后，将N型杂质，例如将磷原子(P)以1～2Mev的能量和1×1012～5×1013ions/cm2浓度离子注入衬底1，从露出的衬底到所定位置形成N型埋入层200。之后，将N型杂质，例如将磷原子(P)以30～80Kev的能量和2×1011～5×1012ions/cm2浓度离子注入，在半导体衬底1表面形成调节阈值电压的第1阈值电压调节层12A。然后，以公知的感光膜除去方法除去第1掩膜图形110。
下面，参照图1B，为露出N沟预定区域，通过光刻工艺，形成第2掩膜图形120。这时，第2掩膜图形120不仅是在N沟的预定区域形成，而且在衬底深处形成的N型埋入层200的边缘部分也露出。第2掩膜图形120的厚度最好是2～4μm。而且，将第2掩膜图形120作为离子注入掩膜，将调节阈值电压用N型杂质，例如将磷原子(P)以700Kev～1.5Mev的能量和5×1012～5×1013ions/cm2浓度离子注入，形成第1N沟12及与N型埋入层200的一定部分结合的第2N沟12′。然后，以公知的除去方法除去第2掩膜120。
参照图1C，为露出P沟的预定区域，以2～4μm的厚度形成第3掩膜图形130。然后将露出的半导体衬底1的P型杂质，例如将硼原子(boron)以500～700Kev的能量和1×1013～5×1013ions/cm2浓度离子注入，从而形成第1P沟13及第2P沟113。这时，本发明的第2P沟113不象以往那样在N沟内形成，而是在由N型埋入层200，及与埋入层200边缘结合的第2N沟12′包围的半导体衬底1内形成。接着，在前阶段形成的第1P沟13及第2P沟113的表面，将调节阈值电压的P型杂质，例如硼，以70～120Kev的能量和5×1012～5×1013ions/cm2浓度一次离子注入，或以10～30Kev的能量和1×1012～5×1012ions/cm2浓度二次离子注入，形成注入了3P型杂质的第2阈值电压调节层13A。这时，由于在第2P沟已经形成N型的第1阈值电压调节层12A和P型的第2阈值电压调节层13A，故互相计数掺杂(counter doping)，使第2P沟113内的阈值电压调节层12A，13A，具有比第1P沟13内的阈值电压调节层13A更低的浓度。因此，第2P沟113的阈值电压比第1P沟13低。
图1D是在上述结果物形成MOS晶体管的门电极图，除去第3掩膜图形和结果物洗净完了之后，由众所周知的方法形成门氧化膜3和门电极14A，24A，24B。这里，未说明标号13B是由第2P沟内的第1阈值电压调节层12A和第2阈值电压调节层13A的计数掺杂而形成的，是具有低浓度的第3阈值电压调节层。
基于上述过程所形成的半导体元件，第1P沟13施加有接地电压，第2P沟113施加有负电压。在第2P沟113形成的第3阈值电压调节层13B由于具有比第1P沟13的阈值电压调节层13A低的浓度，故第2P沟113的阈值电压比第1P沟13的阈值电压低。因此，即使施加其它的电压，第1及第2沟形成的MOS晶体管的阈值电压也能够保持同一值。
另外，本发明中，第2P沟113在N沟内没有最优化，是在由N沟及N型埋入层包围的半导体衬底内部形成的，具有能够提高P沟特性的优点。从而增大元件特性及收获率。

Claims (20)

1.一种半导体装置，其特征在于，包括：掺杂第1型杂质的半导体衬底；在上述半导体衬底的单位元件中用于定义第1、第2及第3活性区域的元件分离用绝缘膜；从部分包含上述第1活性区域及其两侧的元件分离绝缘膜区域表面到所定深度形成的第2杂质型的埋入层；在上述第1活性区域邻接的第2活性区域下部形成的第1杂质型的第1沟区域；从部分包含上述第1活性区域及其两侧的元件分离绝缘膜区域表面到所定深度的第1杂质型的第2沟区域，上述第1杂质型的第2沟区域与上述埋入层互相以所定间隔成分离状态存在；在部分包含的上述第2活性区域邻接的第3活性区域及其两侧的元件分离绝缘膜区域下部形成的第2杂质型的第1沟区域；定义上述第1活性区域与第2活性区域的元件分离绝缘膜下部形成的第2杂质型的第2沟区域；分别在上述第1活性区域的上述第2沟表面附近及上述第2活性区域的上述第1沟表面附近设置用于调节阈值电压的第1杂质型的第1及第2掺杂区域，上述第1掺杂区域的浓度比上述第2掺杂区域的浓度低。
2.如权利要求1所述的半导体装置，其特征在于，上述第2杂质型的第2沟所定区域与上述埋入层的所定区域部分重叠。
3.如权利要求2所述的半导体装置，其特征在于，还包含在上述第1活性区域上形成的二个门电极。
4.如权利要求3所述的半导体装置，其特征在于，还包含在上述第2活性区域上形成的一个门电极。
5.如权利要求1所述的半导体装置，其特征在于，上述第1杂质型是P型，第2杂质型是N型。
6.如权利要求5所述的半导体装置，其特征在于，上述第1掺杂区域包含硼原子，上述第2掺杂区域包含硼原子和磷原子。
7.一种半导体元件的制造方法，其特征在于，包括：提供第1杂质型的半导体衬底阶段；在上述半导体衬底的单位元件内形成定义第1、第2及第3三个部分活性区域的元件分离用绝缘膜阶段；从部分包含上述第1活性区域及其两侧的分离绝缘膜区域表面到所定深度形成第2杂质型的埋入层阶段；在部分包含定义上述第1活性区域邻接的第2活性区域的元件分离绝缘膜下部区域和上述第2活性区域邻接的第3活性区域及其两侧的元件分离绝缘膜的下部区域形成第2杂质型的第1沟区域及第2杂质型的第2沟区域阶段；在部分包含上述第1活性区域及其两侧的元件分离绝缘膜区域的下部形成第1杂质型的第3沟区域，在上述第2活性区域的下部形成第1杂质型的第4沟区域阶段；在上述第1活性区域的上述第3沟表面附近及上述第2活性区域的上述第4沟表面附近形成用于调节阈值电压的第1杂质型的第1及第2掺杂区域，形成上述第1掺杂区域的浓度比上述第2掺杂区域的浓度低的阶段。
8.如权利要求7所述的半导体元件制造方法，其特征在于，上述第1杂质型是P型，第2杂质型是N型。
9.如权利要求8所述的半导体元件制造方法，其特征在于，上述第1掺杂区域的形成阶段包含N型杂质离子注入阶段和P型杂质二次离子注入阶段。
10.如权利要求9所述的半导体元件制造方法，其特征在于，上述N型杂质的离子注入阶段包含向露出的第1活性区域以磷(P)原子30～80Kev的能量和2×1011～5×1012ions/cm2浓度离子注入阶段。
11.如权利要求9所述的半导体元件的制造方法，其特征在于，上述P型杂质的离子注入阶段，包含向上述露出的第1活性区域将硼以70～120Kev的能量和5×1012～5×1013ions/cm2浓度1次离子注入阶段和向上述露出的第1活性区域将硼以10～30Kev的能量和1×1012～5×1012ions/cm2浓度离子注入阶段。
12.如权利要求7所述的半导体装置的制造方法，其特征在于，上述第2杂质型的埋入层形成阶段，包含露出上述1活性区域及其两侧的元件分离绝缘膜层的形成掩膜图形阶段；将磷(P)原子以1～2Mev的能量和1×1012～5×1013ions/cm2浓度离子注入阶段；除去上述掩膜图形阶段。
13.如权利要求12所述的半导体元件的制造方法，其特征在于，上述掩膜图形的厚度为3～5μm。
14.如权利要求7所述的半导体元件的制造方法，其特征在于，上述第1沟区域与第2沟区域同时形成。
15.如权利要求7所述的半导体元件的制造方法，其特征在于，上述第3沟及第4沟区域同时形成。
16.如权利要求8所述的半导体元件的制造方法，其特征在于，上述第1沟区域及第2沟区域的形成阶段，包含定义上述第3活性区域及上述第1、第2活性区域的元件分离绝缘膜的所定区域露出形成掩膜图形阶段；将磷(P)原子以700Kev～1.5Mev的能量和5×1012～5×1013ions/cm2浓度向衬底全表面离子注入阶段；除去上述掩膜图形阶段。
17.如权利要求16所述的半导体元件的制造方法，其特征在于，上述掩膜图形的厚度为2～4μm。
18.如权利要求8所述的半导体元件的制造方法，其特征在于，上述第3沟及第4沟的形成阶段，包含露出上述第1活性区域及上述第2活性区域形成掩膜图形阶段；将硼原子以500Kev～700Kev的能量和1×1013～5×1013ions/cm2浓度向衬底全表面离子注入阶段；除去上述掩膜图形阶段。
19.如权利要求18所述的半导体元件的制造方法，其特征在于，上述掩膜图形的厚度为2～4μm。
20.一种半导体元件的制造方法，其特征在于，包括：提供P型半导体衬底阶段；在上述半导体衬底的单位元件内形成定义第1、第2及第3三个部分活性区域的元件分离用绝缘膜阶段；从部分包含上述第1活性区域及其两侧的元件分离绝缘膜区域表面到所定深度形成N型埋入层阶段；向上述第1活性区域将N型杂质一次离子注入，在上述第1活性区域表面很近的下部形成第1掺杂区域阶段；在部分包含定义上述第1活性区域邻接的第2活性区域的元件分离绝缘膜下部区域和上述第2活性区域邻接的第3活性区域及其两侧的元件分离绝缘膜的下部区域形成N型第1沟区域及N型第2沟区域阶段；在部分包含上述第1活性区域及其两侧的元件分离绝缘膜区域的下部形成P型第3沟，在上述第2活性区域的下部形成P型第4沟区域阶段；在上述第1活性区域的第1掺杂区域及上述第2活性区域的上述第4沟表面附近，将用于调节阈值电压的P型杂质离子注入，形成第2及第3掺杂区域的阶段。
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