CN104979348A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN104979348A
CN104979348A CN201510155592.9A CN201510155592A CN104979348A CN 104979348 A CN104979348 A CN 104979348A CN 201510155592 A CN201510155592 A CN 201510155592A CN 104979348 A CN104979348 A CN 104979348A
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新田博明
赤沼英幸
桑沢和伸
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Seiko Epson Corp
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Abstract

本发明提供一种半导体装置及其制造方法。该半导体装置具备：P沟道DMOS晶体管，其具备N型栅电极；P沟道MOS晶体管，其具备P型栅电极；N沟道MOS晶体管，其具备N型栅电极。优选为，P沟道DMOS晶体管的N型栅电极具有：位于P沟道DMOS晶体管的源极侧的第一端部；和位于P沟道DMOS晶体管的漏极侧的第二端部，并且P沟道DMOS晶体管在第一端部处具有P型扩散层。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置及其制造方法。
背景技术
在DMOS(Double diffused Metal Oxide Semiconductor：双扩散金属氧化物半导体)晶体管例如为P沟道型的情况下，具有以双扩散的方式形成位于半导体基板的第一方向侧的面的低浓度的N型阱区和位于该N型阱区的第一方向侧的面的高浓度的P型源极区的结构。该DMOS晶体管具有能够处理大功率并且开关速度较快等特性。
P沟道DMOS晶体管的主要的载流子为空穴，与N沟道DMOS晶体管的主要的载流子亦即电子相比迁移率较低。因此，存在P沟道DMOS晶体管与N沟道DMOS晶体管相比通态电阻变大的情况。但是，通过使用作为P沟道DMOS晶体管的栅电极而含有N型的杂质的半导体，从而能够被形成为埋入沟道，由此降低通态电阻。在下述的专利文献1中公开了一种使用作为P沟道DMOS晶体管的栅电极而含有N型的杂质的半导体的装置。
考虑到将如上所述的具备N型栅电极的P沟道DMOS晶体管和与其一起使用的逻辑电路混装。在这种情况下，考虑到作为构成逻辑电路的MOS晶体管，使用具备N型栅电极的P沟道MOS(Metal Oxide Semiconductor：金属氧化物半导体)晶体管和具备N型栅电极的N沟道MOS晶体管。即，考虑到将DMOS晶体管以及MOS晶体管的栅电极全部设为N型栅电极。
然而，虽然具备N型栅电极的P沟道MOS晶体管被形成为埋入沟道而降低了通态电阻，但是另一方面，容易产生小于阈值电压时的漏电流。因此，存在具备N型栅电极的P沟道MOS晶体管作为构成逻辑电路的MOS晶体管而并不为优选的情况。
专利文献1：日本特开2008-235592号公报(图10)
发明内容
本发明为鉴于如上所述的技术课题而完成的发明。本发明的若干方式涉及降低DMOS晶体管的通态电阻并且降低MOS晶体管的漏电流的技术。
在本发明的若干方式中，半导体装置具备：P沟道DMOS晶体管，其具备N型栅电极；P沟道MOS晶体管，其具备P型栅电极；N沟道MOS晶体管，其具备N型栅电极。
根据该方式，由于将P沟道DMOS晶体管的栅电极设为N型，并将P沟道MOS晶体管的栅电极设为P型，因此能够降低DMOS晶体管的通态电阻并且降低MOS晶体管的漏电流。
在上述的方式中，优选为，P沟道DMOS晶体管的N型栅电极具有：位于P沟道DMOS晶体管的源极侧的第一端部；和位于P沟道DMOS晶体管的漏极侧的第二端部，并且P沟道DMOS晶体管的N型栅电极在第一端部处具有P型扩散层。
由此，能够形成在源极区中切实地注入了P型杂质的P沟道DMOS晶体管。
在上述的方式中，优选为，P型扩散层在N型栅电极的厚度方向上位于从栅极绝缘膜离开的位置处。
由此，能够将DMOS晶体管形成为埋入沟道，从而降低通态电阻。
在本发明的其他方式中，半导体装置的制造方法包括：工序(a)，在位于与处在半导体基板的第一方向侧的面的第一N型区的一部分以及第一P型区的一部分相接的位置处的绝缘膜的第一方向侧，形成N型栅电极；工序(b)，通过横跨N型栅电极的第一方向侧的面的一部分亦即第一区域与第一N型区的第一方向侧的面的一部分亦即第二区域而注入P型的杂质，从而在第一区域形成P型扩散层且在第二区域区形成源极区。
根据该方式，能够切实地向P沟道DMOS晶体管的源极区注入P型杂质。
在上述方式中，优选为，在工序(a)与工序(b)之间还具备如下的工序(c)，即，横跨第一区域的第一方向侧的面和第二区域的第一方向侧的面而形成抗蚀层，并向第三区域和第四区域注入N型的杂质，并去除抗蚀层，所述第三区域为N型栅电极的第一方向侧的面的一部分且为与第一区域不同的区域，所述第四区域为第一N型区的第一方向侧的面的一部分且为与第二区域不同的区域。
由此，能够对在向N型栅电极的第一方向侧的面注入N型的杂质时，N型的杂质被注入到源极区中的情况进行抑制。
在上述方式中，优选为，工序(b)还包括形成P沟道MOS晶体管的源极区以及漏极区的工序。
由此，能够同时形成P沟道DMOS晶体管的源极区与P沟道MOS晶体管的源极区和漏极区。
在上述方式中，优选为，工序(c)还包括形成N沟道MOS晶体管的源极区以及漏极区的工序。
由此，能够同时形成N型栅电极的N型扩散层和N沟道MOS晶体管的源极区以及漏极区。
附图说明
图1为表示实施方式所涉及的半导体装置的剖视图以及杂质的浓度分布的曲线图。
图2为表示实施方式所涉及的半导体装置的制造方法的剖视图。
图3为表示实施方式所涉及的半导体装置的制造方法的剖视图。
图4为表示实施方式所涉及的半导体装置的制造方法的剖视图。
图5为表示实施方式所涉及的半导体装置的制造方法的剖视图。
具体实施方式
以下，对本发明的实施方式进行详细说明。另外，以下所说明的实施方式并不对权利要求书中所记载的本发明的内容进行不当限定。此外，本实施方式所说明的全部结构并不一定都是作为本发明的解决方法所必须的。此外，对于相同的结构要素标注相同的参照符号并省略说明。
1.结构
图1(A)为表示本发明的实施方式所涉及的半导体装置的一个示例的剖视图。
图1(A)所示的半导体装置1包括P沟道DMOS晶体管Tr1、P沟道MOS晶体管Tr2和N沟道MOS晶体管Tr3。这些晶体管均位于P型的半导体基板10p的第一方向侧的面处。第一方向侧相当于各个附图中的上侧。半导体基板10p由含有P型杂质的单晶硅构成。
1-1.P沟道DMOS晶体管Tr1
如图1(A)所示，由于P沟道DMOS晶体管Tr1具有左右对称的结构，因此对于在右侧与左侧相对应的要素标注相同的符号，并省略重复的说明。N型阱11n、N型体区12n、P型偏置(offset)区13p、P型源极区21p、N型体接触区22n和P型漏极区23p位于半导体基板10p中的P沟道DMOS晶体管Tr1的位置处。
N型阱11n含有N型的杂质。N型阱11n位于与半导体基板10p的第一方向侧的面相接的位置处。N型体区12n与N型阱11n相比含有浓度较高的N型的杂质。N型体区12n在N型阱11n的内部位于与半导体基板10p的第一方向侧的面相接的位置处。P型偏置区13p含有P型的杂质。P型偏置区13p在N型阱11n的内部与半导体基板10p的第一方向侧的面相接且位于N型体区12n的左右两侧。
P型源极区21p含有P型的杂质，N型体接触区22n与N型体区12n相比含有浓度较高的N型的杂质。P型源极区21p以及N型体接触区22n在N型体区12n的内部位于与半导体基板10p的第一方向侧的面相接的位置处。P型漏极区23p与P型偏置区13p相比含有浓度较高的P型的杂质。P型漏极区23p在P型偏置区13p的内部位于与半导体基板10p的第一方向侧的面相接的位置处。
第一绝缘膜31、第二绝缘膜32、第三绝缘膜33和N型栅电极41n位于半导体基板10p的第一方向侧。
第三绝缘膜33沿着N型阱11n的外周而配置。第三绝缘膜33为，例如通过LOCOS(Local Oxidization of Silicon：硅的局部氧化)法而形成的绝缘膜。P沟道DMOS晶体管Tr1通过第三绝缘膜33与N型阱11n而与半导体基板10p的其他元件分离。
N型栅电极41n横跨N型体区12n的第一方向侧与P型偏置区13p的第一方向侧而配置。第一绝缘膜31与第二绝缘膜32位于N型栅电极41n与半导体基板10p之间。
第一绝缘膜31存在于N型栅电极41n与半导体基板10p之间的区域中的N型体区12n侧的位置处。第一绝缘膜31具有作为栅极绝缘膜的作用。
第二绝缘膜32存在于N型栅电极41n与半导体基板10p之间的区域中的P型偏置区13p侧的位置处。第二绝缘膜32通过具有与第一绝缘膜31相比较大的膜厚，从而具有缓和N型栅电极41n与P型漏极区23p之间的电场的作用。
N型栅电极41n由含有N型的杂质的多晶硅构成。N型栅电极41n具有位于源极侧的第一端部51和位于漏极侧的第二端部52。
P型扩散层44p位于N型栅电极41n的第一端部51处。P型扩散层44p含有P型的杂质。P型扩散层44p在N型栅电极41n的厚度方向上位于从第一绝缘膜31离开的位置处。N型栅电极41n的厚度方向与第一方向大致一致。此外，P型扩散层44p位于与N型栅电极41n的第一方向侧的面相接的位置处。
N型扩散层45n也位于N型栅电极41n的第一方向侧的面处。N型扩散层45n与N型栅电极41n的其他部分相比含有浓度较高的N型的杂质。N型扩散层45n位于从与P型扩散层44p相连接的位置起到N型栅电极41n的第二端部52为止的位置处。
图1(B)为表示沿着图1(A)中的A-B线的杂质的浓度分布的曲线图。在N型栅电极41n的第一端部51附近，在距第一方向侧的面较近的位置处，即，在N型栅电极41n的厚度方向上从第一绝缘膜31离开的位置处，含有浓度较高的P型的杂质。在距第一方向侧的面较远的位置处，即，距第一绝缘膜31较近的位置处，含有浓度较高的N型的杂质。因此，虽然N型栅电极41n在一部分处具有P型扩散层44p，但将被形成在N型体区12n中的沟道形成为埋入沟道，从而能够降低通态电阻。
1-2.P沟道MOS晶体管Tr2
再次参照图1(A)，N型阱14n、P型源极区24p和P型漏极区25p位于半导体基板10p中的P沟道MOS晶体管Tr2的位置处。
N型阱14n含有N型的杂质。N型阱14n位于与半导体基板10p的第一方向侧的面相接的位置处。
P型源极区24p以及P型漏极区25p含有P型的杂质。P型源极区24p以及P型漏极区25p在N型阱14n的内部与半导体基板10p的第一方向侧的面相接且以相互隔开间隔的方式而配置。
第四绝缘膜34、第五绝缘膜35和P型栅电极42p位于半导体基板10p的第一方向侧。第五绝缘膜35为，例如通过LOCOS法而形成的绝缘膜。P沟道MOS晶体管Tr2通过第三绝缘膜33、第五绝缘膜35和N型阱14n而与半导体基板10p的其他元件分离。
第四绝缘膜34位于与半导体基板10p的第一方向侧的面且与被夹在P型源极区24p与P型漏极区25p之间的区域相接的位置处。第四绝缘膜34具有作为栅极绝缘膜的作用。
P型栅电极42p位于与第四绝缘膜34的第一方向侧的面相接的位置处。P型栅电极42p由含有P型的杂质的多晶硅构成。P型扩散层46p位于P型栅电极42p的第一方向侧的面处。P型扩散层46p与P型栅电极42p的其他部分相比含有浓度较高的P型的杂质。P型栅电极42p能够抑制在N型阱14n中所形成的沟道被形成为埋入沟道的情况，从而降低小于阈值电压时的漏电流。
1-3.N沟道MOS晶体管Tr3
P型阱15p、N型源极区26n、N型漏极区27n位于半导体基板10p中的N沟道MOS晶体管Tr3的位置处。
P型阱15p含有P型的杂质。P型阱15p位于与半导体基板10p的第一方向侧的面相接的位置处。
N型源极区26n以及N型漏极区27n含有N型的杂质。N型源极区26n以及N型漏极区27n在P型阱15p的内部与半导体基板10p的第一方向侧的面相接且以相互隔开间隔的方式而设置。
第五绝缘膜35、第六绝缘膜36和N型栅电极43n位于半导体基板10p的第一方向侧。N沟道MOS晶体管Tr3通过第五绝缘膜35、P型阱15p而与半导体基板10p的其他元件分离。
第六绝缘膜36位于与半导体基板10p的第一方向侧的面且与被夹在N型源极区26n与N型漏极区27n之间的区域相接位置处的。第六绝缘膜36具有作为栅极绝缘膜的作用。
N型栅电极43n位于与第六绝缘膜36的第一方向侧的面相接的位置处。N型栅电极43n由含有N型的杂质的多晶硅构成。N型扩散层47n位于N型栅电极43n的第一方向侧的面处。N型扩散层47n与N型栅电极43n的其他部分相比含有浓度较高的N型的杂质。通过将P沟道MOS晶体管Tr2与N沟道MOS晶体管Tr3结合，从而构成了逻辑电路。
2.制造方法
图2～图5为表示本发明的实施方式所涉及的半导体装置的制造方法的剖视图。首先，如图2(A)所示，在P型的半导体基板10p的第一方向侧的面上形成N型阱11n。
接下来，如图2(B)所示，在半导体基板10p的第一方向侧的面的预定部位处，例如通过LOCOS法而形成第二绝缘膜32、第三绝缘膜33以及第五绝缘膜35。
接下来，如图3(C)所示，通过向半导体基板10p的第一方向侧的面注入N型的杂质，从而形成N型体区12n以及N型阱14n。此外，通过向半导体基板10p的第一方向侧的面注入P型的杂质，从而形成P型偏置区13p以及P型阱15p。N型体区12n相当于本发明中的第一N型区，P型偏置区13p相当于本发明中的第一P型区。
接下来，如图3(D)所示，在半导体基板10p的第一方向侧的面上形成成为栅极绝缘膜的较薄的绝缘膜37。并且，在绝缘膜37的第一方向侧的面上形成成为栅电极的多晶硅层48。
接下来，如图4(E)所示，向多晶硅层48中成为N型栅电极41n的部分以及成为N型栅电极43n的部分注入N型的杂质而形成N型区48n。另外，既可以向多晶硅层48中成为P型栅电极42p的部分注入P型的杂质，也可以不特别注入。
接下来，如图4(F)所示，对多晶硅层48的一部分以及绝缘膜37的一部分进行蚀刻而将其去除。由此，形成N型栅电极41n、P型栅电极42p、N型栅电极43n、第一绝缘膜31、第四绝缘膜34和第六绝缘膜36。
接下来，如图5(G)所示，为了在N型体区12n中形成N型体接触区22n，并在N型栅电极41n中形成N型扩散层45n，而向各自的位置注入N型的杂质。
此时，预先形成抗蚀层R1，以便不使N型的杂质进入成为P型源极区21p的部分。抗蚀层R1以不仅覆盖成为P型源极区21p的部分而且还覆盖位于N型栅电极41n的源极侧的第一端部51的方式，横跨N型体区12n的一部分与N型栅电极41n的一部分而形成。N型体接触区22n被形成在相当于本发明中的第四区域的位置处，N型扩散层45n被形成在相当于本发明中的第三区域的位置处。
此外，如图5(G)所示，优选为，在进行该工序的同时，形成N沟道MOS晶体管Tr3的N型源极区26n、N型漏极区27n和N型扩散层47n。然后，去除抗蚀层R1。
接下来，如图5(H)所示，为了在N型体区12n中形成P型源极区21p，并在P型偏置区13p中形成P型漏极区23p，而向各自的位置注入P型的杂质。
此时，预先形成的抗蚀层R2并未完全覆盖N型栅电极41n，而是预先使位于N型栅电极41n的源极侧的第一端部51露出。由此，横跨成为P型源极区21p的部分与位于N型栅电极41n的源极侧的第一端部51而注入P型的杂质。在位于N型栅电极41n的源极侧的第一端部51附近形成有P型扩散层44p。成为P型源极区21p的部分相当于本发明中的第二区域，位于N型栅电极41n的源极侧的第一端部51附近相当于本发明中的第一区域。
此外，如图5(H)所示，优选为，在进行该工序的同时，形成P沟道MOS晶体管Tr2的P型源极区24p、P型漏极区25p和P型扩散层46p。然后，去除抗蚀层R2。
通过以上的工序，能够制造出半导体装置1。
在以上所述的实施方式中，也可以替代N型阱11n而配置含有P型的杂质的P型阱。
符号说明
1…半导体装置；10p…半导体基板；11n…N型阱；12n…N型体区；13p…P型偏置区；14n…N型阱；15p…P型阱；21p…P型源极区；22n…N型体接触区；23p…P型漏极区；24p…P型源极区；25p…P型漏极区；26n…N型源极区；27n…N型漏极区；31…第一绝缘膜；32…第二绝缘膜；33…第三绝缘膜；34…第四绝缘膜；35…第五绝缘膜；36…第六绝缘膜；37…绝缘膜；41n…N型栅电极；42p…P型栅电极；43n…N型栅电极；44p…P型扩散层；45n…N型扩散层；46p…P型扩散层；47n…N型扩散层；48…多晶硅层；48n…N型区；51…第一端部；52…第二端部；R1、R2…抗蚀层；Tr1…P沟道DMOS晶体管；Tr2…P沟道MOS晶体管；Tr3…N沟道MOS晶体管。

Claims (7)

1.一种半导体装置，具备：
P沟道双扩散金属氧化物半导体晶体管，其具备N型栅电极；
P沟道金属氧化物半导体晶体管，其具备P型栅电极；
N沟道金属氧化物半导体晶体管，其具备N型栅电极。
2.如权利要求1所述的半导体装置，其中，
所述P沟道双扩散金属氧化物半导体晶体管的所述N型栅电极具有：位于所述P沟道双扩散金属氧化物半导体晶体管的源极侧的第一端部；和位于所述P沟道双扩散金属氧化物半导体晶体管的漏极侧的第二端部，并且所述P沟道双扩散金属氧化物半导体晶体管的所述N型栅电极在所述第一端部处具有P型扩散层。
3.如权利要求2所述的半导体装置，其中，
所述P型扩散层在所述N型栅电极的厚度方向上位于从栅极绝缘膜离开的位置处。
4.一种半导体装置的制造方法，包括：
工序(a)，在位于与处在半导体基板的第一方向侧的面的第一N型区的一部分以及第一P型区的一部分相接的位置处的绝缘膜的所述第一方向侧，形成N型栅电极；
工序(b)，通过横跨所述N型栅电极的所述第一方向侧的面的一部分亦即第一区域与所述第一N型区的所述第一方向侧的面的一部分亦即第二区域而注入P型的杂质，从而在所述第一区域形成P型扩散层且在所述第二区域形成源极区。
5.如权利要求4所述的半导体装置的制造方法，其中，
在工序(a)与工序(b)之间还具备如下的工序(c)，即，横跨所述第一区域的所述第一方向侧的面和所述第二区域的所述第一方向侧的面而形成抗蚀层，并向第三区域和第四区域注入N型的杂质，并去除抗蚀层，所述第三区域为所述N型栅电极的所述第一方向侧的面的一部分且为与所述第一区域不同的区域，所述第四区域为所述第一N型区的所述第一方向侧的面的一部分且为与所述第二区域不同的区域。
6.如权利要求4或权利要求5所述的半导体装置的制造方法，其中，
工序(b)还包括形成P沟道金属氧化物半导体晶体管的源极区以及漏极区的工序。
7.如权利要求5所述的半导体装置的制造方法，其中，
工序(c)还包括形成N沟道金属氧化物半导体晶体管的源极区以及漏极区的工序。
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