CN104900591A - 低成本半导体器件制造方法 - Google Patents

低成本半导体器件制造方法 Download PDF

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CN104900591A
CN104900591A CN201410647719.4A CN201410647719A CN104900591A CN 104900591 A CN104900591 A CN 104900591A CN 201410647719 A CN201410647719 A CN 201410647719A CN 104900591 A CN104900591 A CN 104900591A
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drain
district
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dosage
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CN104900591B (zh
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弗朗索瓦·赫伯特
方演燮
柳惟信
赵城敏
金胄浩
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Aisi Kaifang Semiconductor Co ltd
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MagnaChip Semiconductor Ltd
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Abstract

本发明提供了一种低成本半导体器件制造方法和使用该方法制造的半导体器件。该方法包括：在半导体衬底中形成多个本体区；在本体区中形成多个栅极绝缘层和多个栅电极；在衬底的整个表面中实施毯式离子注入以在不具有掩模的情况下在本体区中形成低浓度掺杂区(LDD区)；在栅电极的侧壁处形成间隔物；以及实施高浓度的离子注入以在LDD区周围形成高浓度的源极区和高浓度的漏极区。根据本实施例，器件具有良好的电特性，并且同时降低了制造成本。由于在形成高浓度的源极区和漏极区时实施倾斜和旋转共同注入，所以潜在地省去了LDD掩模步骤。

Description

低成本半导体器件制造方法
相关申请的交叉引用
本申请要求于2014年3月6日提交至韩国知识产权局的韩国专利申请第10-2014-0026362号的权益，其全部内容通过引用合并到本文中以用于所有目的。
技术领域
以下描述涉及一种低成本半导体器件制造方法。以下描述还涉及一种通过减少在半导体器件制造过程中使用的掩模工艺步骤而具有降低的制造成本的半导体器件和这样的半导体器件的制造方法。
背景技术
通常而言，各种半导体器件在一个衬底中的一次性制造工艺产生巨大的费用。产生这些费用是因为每次在制作各个器件时，在工艺流程中插入有数十个掩模。相应地，掩模步骤伴随有数十个光刻工艺和蚀刻工艺。这样的掩模工艺、光刻工艺和掩模工艺重复得越多，每个单位的制造成本增加得越多。为了生产成本显著较低的半导体器件或芯片，使掩模步骤的数目尽可能少是有帮助的。较详细地考虑了用于制造双极互补金属-氧化物-半导体(CMOS)-双扩散金属-氧化物-半导体(DMOS)(BCD)类型的工艺流程技术，其将许多不同的有源器件和无源器件集成在一个衬底上，用于模拟应用和功率管理应用。
BCD由双极功率器件、CMOS功率器件、DMOS功率器件、无源器件和互连器件的组合构成。在BCD技术中采用集成的器件结构的一个实施例是全隔离横向n沟道金属-氧化物-半导体场效应晶体管(MOSFET)(nLDMOS)。一种使用LDMOS器件、双极器件、CMOS器件、一种栅极氧化物、一种多晶硅栅极和三层金属层的BCD流式架构(flowarchitecture)(对于一种多晶硅栅极和三层金属而言，整体上称为1P3M流)，可能需要超过20个的掩模层。例如，这样的架构通常使用22至23个掩模层。由于使用了这么多掩模层和其他相关的必要工艺，因此所得到的晶片的成本高。
在BCD、BiCMOS和CMOS技术中，为了解决日益增加的制造成本的挑战，可以最小化掩模操作的数目。此处，BiCMOS是将双极结型晶体管和CMOS晶体管集成到单集成电路器件中的先进的半导体技术。如果将制造工艺分解成单独的模块，则最标准的技术使用单独并且专用的N沟道低掺杂漏极(NLDD)掩模和P沟道低掺杂漏极(PLDD)掩模以及注入操作以分别形成N沟道器件和P沟道器件的低掺杂漏极(LDD)延伸部。形成用于NMOS的LDD(低掺杂漏极)区需要NLDD掩模；形成用于PMOS的LDD区必然需要PLDD掩模。因此，如果能够减少用于形成NMOS晶体管和PMOS晶体管的LDD的这样的LDD掩模的数量，则制造成本可以降低。
此外，期望的是使nLDMOS的击穿电压(BVdSS)最大化，使导通状态下漏极-源极的电阻(Rdson)最小化，并且还使其制造成本最小化。期望构造具有这些方面的器件是因为这些方面提高了器件的性能和可靠性同时保持成本可控。然而，例如，在BCD器件(例如，用于DC-DC或DC-AC高电流转换器的功率器件)中，不存在满足刚才讨论的所有要求和目标的已知的BCD工艺技术。
发明内容
提供本发明内容以用简化的形式介绍在下面的具体实施方式中进一步描述的一系列概念。本发明内容并非旨在确定所要求保护的主题的关键特征和基本特征，也并非旨在用作在确定所要求保护的主题的范围时的辅助。
在一个一般性方面中，一种制造半导体器件的方法包括：在半导体衬底中制备第一区和第二区；在第一区中形成具有高浓度掺杂剂的第一本体区以形成高阈值电压器件；在第二区中形成具有低浓度掺杂剂的第二本体区以形成低阈值电压器件；在第一本体区和第二本体区之上形成栅电极；将第二导电类型的掺杂剂毯式(或无掩模，blanket)注入到第一本体区和第二本体区中以形成低掺杂漏极(LDD)区；形成紧邻栅电极的间隔物；以及源极-漏极注入第二导电类型的掺杂剂以形成在间隔物之下延伸的低掺杂延伸部和低电阻的源极/漏极区，其中，源极-漏极注入包括倾斜和旋转注入，并且其中，毯式注入和源极-漏极注入足以补偿足够的高阈值电压器件的第一本体区，以确保在源极/漏极区与沟道区之间的低电阻连接。
毯式注入可以具有1E11离子cm-2至5E13离子cm-2的低剂量。
源极-漏极注入还可以包括实施相对于半导体衬底的表面基本垂直的第一剂量的注入。
倾斜和旋转注入可以包括以相对于半导体衬底的表面的倾斜角度的低于第一剂量的第二剂量注入，以在间隔物之下形成低电阻连接。
第一剂量可以为5E14离子cm-2至1E16离子cm-2，并且第二剂量可以为1E12离子cm-2至1E14离子cm-2。
毯式注入在形成低掺杂漏极区时可以略去所有的掩模操作。
在另一个一般性方面中，一种半导体结构包括：在半导体衬底中的第一区和第二区；位于第一区中的横向双扩散金属-氧化物-硅(LDMOS)器件；形成在第一区中的具有第二导电性的第一埋层；形成在第一埋层上的具有第一导电性的第二埋层；形成在第二埋层上的具有第二导电性的漂移区；形成为与漂移区相邻的高浓度的第一本体区；形成在漂移区和第一本体区之上的第一栅电极；形成为紧邻栅电极的间隔物；形成为在间隔物之下延伸的低掺杂延伸部和低电阻的源极区；形成在第一本体区中的具有第一导电性的本体接触区；与源极区间隔开的低电阻的漏极区；形成在源极区与漏极区之间的第一本体区中的沟道区；以及在源极区、漏极区与沟道区之间的低电阻连接。
该结构还可以包括在第二区中的低阈值电压器件和在第二区中的低浓度的第二本体区。
在相同的掩模操作期间，漂移区与第二埋层可以以自对准的方式形成。
低电阻连接可以通过毯式注入操作和源极/漏极的倾斜和旋转注入操作形成。
在另一个一般性方面中，一种制造半导体器件的方法包括：在半导体衬底中制备第一区和第二区；在第一区中形成具有高浓度掺杂剂的第一本体区以形成高阈值电压器件；在第二区中形成具有低浓度掺杂剂的第二本体区以形成低阈值电压器件；在第一本体区和第二本体区之上形成栅电极；将第二导电类型的掺杂剂毯式注入到第一本体区和第二本体区中以形成低掺杂漏极(LDD)区；紧邻栅电极形成间隔物；以及源极-漏极注入第二导电类型的掺杂剂以形成在间隔物之下延伸的低掺杂延伸部和低电阻的源极/漏极区。
源极-漏极注入可以包括倾斜和旋转注入。
倾斜和旋转注入可以包括以相对于半导体衬底的表面的倾斜角度的低于第一剂量的第二剂量注入，以在间隔物之下形成低电阻连接。
第一剂量可以为5E14离子cm-2至1E16离子cm-2，并且第二剂量可以为1E12离子cm-2至1E14离子cm-2。
毯式注入和源极-漏极注入可以足以补偿足够的高阈值电压器件的第一本体区，以确保在源极/漏极区与沟道区之间的低电阻连接。
毯式注入可以具有1E11离子cm-2至5E13离子cm-2的低剂量。
源极-漏极注入还可以包括实施相对于半导体衬底的表面基本垂直的第一剂量的注入。
毯式注入在形成低掺杂漏极区时可以略去所有的掩模操作。
根据本实施例，省略NLDD掩模和PLDD掩模，并且实施N型掺杂剂毯式离子注入。因此，使所需要的掩模数目最小化。由于在实施例中使用的替代方法，所以通过减少掩模的数量，在实现期望的电特性的同时，也降低了制造成本。
也就是说，根据本实施例，在制造MOSFET结构(例如，与具有高性能特性的CMOS模块一起制作的LDMOS)的过程中，提供了一种将这样的器件集成在一起同时维持低成本的BCD技术。
其他特征和方面从以下的具体实施方式、附图和权利要求中将是明显的。
附图说明
图1描绘了根据一个实施例的半导体器件的图。
图2至图6描绘了示出根据一个实施例的MOSFET器件的制造方法的图。
图7至图9描绘了示出在根据一个实施例的MOSFET器件的制造方法中的LDMOS器件的制造方法的图。
图10A描绘了示出N沟道可扩展DMOS器件的图。图10B描绘了示出P沟道可扩展DMOS器件的图。图10A与图10B中的器件使用低成本制造方法制造，该方法包括根据一个实施例的通过2步法来制造高浓度的源极/漏极区、毯式LDD离子注入、倾斜/旋转和其他适合的操作。
图11A描绘了隔离低电压(LV)NMOS器件的图，图11B描绘了使用根据一个实施例的低成本制造方法制造的低电压PMOS器件的图。
图12描绘了使用根据一个实施例的低成本制造方法制造的纵向肖特基二极管器件的图。
图13描绘了使用根据低成本制造方法制造的纵向NPN元件(a)和横向PNP元件(b)的图。
具体实施方式
在下文中，在一个衬底中通过BCD技术以低成本制造的各种器件中，使用CMOS器件、BiCMOS(双极-CMOS)器件、CDMOS(CMOS-DMOS)器件和BCD(双极-CMOS-DMOS)器件作为这样的器件的实施例。因此，在使用这样的BCD技术制造的这样的器件中的是包括CMOS的结构。例如，在本说明书中提到的BCD技低电压术包括这样的实施例：例如，具有高性能/电压特性的LDMOS器件、用于模拟功能和逻辑功能的CMOS、模拟可扩展DMOS(包括N沟道和P沟道)、双极晶体管、二极管和其他无源器件。
因而，在本说明书中考虑的CMOS器件分为NMOS、PMOS、隔离CMOS和其他适合的组。此处，隔离指减少晶体管之间的电相互作用的方式。LDMOS器件分为nLDMOS和pLDMOS。nLDMOS指n沟道横向扩散金属-氧化物-半导体场效应晶体管(在下文中，称为nLDMOS)。pLDMOS是p沟道横向扩散金属-氧化物-半导体场效应晶体管。这样的晶体管经由在较高度掺杂的硅衬底上的外延硅层制造。
nLDMOS和pLDMOS是用于成功地实现具有期望性能的功率器件(如DC-DC大电流转换器和稳压器)的器件。根据本文中提供的实施例，使nLDMOS的击穿电压(BVdss)最大化；使导通状态下的漏极源极电阻(Rdson)最小化。此外，使制造成本大大降低。由此，该实施例提供了具有理想的性能属性而且相对便宜的器件。
就本实施例中的双极晶体管、二极管和其他无源器件而言，所包括的二极管的实施例为纵向NPN、横向PNP和/或肖特基二极管。双极晶体管是它们的操作依赖于两种类型的半导体的接触的晶体管。在实施例中，这样的器件通过低成本BCD工艺制造在一个半导体衬底中。因而，根据本实施例，首先，提出一种其中NMOS器件、PMOS器件和高阈值电压的NMOS器件一起形成的MOSFET器件作为实施例。另外，还存在与低成本MOSFET的形成同时形成的模拟可扩展DMOS(N沟道和P沟道)、双极晶体管、二极管和其他无源器件，并且下面对其进一步讨论。
在对于CMOS设计的现有技术中，可能存在使用倾斜离子注入法形成LDD的实例，在这样的实例下在离子注入的工艺中施加低的剂量和通常高的能量以形成源极/漏极。在这样的技术中，使离子束倾斜以引入具有期望的布置和浓度的掺杂剂。在形成源极和漏极的掩模步骤中，如果通过附加的离子注入来形成LDD，则可以减少使用的掩模的数目。然而，用于形成LDD的离子注入仅对于CMOS器件最优化。因而，存在在晶片的不同区域中，NLDD区潜在地不完全形成或根本没有形成的问题。因此，在具有高阈值电压的器件与具有低阈值电压的器件一起形成的实施例中，器件的性能潜在地降低。出现这种情况是因为在高阈值器件的源极区与沟道区之间的电阻增加，因为NLDD掺杂浓度被高阈值器件的本体区的高掺杂浓度补偿和/或降低。
在形成源极和漏极的掩模步骤中，在去除了用于形成NLDD和PLDD的掩模的情况下，制造成本由此降低。然而，去除掩模导致LDMOS功率器件的性能劣化的问题。
此外，在BCD工艺中，用于形成LDD的离子注入仅对于CMOS器件结构最优化。因此，在本体区中位于栅极之下的高浓度的N型源极与有源沟道区之间的连接因掺杂补偿而变弱。因此，这导致关于晶体管的Rdson增加的问题。存在这个问题是因为在间隔物之下，不足的N型LDD掺杂由相对高的沟道掺杂(也称为本体掺杂)补偿，导致在间隔区之下的高的电阻，这增加了器件的Rdson。
在图1的实施例中，存在具有第一阈值电压Vth的第一MOSFET 40、具有第二Vt的第二MOSFET 50和具有第三Vt的第三MOSFET 60，其中，MOSFET 40、50、60通过根据一个实施例的低成本制造方法而形成。第一MOSFET 40是高阈值NMOS，第二MOSFET 50是标准NMOS，并且第三MOSFET 60是标准PMOS。
此处，例如，第一Vth符合0.8V≤Vth≤1.2V。例如，第二Vt和第三Vt可以分别具有0.6V至0.8V和-0.6V至-0.8V的范围作为它们的范围。此处，Vth的和Vt两者代表阈值电压，但Vth表示用于实施例的不同部分的不同的阈值电压。因此，在图1的实施例中，第一MOSFET 40被确定为具有高于第二MOSFET 50或第三MOSFET 60的Vth的器件。为了在这样的实施例中具有这样的高阈值电压，在栅电极之下的沟道区中形成具有高浓度的P型掺杂的本体扩散区P本体。
因此，应将图1理解为这样的一种结构：其中设置有CMOS器件和具有高阈值电压的至少一个N沟道器件或P沟道器件，或者其中CMOS器件和高电压器件设置在一起。与CMOS器件相比，高电压器件具有更高的阈值电压。相反，在另一实施例中，设置有一种具有低于NMOS器件50的阈值电压的阈值电压的器件(一种低Vt的器件)，而不是具有高阈值电压的器件。对于该实施例，图1应以设置有具有彼此不同的阈值电压的NMOS器件的方式来考虑。在各个MOSFET器件的区域中，为了符合器件的操作电压或阈值电压，形成多个本体区。使用多个本体区表示实施例具有至少两个本体区，但是也适于具有更多个本体区的实施例。在图1的实施例中，设置有第一本体区123、第二本体区124、第三本体区122。多个本体区的深度潜在地彼此不同。与高电压器件相关联的电压越高，本体区的深度潜在地越深。在图1中，虽然以图示的方式示出各个本体区被定位成彼此接触，但是对于单独的NMOS、PMOS、高电压器件而言，在本体区之间可任选地形成导电类型与本体区的导电类型相反的阱区(在图1中未示出)，以有助于确保适合的电特性。例如，虽然未示出，但是在实施例中，在使用相同的导电类型的第一本体区123与第二本体区124之间，可任选地加入具有不同导电类型的阱区。通过加入这样的区域，使得器件能够在各个不同的操作电压下操作。
可以形成深沟槽隔离结构(DTI)(未示出)或通过使用扩散阱形成的结隔离结构，它们的深度比本体区的深度更深。此外，浅沟槽隔离(STI)或硅的局部氧化(LOCOS)可任选地提供作为包围深沟槽隔离结构(DTI)(未示出)的场隔离。STI的深度比阱区(未示出)的深度浅。
此外，为了对于本体区具有高阈值电压，与在表面上具有低阈值电压的器件相比，形成在栅电极之下的本体区的浓度被设计得更高。因而，在高Vth NMOS器件40的情况下，与用于低Vt器件50的第二本体区124相比，第一本体区123具有更高的浓度。在一个实施例中，较高的阈值电压器件40包括具有专用本体区123的LDMOS，与CMOS器件50的本体区124相比，专用本体区123具有更高的掺杂浓度。通过包括这样的较高的掺杂浓度，本实施例提供了对于本体区的高阈值电压。
在本体区122、123、124上，布置有栅极绝缘层174A、174B、174C和栅电极170A、170B、170C。在栅电极170A、170B、170C的两侧处包括有间隔物172A、172B、172C和源极/漏极区122C、123C、124C。
此外，在间隔物172之下，布置有LDD区123B、124B、122B，其中，LDD区123B、124B、122B是低掺杂浓度的区域。在其他的方法中，为了形成LDD区，在N沟道器件之上使用NM(N负)LDD掩模并且在P沟道器件之上使用PM(P负)LDD掩模。根据本实施例，在不具有这些NM掩模和PM掩模的情况下通过毯式离子注入来形成LDD区。从而提供了一种低成本半导体器件制造方法。该方法基于N型掺杂剂的毯式离子注入，之后形成包围栅极170的外围的间隔物172。实施例的毯式注入足以补偿足够的高浓度的高Vth器件的第一本体区123，以确保源极/漏极区123C与本体区123顶部的沟道区之间的低电阻连接。与沟道掺杂无关，根据本公开内容的低成本半导体器件的制造方法通过毯式离子注入形成本体扩散区与源极区之间的强的连接，以确保源极区与沟道区之间低的寄生电阻。在这样的实施例中，毯式离子注入参数选择为使得P沟道源极区和P沟道漏极区不受毯式注入的影响。因此，nLDMOS、隔离CMOS、nDMOS、pDMOS、纵向NPN、横向PNP、肖特基二极管和其他适合的部件采用这样的毯式LDD离子注入制造。以下将进一步解释这样的部件的结构。
图2至图6描绘了示出用于根据一个实施例的MOSFET半导体器件的制造方法的图。图2至图6示出了一种低成本半导体器件制造方法，该方法包括：在半导体衬底中形成多个本体区；在本体区中形成栅极绝缘层和栅电极；在衬底的整个表面中实施毯式离子注入以在不具有掩模的情况下紧邻栅电极形成低掺杂浓度的区域(LDD区)；在栅电极的侧壁处形成间隔物；以及实施高浓度离子注入以在LDD区与栅极区周围形成高浓度的源极区和高浓度的漏极区。例如，这样的方法包括毯式N-技术(也称为N负技术或NM技术)，其在不使用附加的掩模层的情况下在高阈值电压器件的本体区中形成强的源极区以提供沟道区耦合。通过避免附加的掩模层，使成本最小化。
图2至图6示出了同时制造三个MOSFET器件的实施例。然而，在其他实施例中，在一个半导体衬底中，同时制造多个MOSFET器件，或者同时制造MOSFET器件和肖特基二极管，或者同时制造MOSFET器件和双极结型晶体管(BJT)。作为另一替代方案，同时制造MOSFET器件和无源器件。在该实施例中，MOSFET器件包括如nLDMOS、pLDMOS、隔离CMOS、延伸漏极NMOS(nEDMOS)、延伸漏极PMOS(pEDMOS)等的器件。在实施例中，BJT器件包括如纵向NPN或横向PNP的器件。此外，二极管可任选地包括肖特基二极管。在该实施例中，上述器件被同时制造并彼此结合。在该实施例中，在这些器件的组合中，深入讨论了三个MOSFET器件，但关于三个MOSFET器件的组合提出的意见也适用于上述其他的器件组，以及未讨论的其他适合的组合。
现在参照图2的实施例，提供具有低的掺杂剂浓度的第二导电类型的P型掺杂剂的半导体衬底10。
再次参照图2的实施例，为了在半导体衬底10中形成MOSFET器件，在图2的实施例中形成用于具有高阈值电压和高压操作电压的第一MOSFET器件40的第二导电类型123的第一本体区、用于具有低阈值电压的第二MOSFET器件50的第二导电类型(P阱)124的第二本体区、以及用于具有低阈值电压的第三MOSFET器件60的第一导电类型(N阱)122的第三本体区。此处，为了使第一MOSFET器件40具有高阈值电压(即，高Vth)，将在衬底的表面上的第一本体区123的浓度选择为比第二本体区124的浓度高。例如，为了具有0.8V的高阈值电压，在沟道区中形成具有高浓度的P型本体扩散区P本体。
反之，在本实施例中，在第一本体区123中，形成具有低阈值电压(即0.6V或更低的低Vt)的低电压MOSFET器件，而不是高电压MOSFET。
第一本体区(N阱)123由此变为具有高阈值电压的本体区；并且第二体区(P阱)124变为NMOS器件50的本体区。在各种实施例中，当形成第一本体区123、第二本体区124和第三本体区122时，对于所讨论待发生的掺杂剂扩散，在高温(例如，1000℃或更高的温度)下进行驶入式(drive-in)退火。不对N阱和P阱毯式注入。在实施例中，形成LOCOS、STI、DTI或作为这些其他隔离层的组合的隔离层160用于器件之间的隔离。然后将栅极绝缘层174A、174B、174C沉积在半导体衬底上，并且沉积用于栅电极的导电层(如多晶硅)。例如，使用用于栅电极的掩模来分别形成栅电极170A、170B、170C。
现在参照图3，通过使用第一导电类型的掺杂剂沿相对于半导体衬底的整个表面的垂直方向来进行实施毯式离子注入。在注入过程期间，在一个实施例中，实施倾斜或旋转以促进注入。通常以不同的旋转动作重复多次毯式注入，例如四旋转。作为该工艺的一部分，在栅极170A、170B、170C的侧面处形成第一导电类型的低掺杂漏极(LDD)区123B、124B、122B。
在实施例中，用于形成LDD区(即，第一半导体区)的毯式离子注入的能量为10KeV至60KeV；可以注入设定为1E11cm-2至5E13cm-2的剂量的N型掺杂剂磷(Ph)。申请人指出，提及数字如1E11指的是数量1×1011。这被称为科学记数法。这样的数量是注入在物理区域上的离子、原子、分子或其他适合的粒子的计数。申请人指出，潜在优选的是剂量为1E11cm-2至5E12cm-2。在本实施例中，总的LDD掺杂剂浓度变为1E18原子/cm3或更少。
另外参照图4的实施例，在栅电极170A、170B、170C的侧壁处形成侧壁间隔物172A、172B、172C。形成侧壁间隔物后，使用用于N沟道掩模的N+和用于P沟道掩模的P+进行具有高掺杂浓度的源极/漏极注入。高掺杂区123C、124C、122C与低掺杂区LDD区123B、124B、122B相邻。这些源极/漏极注入包括5E15cm-2至1E16cm-2的高剂量离子注入以形成低电阻的源极/漏极接触。例如，这些低电阻的源极/漏极接触通常可以包括使用砷的用于N沟道的N+和使用浅硼(shallow Boron)或二氟化硼(BF2)的用于P沟道的P+。这些源极/漏极注入还使用倾斜和旋转离子注入技术以形成在间隔物172A、172B之下延伸的低掺杂延伸部和LDD区123B、124B。为了在栅极结构之下在晶片的表面上沿任何方向延伸的注入，倾斜注入还可以包括一些旋转。由于这些倾斜和旋转的共同注入与S/D注入的使用，所以在间隔物之下存在足够的N型活性掺杂剂。因此，在图4的实施例中，在间隔物172A、172B之下呈现非常低的电阻。
源极/漏极注入包括两步注入。在第一步中，在施加光致抗蚀剂掩模之后，通过高剂量和非倾斜的方法来实施第一离子注入。非倾斜法指第二导电类型的掺杂剂相对于半导体衬底的表面基本垂直地注入。首先使用非倾斜法注入的掺杂剂是砷；并且剂量为5E14cm-2至1E16cm-2，高于LDD离子注入的剂量。通过使用高浓度剂量的方式，形成高浓度的源极/漏极区如第二半导体区。
在第二步中，实施使用剂量低于第一步的剂量的第二离子注入。此外，第二离子注入使用以相对于半导体衬底的表面为预定的倾斜角度的倾斜和旋转方法。在N沟道区中，使用与之前在第一离子注入中注入的掺杂剂不同的磷掺杂剂为第二倾斜注入的掺杂剂。在一个实施例中，使用与在LDD毯式离子注入中使用的掺杂剂相同的掺杂剂。用于这样的离子注入的能量为10KeV至80KeV。在各种实施例中，该剂量等于或大于毯式离子注入中的剂量，并且该剂量是小于第一剂量的中等量。由此，该剂量为1E12cm-2至1E14cm-2。在一个实施例中，倾斜角度预定为7度至15度的角度。倾斜离子注入的原因是为了在第一半导体区(即在间隔物172之下通过毯式LDD离子注入形成的LDD区)中使用更多的相同的导电类型的掺杂剂来补充之前的掺杂。因为使用了与在LDD毯式离子注入中使用的掺杂剂相同的掺杂剂，所以可以进行该补充。
然后，如图5所示，施加光致抗蚀剂掩模以覆盖N沟道器件40、50并且露出P沟道器件60。如关于之前的低电压NMOS器件制造方法的实施例所讨论的，实施两步离子注入法。在第一步中，第一离子注入是非倾斜法并且使用掺杂剂BF2或B11，其中B11是适合于这些施加的特定的硼同位素。剂量为5E14cm-2至1E16cm-2。
在第二步中，通过不仅使用四旋转(即，四个旋转的组合)，而且使用基于半导体衬底的表面的倾斜角度离子注入法来实施第二离子注入。如以上所讨论的，使用硼掺杂剂。在这样的实施例中，用于离子注入的能量为10KeV至80KeV，剂量为1E12cm-2至1E14cm-2，并且倾斜角度为相对于半导体衬底的表面倾斜7度至15度。从而形成第二导电类型的高浓度的源极/漏极区122C。这些源极/漏极注入还包括形成在间隔物172C之下延伸的低掺杂延伸部和LDD区122B的倾斜和旋转离子注入。由于这些倾斜和旋转的共同注入与S/D注入的存在，所以在间隔物172C之下存在足够的P型活性掺杂剂。因此，在间隔物172C之下呈现非常低的电阻。
然后，通过去除掩模用于掺杂剂的扩散和活化，通过热退火制作出如图6的实施例中所示的这样的器件。在图6的实施例中，在高浓度的源极/漏极区、本体接触区和栅电极上，附加形成硅化物层。进行一些操作以形成高电压器件的N+源极与沟道区之间的低电阻连接，该操作包括：略去所有的LDD掩模操作、增加毯式N-LDD注入的步骤以及增加对N+源极/漏极和P+源极/漏极的倾斜和旋转的深的和较低剂量的LDD注入的步骤。
虽然在图2至图6中实施例示出了一种高Vth NMOS器件与NMOS和PMOS器件一起同时形成的制造工艺，但是一些实施例的制造工艺包括形成LDMOS器件。因此，在图7至图9中对与CMOS器件同时形成的nLDMOS器件的制造工艺进行说明。如前面图2至图6中提到的，这样的LDMOS器件通过低成本工艺形成，并且使用毯式LDD离子注入和使用倾斜/旋转的源极/漏极离子注入以提高这样的LDMOS器件的性能同时仍控制成本。
首先参照图7，如以上所讨论的，在P型半导体衬底200中形成第一导电类型的埋层210。在P型半导体衬底200中布置P型外延层212。然后形成第一导电类型的阱区N阱221、222和第二导电类型的阱区P阱223至226。不对N阱和P阱进行毯式注入。如之前关于图2至图6所讨论的，N阱和P阱是在形成上述的CMOS器件时一起形成的结构。然后在第一导电类型的埋层210上形成第二导电类型的埋层P埋层(PBL)250。然后在第二导电类型的埋层250上形成第一导电类型的漂移区(n-DRIFT)240。在相同的掩模操作期间，漂移区240和第二埋层250以自对准的方式形成。第二埋层250与漂移区240自对准。在漂移区240的上部上形成栅极绝缘层274和栅电极270D。由于第二导电类型的埋层250而在本实施例的上/下部处形成PN结区。
形成待与第二导电类型的埋层250连接的第二导电类型的本体区P本体223A。LDMOS针对沟道使用掺杂高于NMOS的P阱的P本体区223A。P本体223A的注入能量为10KeV至100KeV，并且剂量为1E12cm-2至1E15cm-2。
如以上所设置的P阱223的作用是连接P本体223A和PBL 250，以将实施例的这些部分彼此连接。P本体223A、P阱223和PBL 250全部同样彼此物理连接。
第二导电类型的本体区223A的掺杂浓度高于第二导电类型的阱区223的掺杂浓度。第二导电类型的埋层(PBL)250的作用是隔离nLDMOS的阱区240并降低在器件操作期间产生的寄生BJT的特性(如纵向或横向寄生操作特性)。这样的结构被称为全隔离系统出口(FISO)结构。为了防止这样的寄生BJT操作，在不影响击穿电压的情况下最大化第二导电类型的埋层(PBL)250的浓度。
然后，在图8中，通过与针对CMOS器件制造工艺所描述的相应方法相同的毯式离子注入法，在半导体层上形成第一导电类型的LDD区221B，以与栅电极270D交叠。因而，关于LDD离子注入的情况与上述MOSFET器件的制造工艺相同。如关于CMOS器件所说明的，DMOS器件通过毯式离子注入同时实现。在栅极270D的侧壁处进一步形成间隔物272。
在示出形成间隔物272的情况的图9的实施例中，将第一导电类型的高浓度的掺杂剂离子注入到半导体层中，从而形成高浓度的源极区276和高浓度的漏极区278。关于离子注入的情况与上述MOSFET器件的制造工艺相同，为使用与用于N沟道漏极和源极的N+掩模、用于P沟道源极的P+掩模以及nLDMOS的漏极与本体接触相同的掩模序列。即，使用诸如倾斜和/或旋转的离子注入法。由此，在通过毯式离子注入法形成的LDD区中待掺杂更多的N型掺杂剂。然后，将第二导电类型的高浓度的掺杂剂离子注入到半导体层中，从而在nLDMOS器件中形成高浓度的本体接触区280。将高浓度的本体接触区280、高浓度的源极区276和高浓度的漏区278设计成具有高于P本体区223A的掺杂浓度的掺杂浓度，以减小寄生电阻。
如上所述，在实施例中提出的低成本工艺不仅用于制造CMOS器件和nLDMOS/pLDMOS器件，而且还扩展为通用的BCD器件制造工艺。BCD器件不仅包括上述nLDMOS，而且潜在地包括隔离CMOS、nEDMOS、pEDMOS、纵向NPN、横向PNP、BJT、肖特基二极管。因而，在上述第一MOSFET、第二MOSFET和第三MOSFET中，其之一用作隔离CMOS、nEDMOS、pEDMOS、纵向NPN、横向PNP、BJT和肖特基二极管元件的替代。以下附图是描绘上述器件的图。
图10A示出了一种N沟道可扩展DMOS器件，并且图10B示出了一种使用根据实施例的低成本制造方法制造的P型沟道可扩展DMOS器件，其包括通过2步法(包括毯式LDD离子注入和倾斜/旋转以及其他步骤)制造的高浓度的源极/漏极区。图中的箭头表示临界间距。通过控制间距值来适当地改变半导体器件的额定电压。
图11A示出了一种隔离低电压NMOS器件，图11B示出了一种使用根据实施例的低成本制造方法制造的低电压PMOS器件，其包括通过2步法(包括毯式LDD离子注入和倾斜/旋转以及其他步骤)制造的高浓度的源极/漏极区。如上所述，图中的箭头表示临界间距。通过控制间距值来适当地改变半导体器件的额定电压。
图12示出了一种使用根据实施例的低成本制造方法制造的纵向肖特基二极管器件，其包括通过2步法(包括所讨论的毯式LDD离子注入和倾斜/旋转以及其他步骤)制造的高浓度的源极/漏极区。在图12的实施例中，在与阳极电极接触的硅化物肖特基接触区379周围形成高浓度的P型掺杂保护环382、384。N阱区320在硅化物肖特基接触区379之下形成阴极区。此外，高浓度的N型掺杂区383在N阱区320上形成阴电极。在低浓度的N阱区320之下形成高浓度的N型埋掺杂层(NBL)310，从而防止N阱的电阻降低。在N阱320的两侧处，形成隔离环323、324用于提供与其他器件的分隔，其他器件包括高浓度的P型掺杂区391、393、P本体区323A、324A和P阱区323、324。在肖特基二极管的形成中同样实施毯式LDD离子注入。在半导体衬底的硅化物肖特基接触区379的正之下的N阱区327中形成毯式LDD。为了形成肖特基接触，在低剂量的掺杂下实施毯式LDD离子注入使得掺杂剂的浓度变为1E18原子/cm3或更少。在本实施例中，剂量与上述关于其他实施例的情况相同。
图13表示利用毯式LDD离子注入和倾斜/旋转等2步法制造的、用于形成高浓度源极/漏极区的、利用低成本制造方法制造的纵向NPN元件(a)和横向PNP元件(b)。首先，对于纵向NPN元件的结构(图13a)，高浓度的N型掺杂区282在栅电极之间起发射极的作用。P本体225和高浓度P型掺杂区281起基区的作用并包围发射极区。并且N阱220、NBL210、高浓度N型掺杂区293起集电极的作用。并且，横向PNP结构(图13b)中，P本体区332同时起发射极和集电极的作用。P本体之间存在N阱322、323，N阱起基区作用。并且栅电极起多个场板的作用。
除非另有说明，否则第一层在第二层或衬底“上”的表述应被理解为包括两种情况：第一层直接接触第二层或衬底，和在第一层与第二层或衬底之间设置有一个或更多个其他层。
空间相关的表述如“在......之下”、“在……下”、“下部”、“在……之上”和“上部”等可以用来方便地地描述一个器件或一个元件与其他器件的关系或元件之间的关系。空间相关的表述应被理解为包括附图中描述的方向，以及器件在使用或操作时的其他方向。此外，器件可以面向其他方向，因此，对空间相关的表述的理解基于方位。
本文中所使用的表述如“第一导电类型”和“第二导电类型”可以指彼此相反的导电类型如N型或P型，并且本文中所解释和说明的实施例包括其互补实施例。
本文所描述的装置和单元可以通过使用硬件部件来实现。硬件部件可包括，例如控制器、传感器、处理器、生成器、驱动器和其他等效的电子部件。硬件部件可以利用一个或更多个例如通用或专用计算机实现，例如，处理器、控制器和算术逻辑单元、数字信号处理器、微型计算机、现场可编程阵列、可编程逻辑单元、微处理器或以限定方式能够响应和执行指令的任何其他器件。硬件部件可以运行操作系统(OS)和一个或更多个在OS上运行的软件应用程序。硬件部件也可以访问、存储、操作、处理和创建响应于执行软件的数据。为了简化目的，处理器件的描述被用作单数；然而，本领域的技术人员将理解为处理器件可以包括多个处理元件和多种类型的处理元件。例如，硬件部件可以包括多个处理器或处理器和控制器。此外，不同的处理配置，例如并行处理器，是可能的。
上述方法可以被编写为计算机程序、代码段、指令或它们的某种组合，用于单独或共同地指示或配置处理器件以如理想的操作。软件和数据可以永久或暂时地被包括在任何类型的机器、部件、物理或虚拟设备、计算机存储介质或能够提供指令或数据到或者由处理器件理解的器件中。软件还可以分布在网络耦合的计算机系统上，使得软件以分布式方式被存储和执行。具体地，软件和数据可以由一个或更多个非暂态计算机可读记录介质来存储。介质还可以包括单独地或与软件程序指令、数据文件、数据结构等的组合。非暂态计算机可读记录介质可以包括能够存储由计算机系统或处理器件读取的数据的任意数据可存储器件。非暂态计算机可读记录介质的实施例包括只读存储器(ROM)、随机存取存储器(RAM)、光盘只读存储器(CD-ROM)、磁带、USB、软盘、硬盘、光记录媒体(如CD-ROM或DVD)和PC接口(如PCI、PCI-Express、无线网络等)。此外，用于实现本文所公开的实施例的功能性程序、代码和代码段可以由本领域的技术程序员根据本文所提供的流程图、图中的方框图和相应的说明进行解释。
虽然本公开内容包括具体的实施例，但是对本领域的技术人员明显的是在不偏离本权利要求和其等同物的精神和范围的情况下，可以对这些实施例做出各种形式上和细节上的改变。本文中描述的实施例被认为只在描述意义上，并非为了限制的目的。在每一个实施例中的特征和方面的描述被认为适用于其他实施例中的相似特征和方面。在按照不同的顺序执行描述的技术的情况下，和/或在描述的系统、架构、器件或电路中的部件按照不同的方式组合和/或被其他的部件及其等同物替代或补充的情况下，可以获得合适的结果。因此，本公开的范围不受详细的描述限定，而是受权利要求和其等同物限定，并且在本权利要求和其等同物的范围内的所有变化被解释为包含在本公开内容内。

Claims (18)

1.一种制造半导体器件的方法，所述方法包括：
在半导体衬底中制备第一区和第二区；
在所述第一区中形成具有高浓度掺杂剂的第一本体区以形成高阈值电压器件；
在所述第二区中形成具有低浓度掺杂剂的第二本体区以形成低阈值电压器件；
在所述第一本体区和所述第二本体区之上形成栅电极；
将第二导电类型的掺杂剂毯式注入到所述第一本体区和所述第二本体区中以形成低掺杂漏极(LDD)区；
紧邻所述栅电极形成间隔物；以及
源极-漏极注入第二导电类型的掺杂剂以形成在所述间隔物之下延伸的低掺杂延伸部和低电阻的源极/漏极区，
其中，所述源极-漏极注入包括倾斜和旋转注入，并且
其中，所述毯式注入和所述源极-漏极注入足以补偿足够的所述高阈值电压器件的所述第一本体区，以确保在所述源极/漏极区与沟道区之间的低电阻连接。
2.根据权利要求1所述的方法，
其中，所述毯式注入具有1E11离子cm-2至5E13离子cm-2的低剂量。
3.根据权利要求1所述的方法，
其中，所述源极-漏极注入还包括实施相对于所述半导体衬底的表面基本垂直的第一剂量的注入。
4.根据权利要求1所述的方法，其中，所述倾斜和旋转注入包括以相对于所述半导体衬底的所述表面的倾斜角度的低于所述第一剂量的第二剂量注入，以在所述间隔物之下形成低电阻连接。
5.根据权利要求4所述的方法，其中，所述第一剂量为5E14离子cm-2至1E16离子cm-2，所述第二剂量为1E12离子cm-2至1E14离子cm-2。
6.根据权利要求1所述的方法，其中，所述毯式注入在形成所述低掺杂漏极区时略去所有的掩模操作。
7.一种半导体结构，包括：
在半导体衬底中的第一区和第二区；
位于所述第一区中的横向双扩散金属-氧化物-半导体(LDMOS)器件；
形成在所述第一区中的具有第二导电性的第一埋层；
形成在所述第一埋层上的具有第一导电性的第二埋层；
形成在所述第二埋层上的具有第二导电性的漂移区；
形成为相邻于所述漂移区的高浓度的第一本体区；
形成在所述漂移区和所述第一本体区之上的第一栅电极；
形成为紧邻所述栅电极的间隔物；
形成为在所述间隔物之下延伸的低掺杂延伸部和低电阻的源极区；
形成在所述第一本体区中的具有第一导电性的本体接触区；
与所述源极区间隔开的低电阻的漏极区；
形成在所述源极区与所述漏极区之间的所述第一本体区中的沟道区；以及
在所述源极区、所述漏极区与所述沟道区之间的低电阻连接。
8.根据权利要求7所述的结构，还包括：
在所述第二区中的低阈值电压器件；和
在所述第二区中的低浓度的第二本体区。
9.根据权利要求7所述的结构，
其中，在相同的掩模操作期间，所述漂移区和所述第二埋层以自对准的方式形成。
10.根据权利要求7所述的结构，
其中，低电阻连接通过毯式注入操作和源极/漏极的倾斜和旋转注入操作形成。
11.一种制造半导体器件的方法，所述方法包括：
在半导体衬底中制备第一区和第二区；
在所述第一区中形成具有高浓度掺杂剂的第一本体区以形成高阈值电压器件；
在所述第二区中形成具有低浓度掺杂剂的第二本体区以形成低阈值电压器件；
在所述第一本体区和所述第二本体区之上形成栅电极；
将第二导电类型的掺杂剂毯式注入到所述第一本体区和所述第二本体区中以形成低掺杂漏极(LDD)区；
紧邻所述栅电极形成间隔物；以及
源极-漏极注入第二导电类型的掺杂剂以形成在所述间隔物之下延伸的低掺杂延伸部和低电阻的源极/漏极区。
12.根据权利要求11所述的方法，其中，所述源极-漏极注入包括倾斜和旋转注入。
13.根据权利要求12所述的方法，其中，所述倾斜和旋转注入包括以相对于所述半导体衬底的所述表面的倾斜角度的低于所述第一剂量的第二剂量注入，以在所述间隔物之下形成所述低电阻连接。
14.根据权利要求13所述的方法，其中，所述第一剂量为5E14离子cm-2至1E16离子cm-2，第二剂量为1E12离子cm-2至1E14离子cm-2。
15.根据权利要求11所述的方法，其中，所述毯式注入和所述源极-漏极注入足以补偿足够的所述高阈值电压器件的所述第一本体区，以确保在所述源极/漏极区与沟道区之间的低电阻连接。
16.根据权利要求11所述的方法，其中，所述毯式注入具有1E11离子cm-2至5E13离子cm-2的低剂量。
17.根据权利要求11所述的方法，其中，所述源极-漏极注入还包括实施相对于所述半导体衬底的表面基本垂直的第一剂量的注入。
18.根据权利要求11所述的的方法，其中，所述毯式注入在形成所述低掺杂漏极区时略去所有的掩模操作。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108470680A (zh) * 2017-02-23 2018-08-31 中芯国际集成电路制造(上海)有限公司 半导体结构的制作方法
CN109390404A (zh) * 2017-08-02 2019-02-26 美格纳半导体有限公司 具有低漏源导通电阻的半导体器件及其制造方法
CN111383997A (zh) * 2020-03-02 2020-07-07 上海华虹宏力半导体制造有限公司 用于高压bcd平台互补金属氧化物半导体的制作方法
CN111883484A (zh) * 2020-08-14 2020-11-03 上海华虹宏力半导体制造有限公司 开关ldmos器件的制造方法
CN112151618A (zh) * 2020-09-27 2020-12-29 杰华特微电子（杭州）有限公司 横向超结结构的制造方法
CN113921591A (zh) * 2021-09-24 2022-01-11 上海华虹宏力半导体制造有限公司 Ldmos器件及其形成方法
US11749749B2 (en) 2017-01-25 2023-09-05 Rohm Co., Ltd. Semiconductor device

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9793153B2 (en) * 2011-09-20 2017-10-17 Alpha And Omega Semiconductor Incorporated Low cost and mask reduction method for high voltage devices
CN105990331B (zh) * 2015-02-02 2019-04-09 中芯国际集成电路制造(上海)有限公司 一种静电放电保护结构和电子装置
US20190081044A1 (en) * 2016-04-01 2019-03-14 Intel Corporation Semiconductor device having sub regions to define threshold voltages
US10886405B2 (en) * 2016-12-07 2021-01-05 Macronix International Co., Ltd. Semiconductor structure
KR102227666B1 (ko) * 2017-05-31 2021-03-12 주식회사 키 파운드리 고전압 반도체 소자
CN109148606B (zh) * 2017-06-28 2022-04-12 联华电子股份有限公司 高压元件
KR101955098B1 (ko) * 2017-07-03 2019-05-30 주식회사 케이이씨 과도 전압 억제 소자 및 그 제조 방법
CN111223768B (zh) * 2018-11-27 2024-04-05 上海先进半导体制造有限公司 低压cmos器件的制作方法
KR102224364B1 (ko) 2019-10-02 2021-03-05 주식회사 키 파운드리 고전압 반도체 소자 및 그 제조 방법
TWI761712B (zh) * 2019-10-16 2022-04-21 通嘉科技股份有限公司 可阻擋逆電流之金氧半電晶體
KR102274813B1 (ko) 2020-02-27 2021-07-07 주식회사 키 파운드리 게이트 전극 통과 이온 주입을 이용한 반도체 소자 제조방법
CN113948567A (zh) * 2020-07-17 2022-01-18 和舰芯片制造(苏州)股份有限公司 改善ldmos高压侧击穿电压的装置及其制备方法
CN113035937A (zh) * 2021-03-12 2021-06-25 电子科技大学 一种高侧功率管的esd保护结构
EP4362097A3 (de) * 2022-10-28 2024-06-05 Elmos Semiconductor SE Vorrichtung und verfahren zur substratstrombegrenzung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1602544A (zh) * 2001-12-11 2005-03-30 因芬尼昂技术股份公司 通过离子注入制造高电压mos晶体管的方法
CN101350300A (zh) * 2007-07-20 2009-01-21 中芯国际集成电路制造(上海)有限公司 轻掺杂源漏极离子注入方法
CN101950735A (zh) * 2009-07-10 2011-01-19 新加坡格罗方德半导体制造私人有限公司 高压器件
CN102376581A (zh) * 2010-08-24 2012-03-14 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其制作方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4325180A (en) 1979-02-15 1982-04-20 Texas Instruments Incorporated Process for monolithic integration of logic, control, and high voltage interface circuitry
US5021851A (en) 1988-05-03 1991-06-04 Texas Instruments Incorporated NMOS source/drain doping with both P and As
US5158903A (en) 1989-11-01 1992-10-27 Matsushita Electric Industrial Co., Ltd. Method for producing a field-effect type semiconductor device
KR940004446B1 (ko) 1990-11-05 1994-05-25 미쓰비시뎅끼 가부시끼가이샤 반도체장치의 제조방법
US5372957A (en) 1993-07-22 1994-12-13 Taiwan Semiconductor Manufacturing Company Multiple tilted angle ion implantation MOSFET method
KR100264211B1 (ko) * 1998-06-12 2000-09-01 김영환 반도체장치의 제조 방법
US6599782B1 (en) * 2000-01-20 2003-07-29 Sanyo Electric Co., Ltd. Semiconductor device and method of fabricating thereof
US6528850B1 (en) * 2000-05-03 2003-03-04 Linear Technology Corporation High voltage MOS transistor with up-retro well
WO2003017349A2 (de) * 2001-08-17 2003-02-27 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Dmos-transistor
US6677210B1 (en) * 2002-02-28 2004-01-13 Linear Technology Corporation High voltage transistors with graded extension
KR100481850B1 (ko) * 2002-05-22 2005-04-13 삼성전자주식회사 수직형 디모스 소자 및 그 제조방법
US7569873B2 (en) * 2005-10-28 2009-08-04 Dsm Solutions, Inc. Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
KR100718776B1 (ko) * 2005-11-24 2007-05-16 매그나칩 반도체 유한회사 시모스 이미지센서 제조 방법
US7602037B2 (en) * 2007-03-28 2009-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage semiconductor devices and methods for fabricating the same
US7851314B2 (en) * 2008-04-30 2010-12-14 Alpha And Omega Semiconductor Incorporated Short channel lateral MOSFET and method
US20100244152A1 (en) * 2009-03-27 2010-09-30 Bahl Sandeep R Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor
IT1393781B1 (it) * 2009-04-23 2012-05-08 St Microelectronics Rousset Fotodiodo operante in modalita' geiger con resistore di soppressione integrato e controllabile ad effetto jfet, schiera di fotodiodi e relativo procedimento di fabbricazione
JP5605134B2 (ja) * 2010-09-30 2014-10-15 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5605241B2 (ja) * 2011-01-27 2014-10-15 富士通セミコンダクター株式会社 Ｍｏｓトランジスタおよび半導体集積回路装置の製造方法
US8686502B2 (en) * 2012-03-19 2014-04-01 Texas Instruments Incorporated Schottky diode integrated into LDMOS

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1602544A (zh) * 2001-12-11 2005-03-30 因芬尼昂技术股份公司 通过离子注入制造高电压mos晶体管的方法
CN101350300A (zh) * 2007-07-20 2009-01-21 中芯国际集成电路制造(上海)有限公司 轻掺杂源漏极离子注入方法
CN101950735A (zh) * 2009-07-10 2011-01-19 新加坡格罗方德半导体制造私人有限公司 高压器件
CN102376581A (zh) * 2010-08-24 2012-03-14 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其制作方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11749749B2 (en) 2017-01-25 2023-09-05 Rohm Co., Ltd. Semiconductor device
CN108470680A (zh) * 2017-02-23 2018-08-31 中芯国际集成电路制造(上海)有限公司 半导体结构的制作方法
CN109390404A (zh) * 2017-08-02 2019-02-26 美格纳半导体有限公司 具有低漏源导通电阻的半导体器件及其制造方法
CN111383997A (zh) * 2020-03-02 2020-07-07 上海华虹宏力半导体制造有限公司 用于高压bcd平台互补金属氧化物半导体的制作方法
CN111883484A (zh) * 2020-08-14 2020-11-03 上海华虹宏力半导体制造有限公司 开关ldmos器件的制造方法
CN111883484B (zh) * 2020-08-14 2023-10-20 上海华虹宏力半导体制造有限公司 开关ldmos器件的制造方法
CN112151618A (zh) * 2020-09-27 2020-12-29 杰华特微电子（杭州）有限公司 横向超结结构的制造方法
CN113921591A (zh) * 2021-09-24 2022-01-11 上海华虹宏力半导体制造有限公司 Ldmos器件及其形成方法

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