CN113948567A - 改善ldmos高压侧击穿电压的装置及其制备方法 - Google Patents

改善ldmos高压侧击穿电压的装置及其制备方法 Download PDF

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CN113948567A
CN113948567A CN202010691317.XA CN202010691317A CN113948567A CN 113948567 A CN113948567 A CN 113948567A CN 202010691317 A CN202010691317 A CN 202010691317A CN 113948567 A CN113948567 A CN 113948567A
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屠孝瑜
李咏絮
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Abstract

本发明涉及一种改善LDMOS高压侧击穿电压的装置，包括：P型衬底，该P型衬底的上端的两侧分别设置有带保护环的P+区和场氧化层，P+区与场氧化层连接，P型衬底的上端形成有分别对称分布的源级和栅极，源级与栅极连接，栅极处设置有连接的场氧化层，栅极之间形成漏级，漏级处形成有高压N型轻掺杂漏区；P阱，该P阱在P型衬底的两侧形成并且设置在P+区下方；以及高压深N阱，该高压深N阱形成在P型衬底中并且两侧与P阱接触，其中高压深N阱为高剂量的高压深N阱，P型衬底由高阻硅片制成。此外，本发明还涉及上述装置的制备方法。通过本发明的装置和制备方法，本发明可以降低RSDNW从而提升击穿，改善寄生BJT的耐压。

Description

改善LDMOS高压侧击穿电压的装置及其制备方法
技术领域
本发明涉及LDMOS高压侧的装置及其制备方法，并且更具体地，涉及一种改善LDMOS高压侧击穿电压的装置及其制备方法。
背景技术
目前，LDMOS的高压侧产品与低压侧产品使用同一套制备过程，硅片材料的管控也是同样一套方法，然而，实际上高压侧产品和低压侧产品在寄生双级结型晶体管(BJT)耐压或击穿电压是不同的。
在高压侧产品的使用过程中，往往存在耐压不够，批和批之间差异较大的问题，对此，通常认为是装置阱(Device Well)与P型衬底(P-SUB)之间的BJT耐压不稳定，这可能是深N阱(DNW)对P型衬底窗口(P-SUB window)不够导致耐压不稳。
然而，现有的LDMOS高压侧产品的DNW通常采用的是低剂量DNW，DNW太淡，不够隔绝P型主体(P-Body)和P型衬底(P-SUB)的扩散，导致耗尽区过大，同时P型衬底由一般硅片制成，会影响DNW电阻(RSDNW)的变化，从而影响到在DNW和P-SUB之间寄生双级结型晶体管(BJT)的耐压。
参照附图1，图1更详细地说明了现有技术的情况：图1示出了通过现有制程工艺制备的LDMOS的低压侧产品和高压侧产品的示意图，其中在现有技术中，无论是LDMOS低压侧产品还是高压侧产品，DNW都是低剂量DNW，太淡，同时P型衬底都采用的是一般电阻的硅片，往往采用这样制成的产品，特别是高压侧产品的耐压不够，例如，通常高压侧产品的击穿电压大约在25-30V，想要达到30V以上需求的击穿电压往往难以实现。
发明内容
针对现有技术的不足，本发明的目的在于提供一种改善LDMOS高压侧击穿电压的装置及其方法。通过该方法和装置，本发明可以降低RSDNW从而提升击穿，改善BJT的耐压。
为了解决上述技术问题，本发明采用以下技术方案：
根据本发明的一方面，提供一种改善LDMOS高压侧击穿电压的装置，该装置包括：
P型衬底，P型衬底的上端的两侧分别设置有带保护环的P+区和场氧化层，带保护环的P+区与场氧化层连接，P型衬底的上端形成有分别对称分布的源级和栅极，源级与所述栅极连接，栅极处设置有连接的场氧化层，栅极之间形成漏级，漏级处形成有高压N型轻掺杂漏区；
P阱，P阱在P型衬底的两侧形成并且设置在带保护环的P+区下方；以及
高压深N阱，高压深N阱形成在P型衬底中并且两侧与P阱接触，
其中高压深N阱采用高剂量的高压深N阱，P型衬底由高阻硅片制成。
在本发明的一个实施例中，源极包括P型基底、P+区和N+区，其中P+区和N+区设置在P型基底上，P+区两端连接有N+区。
在本发明的一个实施例中，栅极是多晶硅栅极。
在本发明的一个实施例中，场氧化层的厚度为
Figure BDA0002589490750000021
在本发明的一个实施例中，高压深N阱的高剂量为1.05～1.15E12ea/cm2。
在本发明的一个实施例中，高阻硅片的电阻大于21欧姆。
在本发明的一个实施例中，源极的电压为5-30V。
在本发明的一个实施例中，栅极的电压为10-35V。
在本发明的一个实施例中，漏极的电压为40V。
在本发明的一个实施例中，改善后的高压侧击穿电压为30-40V。
根据本发明的另一方面，提供一种改善LDMOS高压侧击穿电压的装置的制备方法，包含以下步骤：
(1)提供由高阻硅片制成的P型衬底，在P型衬底的上端的两侧上形成带有保护坏的且连接场氧化层的P+区，并在P型衬底的上端上形成源极和栅极，在栅极处连接场氧化层并形成漏级，在漏级处形成高压N型轻掺杂漏区；
(2)在P型衬底的两侧并且在带有保护坏的且连接场氧化层的P+区下方设置P阱；以及
(3)在P形衬底中形成两侧与P阱接触的高剂量的高压深N阱。
在本发明的一个实施例中，源极包括P型基底、P+区和N+区，其中P+区和N+区设置在P型基底上，P+区两端连接有N+区。
在本发明的一个实施例中，栅极是多晶硅栅极。
在本发明的一个实施例中，高阻硅片的电阻大于21欧姆。
通过采用上述技术方案，本发明相比于现有技术具有如下优点：
本发明对现有LDMOS高压侧产品进行改进，本发明将原有的DNW低剂量更改为高剂量，从而抑制了P-Body&P-SUB耗尽区的扩散，提升了耐压，也就是降低了RSDNW从而提升击穿，并且将P型衬底采用由高阻硅片制成，从而降低了衬底对DNW的扩散影响，稳定了耐压。因此本发明采用高阻硅片的衬底搭配高剂量DNW，改善了寄生BJT的耐压，其中RSDNW可从8000降至7000，BJT击穿电压可达到30V-40V。
附图说明
本发明的上述和/或附加的方面和优点在与附图结合对实施例进行的描述中将更加明显并容易理解，其中：
图1示出了现有技术的LDMOS低压侧产品和高压侧产品的轮廓示意图；
图2是本发明改善LDMOS高压侧击穿电压的装置的轮廓示意图；
图3是本发明改善LDMOS高压侧击穿电压的装置的制备方法的示意图；
图4是利用本发明改善LDMOS高压侧击穿电压的装置测量的RS_HVDNW(高压深N阱的电阻)与BVD S_B(源级对衬底的击穿电压)的关系曲线图。
附图标记说明
High side 高压侧
Low side 低压侧
P-SUB P型衬底
Guard Ring P+ 带保护坏的P+区
FOX 场氧化层
Source 源极
POLY0-3K 多晶硅栅极
P-Base P型基底
Drain 漏级
HV_NLLD 高压N型轻掺杂漏区
P-WELL P阱
HV_DNW 高压深N阱
Device 装置
P-Body P型主体
New target 新目标
BVD Source to Sub(BVD S_B) 源级对衬底的击穿电压
RS_HVDNW 高压深N阱的电阻
Mapping data 映射数据
RS_DNW VS BVD 深N阱的电阻对击穿电压
具体实施方式
应当理解，在示例性实施例中所示的本发明的实施例仅是说明性的。虽然在本发明中仅对少数实施例进行了详细描述，但本领域技术人员很容易领会在未实质脱离本发明主题的教导情况下，多种修改是可行的。相应地，所有这样的修改都应当被包括在本发明的范围内。在不脱离本发明的主旨的情况下，可以对以下示例性实施例的设计、操作条件和参数等做出其他的替换、修改、变化和删减。
如图2所示，一种改善LDMOS高压侧击穿电压的装置，该装置包括：P型衬底P-SUB，P-SUB的上端的两侧分别设置有带保护环的P+区Guard Ring P+和场氧化层FOX，GuardRing P+与FOX连接，P-SUB的上端形成有分别对称分布的源级Source和多晶硅栅极POLY0-3K，Source包括P型基底P-Base、P+区和N+区，其中P+区和N+区设置在P-Base上，P+区两端连接有N+区，Source与POLY0-3K连接，POLY0-3K处设置有连接的FOX，POLY0-3K之间形成漏级Drain，Drain处形成有高压N型轻掺杂漏区HV_NLLD；P阱P-WELL，P-WELL在P-SUB的两侧形成并且设置在Guard Ring P+区下方；以及高压深N阱HV_DNW，HV_DNW形成在P-SUB中并且两侧与P-WELL接触，其中HV_DNW采用高剂量的HV_DNW，其颜色深，P-SUB由高阻硅片制成。
在上述装置中，FOX的厚度为
Figure BDA0002589490750000051
优选厚度为
Figure BDA0002589490750000052
在上述装置中，HV_DNW的高剂量为1.05～1.15E12 ea/cm2。
在上述装置中，高阻硅片的电阻大于21欧姆。
在上述装置中，源极的电压为5-30V。
在上述装置中，栅极的电压为10-35V。
在上述装置中，漏极的电压为40V。
在上述装置中，改善后的高压侧击穿电压为30-40V。
此外，如图3所示，本发明还提供一种改善LDMOS高压侧击穿电压的装置的制备方法，包含步骤：提供由高阻硅片制成的P-SUB，在P-SUB的上端的两侧上形成Guard Ring P+和与其连接的FOX，并在P-SUB的上端上形成源极Source和多晶硅栅极POLY0-3K，Source包括P型基底P-Base、P+区和N+区，其中P+区和N+区设置在P-Base上，P+区两端连接有N+区，在POLY0-3K处连接FOX并形成漏级Drain，在Drain处形成HV_NLLD；在P-SUB的两侧并且在Guard Ring P+区下方设置P-WELL；以及在P-SUB中形成两侧与P-WELL接触的高剂量的HV_DNW。
在上述制备方法中，高阻硅片的电阻大于21欧姆，HV_DNW的高剂量为1.05～1.15E12 ea/cm2。
通过本发明的装置和制备方法，本发明对现有LDMOS高压侧产品进行改进，本发明将原有的DNW低剂量更改为高剂量，从而抑制了P-Body&P-SUB耗尽区的扩散，提升了耐压，也就是降低了RSDNW从而提升击穿，并且将P-SUB采用由高阻硅片制成，从而降低了P-SUB对DNW的扩散影响，稳定了耐压。如图4所示，本发明更改DNW剂量和管控高阻硅片，可有效改善RSDNW以及寄生BJT的耐压，其中RSDNW可从8000降至7000，BJT击穿电压可达到30V-40V。很明显，相比于现有技术中BJT击穿电压只有25-30V而言，本申请的装置可以实现BJT击穿电压大于30V，满足客户的需求。
以上所述仅为本发明的较佳实施例，并非用来限定本发明的实施范围；如果不脱离本发明的精神和范围，对本发明进行修改或者等同替换，均应涵盖在本发明权利要求的保护范围当中。

Claims (10)

1.一种改善LDMOS高压侧击穿电压的装置，其特征在于，该装置包括：
P型衬底，所述P型衬底的上端的两侧分别设置有带保护环的P+区和场氧化层，所述带保护环的P+区与场氧化层连接，所述P型衬底的上端形成有分别对称分布的源级和栅极，所述源级与所述栅极连接，所述栅极处设置有连接的场氧化层，所述栅极之间形成漏级，所述漏级处形成有高压N型轻掺杂漏区；
P阱，所述P阱在所述P型衬底的两侧形成并且设置在所述带保护环的P+区下方；以及
高压深N阱，所述高压深N阱形成在所述P型衬底中并且两侧与所述P阱接触，
其中所述高压深N阱采用高剂量的高压深N阱，所述P型衬底由高阻硅片制成。
2.根据权利要求1所述的改善LDMOS高压侧击穿电压的装置，其特征在于，所述源极包括P型基底、P+区和N+区，其中所述P+区和所述N+区设置在所述P型基底上，所述P+区两端连接有所述N+区。
3.根据权利要求1所述的改善LDMOS高压侧击穿电压的装置，其特征在于，所述栅极是多晶硅栅极。
4.根据权利要求1所述的改善LDMOS高压侧击穿电压的装置，其特征在于，所述场氧化层的厚度为
Figure FDA0002589490740000011
5.根据权利要求1所述的改善LDMOS高压侧击穿电压的装置，其特征在于，所述高压深N阱的高剂量为1.05～1.15E12ea/cm2。
6.根据权利要求1所述的改善LDMOS高压侧击穿电压的装置，其特征在于，所述高阻硅片的电阻大于21欧姆。
7.一种改善LDMOS高压侧击穿电压的装置的制备方法，其特征在于，包含以下步骤：
(1)提供由高阻硅片制成的P型衬底，在P型衬底的上端的两侧上形成带有保护坏的且连接场氧化层的P+区，并在所述P型衬底的上端上形成源极和栅极，在栅极处连接场氧化层并形成漏级，在漏级处形成高压N型轻掺杂漏区；
(2)在所述P型衬底的两侧并且在所述带有保护坏的且连接场氧化层的P+区下方设置P阱；以及
(3)在所述P型衬底中形成两侧与所述P阱接触的高剂量的高压深N阱。
8.根据权利要求7所述的制备方法，其特征在于，所述源极包括P型基底、P+区和N+区，其中所述P+区和所述N+区设置在所述P型基底上，所述P+区两端连接有所述N+区。
9.根据权利要求7所述的制备方法，其特征在于，所述栅极是多晶硅栅极。
10.根据权利要求7所述的制备方法，其特征在于，所述高阻硅片的电阻大于21欧姆。
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