CN104798183B - 利用定向自组装的垂直纳米线晶体管沟道和栅极的图案化 - Google Patents

利用定向自组装的垂直纳米线晶体管沟道和栅极的图案化 Download PDF

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CN104798183B
CN104798183B CN201380060134.6A CN201380060134A CN104798183B CN 104798183 B CN104798183 B CN 104798183B CN 201380060134 A CN201380060134 A CN 201380060134A CN 104798183 B CN104798183 B CN 104798183B
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CN104798183A (zh
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P·A·尼许斯
S·希瓦库马
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Intel Corp
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Abstract

本发明描述了定向自组装(DSA)材料或二嵌段共聚物，其可能基于一次光刻操作来对最终限定垂直纳米线晶体管的沟道区和栅极电极的特征进行图案化。在实施例中，DSA材料被约束在使用常规光刻技术进行图案化的引导开口内。在实施例中，沟道区和栅极电极材料对准到DSA材料内的分离的区域的边缘。

Description

利用定向自组装的垂直纳米线晶体管沟道和栅极的图案化
技术领域
本发明的实施例总体上涉及微电子器件的晶体管制造，并且更具体地涉及使用定向自组装(DSA)的垂直纳米线晶体管的图案化。
背景技术
在垂直取向的晶体管中，良好控制的材料层厚度限定了诸如栅极长度(Lg)的功能长度，并且可以有利地定制材料组成以获得带隙和迁移率差别。可以通过沟道宽度(Wg)和纳米线的对应截面的光刻图案化来连续缩放电流驱动。然而，在实际应用中，可能需要印刷直径为15nm左右或更小同时具有非常好的临界尺寸(CD)均匀性和良好的圆度并且具有最小特征间距以获得最高的密度的纳米线特征(例如，孔)。此外，必须要使沟道图案与栅极堆叠体和接触金属化部准确对准。
小于15nm并且具有足够的CD均匀性、圆度和间距的孔的光刻印刷超出了已知ArF或UEV抗蚀剂的能力。将孔印刷得更大并且然后使其缩小的技术不能获得期望的间距(例如，<30nm)。这种间距甚至还低于双掩模图案化技术的分辨率，并且像这样会需要至少三个掩模图案化步骤以及采用昂贵的光刻工具箱的非常强力的缩小工艺。
因此，能够以较低成本制造的用于将垂直纳米线晶体管图案化成尺寸低于15nm并且间距低于30nm的技术是有益的。
附图说明
通过示例而不是限制的方式示出了本发明的实施例，在附图的图中：
图1是根据实施例的垂直纳米线晶体管的等距示图；
图2是根据实施例的示出形成垂直纳米线晶体管的方法的流程图；
图3A、3B、3C、3D和3E示出了根据实施例的在执行图2的方法中的操作时形成的单沟道结构的平面图；
图4A、4B、4C、4D和4E示出了根据实施例的图3A-3E中所示的结构的截面图；
图5A、5B、5C、5D、5E和5F示出了根据实施例的在执行图2的方法中的操作时形成的单沟道结构的平面图；
图6A、6B、6C、6D、6E和6F示出了根据实施例的图5A-5D中所示的结构的截面图；
图7A、7B和7C示出了根据实施例的在执行图2的方法中的操作时形成的双沟道结构的平面图；
图8A、8B和8C示出了根据实施例的图7A-7C中所示的结构的截面图；
图9A、9B、9C、9D和9E示出了根据实施例的在执行图2的方法中的操作时形成的单沟道结构的截面图；
图10A、10B、10C、10D、10E、10F和10G示出了根据实施例的在执行图2的方法中的操作时形成的单沟道结构的截面图；
图11是根据本发明的实施例的采用非平面晶体管的移动计算平台的功能框图；以及
图12示出了根据一个实施例的计算设备的功能框图。
具体实施方式
在以下描述中，阐述了许多细节，然而，对于本领域技术人员而言显而易见的是，在没有这些具体细节的情况下也可以实践本发明。在一些实例中，公知的方法和设备以框图的形式而不是以细节的形式示出，以避免使本发明难以理解。在整个说明书中，对“实施例”的引用表示结合实施例所描述的特定特征、结构、功能或特性包括在本发明的至少一个实施例中。因此，在整个说明书中的各处出现的短语“在实施例中”不一定指代本发明的同一个实施例。此外，特定特征、结构、功能或特性可以采用任何适合的方式组合在一个或多个实施例中。例如，第一实施例可以与第二实施例组合，只要这两个实施例在结构或功能上彼此不互斥。
术语“耦合”和“连接”及其衍生词在本文中可以用于描述部件之间的结构关系。应该理解，这些术语并不是要作为彼此的同义词。相反，在特定实施例中，“连接”可以用于指示两个或更多元件彼此直接物理接触或电接触。“耦合”可以用于指示两个或更多元件彼此直接或间接地(其间具有其它中间元件)物理接触或电接触，和/或指示两个或更多元件彼此配合或相互作用(例如，如在因果关系中)。
如本文中使用的术语“在…之上”、“在…之下”、“在….之间”和“在…上”指代一个材料层相对于其它层的相对位置。像这样，例如，设置在一个层之上或之下的另一个层可以与该层直接接触，或可以具有一个或多个中间层。此外，设置在两个层之间的一个层可以与这两个层直接接触，或可以具有一个或多个中间层。相比之下，第二层“上”的第一层与该第二层直接接触。
图1是可以根据本发明的实施例制造的示例性垂直纳米线晶体管101的等距示图。对于垂直纳米线晶体管101，半导体纳米线相对于衬底105垂直取向，以使纵向长度L沿z维度(垂直于衬底105的表面平面)并且宽度W限定衬底105的由纳米线所占据的面积。对于横向取向的晶体管，垂直晶体管101包括沿纵向长度L的一种或多种半导体材料，其对应于包括设置在非本征源极/漏极区135B、源极/漏极区130B和源极/漏极区120B之间的沟道区145B的晶体管的功能区。根据实施例，晶体管101的漏极可以“朝下”设置在衬底105上，或者晶体管可以被倒置以具有“朝下的源极”。在垂直形式中，晶体管101具有临界尺寸，例如由材料层厚度限定的沟道长度和Lg(即，纵向长度L的部分)，其可以通过外延生长工艺、注入工艺或沉积工艺而得到非常好的控制(例如，至)。
通常，衬底105以及第一和第二半导体材料层111C、111B可以是本领域中已知的任何材料，包括Ⅳ族材料(例如，Si、Ge、SiGe)、Ⅲ-N材料(例如，GaN、AlGaN等)或Ⅲ-Ⅴ族材料(例如InAlAs、AlGaAs等)。漏极/源极区130B、120B具有半导体材料层111A、111D，它们可以是与沟道区145B相同的材料或不同的材料。源极/漏极接触部122B可以包括设置在源极/漏极区120上的半导体111E，例如p+隧穿层和/或高度掺杂(例如，n+)的低带隙帽层。源极接触部122B中还可以包括低电阻率欧姆接触金属。
晶体管101包括栅极堆叠体150B，其完全同轴包围沟道区145B内的纳米线。类似地，源极/漏极接触部122B和132B还被示出为同轴包围源极/漏极区120B、130B，尽管不必这样。设置在栅极堆叠体150B之间，第一电介质间隔体(未示出)设置在源极/漏极接触部132B上并且沿第一纵向长度完全同轴包围非本征源极/漏极区135B。第二电介质间隔体156设置在栅极堆叠体150B上并且沿第二纵向长度完全同轴包围非本征源极/漏极区120B，并且源极/漏极接触部132B设置在第二电介质间隔体上。
图2是根据实施例的示出形成诸如晶体管101的垂直纳米线晶体管的方法201的流程图。通常，方法201需要采用诸如二嵌段共聚物的定向自组装(DSA)材料，从而可能在不需要扫描仪的情况下基于一次光刻操作来对最终限定垂直纳米线晶体管的沟道区的特征进行图案化。
方法201在操作205处开始于以光刻方式图案化掩模层中的引导开口(guideopening)。引导开口用于提供DSA材料要对准的边缘，并且更具体地引导开口是封闭多边形，并且有利地是弧形，并且更具体地是圆形。在操作205处可以同时印刷任意数量的引导开口，例如可以使用本领域中已知的任何常规光刻工艺来印刷引导开口的1维或2维阵列。如本文使用的，1维阵列需要引导开口中的一行或一列在行或列维度中的相邻开口之间具有最小间距并且在相邻行或列之间的距离超过最小间距，而2维阵列需要引导开口的行和列在行和列维度中的所有引导开口之间具有最小间距。可以改变引导开口的尺寸和形状以允许在给定引导层开口中图案化多于一个沟道孔，例如图7b所示。
图3A-3D示出了根据实施例的在执行方法201中的操作时形成的单沟道晶体管结构的平面图。圆形引导开口315在图3A中示出并且表示在操作205处印刷的1维或2维阵列的一个重复单元。图4A-4D分别示出了沿图3A中所示的A'-A线截取的图3A-3E中所示的结构的截面图。在示例性实施例中，圆形引导开口315具有不超过20nm的临界尺寸(CD1)并且多边形边缘306限定穿过掩模340的厚度的孔305(图4A)，掩模340可以是光致抗蚀剂或硬掩模材料。在光致抗蚀剂实施例中可以利用适合于所采用的光刻工具的任何常规抗蚀剂配方。掩模340设置在半导体层之上，半导体层具有对应于要提供纳米线晶体管的沟道区的期望的晶体管沟道长度(Lg)的z高度厚度(Tl)。对于图4A中所示的示例性实施例，掩模340直接设置在沟道半导体层315(例如，单晶硅、SiGe等)上，尽管诸如硬掩模材料层(例如，SixNy、SiO2等)的中间材料层可以设置在光致抗蚀剂层340与沟道半导体层315之间。
返回图2，方法201继续进行操作210，其中将DSA材料沉积到操作205处形成的引导开口中。在准备涂覆DSA材料时，可以处理层315的表面，以使其对聚合物A和聚合物B的吸引/排斥相等。如图3B和4B所示，DSA材料350填充引导开口315并且被引导开口边缘306包含。DSA材料350通常包括至少第一和第二聚合物(即，聚合物A和聚合物B)。在例如通过旋涂而被涂覆在衬底之上时，聚合物A和B处于混和状态。除了聚合物A和B的基础化学性质之外，根据引导操作315的几何形状和CD以及晶体管沟道区的期望的CD，聚合物A和B均可以被选择为具有期望的分子量分布并且DSA材料350可以被选择为具有期望的聚合物A与聚合物B的比值(A：B)。尽管可以利用本领域中公知的任何DSA材料，但在示例性实施例中，聚合物A和聚合物B的其中之一存在于用作掩模340的光致抗蚀剂中。例如，在掩模340包括聚苯乙烯的情况下，聚合物A或聚合物B也是聚苯乙烯。在一个这种实施例中，聚合物中的另一个是PMMA(聚(甲基丙烯酸甲酯))。
方法201(图2)继续进行操作215，其中将DSA材料分离成内部和外部聚合物区。当在高温下、在足以允许聚合物的充分迁移的持续时间内对DSA材料350进行退火时，根据引导开口315的尺寸和聚合物的分子量等将聚合物A从聚合物B中分离。在引导开口315包封DSA材料350的情况下，可以对离析进行工程设计以使聚合物的其中之一(例如，聚合物A)从引导边缘306迁移走，而聚合物中的另一种(例如，聚合物B)朝向引导边缘306迁移。然后主要包括第一聚合物的内部聚合物区350A被主要包括第二聚合物的外部聚合物区350B完全包围。在图3C和4C所示的示例性实施例中，内部聚合物区350A与引导开口边缘间隔开，以具有从CD1减小的直径CD2。对于适当选择的DSA成分、下层和引导开口边缘表面性质，内部聚合物区350A形成嵌入在外部聚合物区350B内的整数个大体上相同的圆柱或球体。尽管在图3A-3E所示的示例性单沟道实施例中形成了单个内部聚合物区350A，但可以形成多个这种区域，其中在至少一个维度上将引导开口的尺寸调整得足够大。在分离机制是DSA材料的共聚物性质的良好控制的功能的情况下，(多个)内部聚合物区彼此以及与引导开口边缘保持一致的距离。像这样，内部聚合物区350A与引导开口边缘306有效地自对准。
在操作215处执行的热处理和/或固化之后，方法201继续进行操作220，其中通过相对于彼此有选择地去除内部和外部聚合物区的其中之一来将晶体管的半导体沟道区限定在引导开口内部。在图3D和4D所示的示例性实施例中，相对于内部聚合物区350A有选择地去除(例如，分解)外部聚合物区350B。进一步如图所示，还相对于掩模340有选择地去除外部聚合物区350B，从而在操作220处限定两个边缘：内部聚合物区350A的边缘和引导开口边缘306，并且内部聚合物区350A的边缘与引导开口边缘306自对准。
然后环形沟槽375被蚀刻穿过沟道半导体层315和所去除的内部聚合物区350A以及掩模340。可以利用本领域中已知的针对给定半导体材料(Si、SiGe等)的任何蚀刻工艺来使沟道半导体层325的暴露的部分凹陷，以形成与晶体管Lg相关联的沟道区315A的侧壁，其与内部聚合物区350A的边缘对准。如本文中使用的，“对准”允许承受一些很小的蚀刻偏置(正或负)，这可能改变沟道区315A的CD而使其与CD2不同，但是沟道区315A的尺寸仍然基于内部聚合物区350A的尺寸并且因此而明显小于引导开口的尺寸(CD1)。例如，可以利用穿过沟道区315A的各向异性蚀刻以及随后的使沟道区315A的侧壁相对于内部聚合物区350A的CD凹陷的各向同性蚀刻来使沟道区315A的侧壁与内部聚合物区350A对准。在引导开口CD1小于20nm的一个实施例中，沟道区315A具有小于15nm的CD2。例如，基于成分蚀刻选择性或基于定时蚀刻，沟槽375可以停止在下层半导体材料310(例如，单晶Si、SiGe、Ge等)上。根据实施例，下层半导体材料310已经被重掺杂为特定导电类型(可以在其被暴露时被掺杂)，或者被部分去除并且重新生长为掺杂材料。在图3D和4D所示的实施例中，半导体材料310被重掺杂以用作源极/漏极区(例如，图1中的源极/漏极区111A和/或非本征源极/漏极区111B)。
利用在操作220处限定的半导体沟道区，在操作225处，方法201继续将栅极材料沉积在半导体沟道区的侧壁之上。通常，可以执行本领域中已知的任何栅极电介质沉积工艺，包括牺牲栅极电介质的沉积，牺牲栅极电介质随后在制造过程中后将被替换(例如，如在常规的“后栅极”型工艺流程中)。然而，在示例性实施例中，在操作225处，非牺牲高k(例如，>9)栅极电介质380沉积在沟槽375的底部处和沟槽侧壁380A和380B上所暴露的半导体表面上。作为一个示例，在操作225处，通过原子层沉积来将例如但不限于HfO2或ZrO2的金属氧化物沉积为栅极电介质380。
然后方法201以操作230完成，其中半导体沟道区315A被栅极电极材料包围。在示例性实施例中，操作230包括利用栅极电极材料390填充圆柱形沟槽375。栅极电极材料390可以包括任何常规栅极电极材料，例如但不限于多晶硅、功函数金属和/或填充金属。可以利用例如但不限于沉积和抛光的本领域中已知的技术来使栅极电极材料390与沟道区315A或上覆硬掩模层成一平面。如图3E和4E所示，栅极电介质380将栅极电极材料390与沟道区315A以及下层源极/漏极区310和外围半导体材料315B电隔离。注意，栅极电极材料390的尺寸因此完全自对准到引导开口边缘306以及自对准到沟道区315A，并且仅栅极电极材料390的z高度厚度根据期望的晶体管沟道长度而变化。然后可以利用常规技术(例如，半导体沟道区315A的暴露的表面上的源极/漏极半导体111D的沉积或外延生长、接触金属化部的沉积等)完成垂直晶体管。
图5A-5F示出了根据替代的实施例的在执行方法201中的操作时形成的单沟道结构的平面图。图6A-6F示出了根据实施例的图5A-5F中所示的结构的截面图。通常，在图5A-5F中所示的实施例中，操作205-215如在图3A-3D的上下文中所述的那样，只是掩模340沉积在设置于半导体层310之上的电介质层415(例如，SixNy、SiON、SiO2等)上。在将共聚物分离成内部聚合物区350A和外部聚合物区350B之后，在操作220处相对于外部聚合物区350B来有选择地去除内部聚合物区350A，如图5D和6D中所示。在该示例性实施例中，还去除掩模340，留下由外部聚合物区350B组成的环形掩模。然后蚀刻电介质层415以暴露半导体材料310的下层晶体表面。如图6E所示，操作220还包括去除外部聚合物区350B并且从暴露的晶体半导体表面外延生长(例如，利用MOCVD等)半导体沟道区315A，其中电介质层415用作生长停止硬掩模。给定半导体沟道区315A的尺寸(例如，<15nm)，生长的半导体材料层由于高宽比捕获的原因而可能有利地具有良好的结晶度。在形成半导体沟道区315A之后，使电介质层415的第二部分凹陷以形成暴露半导体沟道区的侧壁的圆柱形沟槽。在所示示例性实施例中，完全去除了电介质层415，暴露了半导体层310的表面。对于一个这种实施例，适当掺杂半导体层310以将其用作纳米线晶体管的源极/漏极半导体区，然后直接在源极/漏极半导体区的表面上外延生长沟道区315A。
如图5F和6F所示，方法201然后继续进行操作225以在侧壁380A上、半导体材料层310之上和侧壁380B上形成栅极电介质，大体上如本文中其它位置参考图3E和4E所描述的那样。然后在操作230处沉积栅极电极材料390，以再次包围沟道区315A。
尽管图3A-3E和4A-4E以及图5A-5F和6A-6F示出了方法201的单沟道实施例，图7A-7C示出了根据实施例的在执行方法201中的操作时形成的双沟道结构的平面图。图8A-8C还示出了图7A-7C中所示的结构的截面图。通常，大体上如本文中其它位置针对单沟道实施例所描述的那样实践方法201，并且DSA材料限定两个(或更多)内部聚合物区，其中的每一个都成为限定垂直纳米线晶体管的半导体沟道区的基础。对于这种多沟道实施例，利用DSA材料来将沟道区自对准到周围的栅极，并且还相对于印刷引导开口所采用的间距来减小相邻沟道区之间的间距。在示例性实施例中，两个相邻沟道区的间距低于印刷引导开口所采用的扫描仪的分辨极限。
图7A和8A示出了最初被图案化(例如，印刷或蚀刻)成掩模340(例如，在操作205处)的引导开口315在第一维度(例如，轴B1)上比在第二维度(例如，轴A1)上大。通常，较长的长度B1超过DSA材料的阈值特性(例如，40nm)，而较短的长度A1则不超过(例如，对于单沟道实施例，A1可以大致是引导开口的直径(例如，小于20nm))。在实施例中，较长的长度B1至少是较短的长度A1的两倍。对于特定表面条件，这种细长的引导开口315在填充有具有适当共聚物性质的DSA材料时退火成图7B和8B中所示的两个内部聚合物区350A1和350A2。内部聚合物区350A1和350A2都被邻接的外部聚合物区350B包围，并且每个分离的区域的材料性质如本文其它位置在单沟道实施例的上下文中所述的那样。在分离时，内部聚合物区350A1和350A2具有实质上相同的尺寸(例如，图8C中所示的CD3)。在引导开口的至少一个维度小于20nm的示例性实施例中，内部聚合物区350A1和350A2均具有小于15nm的宽度，并且在其它这种实施例中，内部聚合物区350A1和350A2的间距也小于15nm。
在多个内部聚合物区350A1和350A2在材料上有别于外部聚合物区350B的情况下，方法201大体上如针对单沟道实施例(例如，如图3A-3E、4A-4E所示)所描述的那样继续进行操作220、225、230，以将沟道半导体层315限定成两个沟道区315A1和315A2，它们分别由穿过栅极电介质350A1和350A2的共享栅极电极390来控制。像这样，DSA材料的分离能力可以用于制作多线垂直晶体管，其尺寸可以被分别调整以实现最优栅极控制(减小的短沟道效应)，同时提供期望量的驱动电流(由所形成的分立沟道的数量确定)。
在实施例中，不仅垂直晶体管的沟道区和栅极是基于DSA材料的分离来限定的，晶体管的例如但不限于源极/漏极区的其它功能区也是这样的，如图9A-9E和10A-10G所示。图9A、9B、9C、9D和9E示出了根据实施例的在执行图2B的方法中的操作时形成的单沟道结构的截面图。通常，在该示例性实施例中，在由DSA材料的分离所限定的区域中重新生长垂直纳米线晶体管的源极/漏极区以及沟道区。
图9A开始于操作215的完成，其中已经将DSA材料分离成内部聚合物区350A和外部聚合物区350B。该实施例中的衬底包括设置于简并掺杂的半导体层945之上的电介质层925，半导体层945还被设置于晶体半导体衬底层903之上。相对于外部聚合物区350B而有选择地去除内部聚合物区350A，如本文中其它位置所述的，并且还相对于掩模340而有选择地去除内部聚合物区350A，如图9B所示。然后穿过电介质层925和层945在去除内部聚合物区350A以暴露半导体903的区域中蚀刻内部沟槽。在之后去除了掩模340的情况下，去除了电介质层925的外围部分以留下电介质925的包围内部沟槽的环形周界。然后采用选择性外延工艺来从内部沟槽和外围区内的暴露的半导体衬底层903的种子表面形成纳米线晶体管。如图9D所示，从半导体衬底层903并且从半导体层945生长第一(底部)晶体源极/漏极半导体层310。源极/漏极半导体层310的重新生长可以改善随后生长的沟道区中的结晶度，因为在源极/漏极半导体层310中可能发生有利的缺陷捕获。此外，源极/漏极半导体层310的重新生长用来有选择地形成与现在嵌入的导电半导体层945的连接，并且晶体或多晶半导体形成在半导体层945之上。然后从源极/漏极半导体层310外延生长半导体沟道区315。第二(顶部)源极/漏极半导体层320进一步生长在半导体沟道区315之上。重新生长的膜被往回抛光以使其与作为抛光停止层的电介质层925成一平面。由于内部沟槽与外围之间的初始非平面性，平面化过程去除了外围中重新生长的半导体使其回到底部源极/漏极半导体层310，而顶部源极/漏极半导体层320保持在内部区中作为垂直纳米线晶体管的部分。
在操作220处通过首先使电介质层925的保留原始设置的外部聚合物区350B的环形部分凹陷来形成栅极电介质。这暴露了半导体沟道区315的侧壁。可以利用对下层导电层945有选择性的蚀刻来使电介质层925完全凹陷，在这种情况下，操作225处形成的栅极电介质用来使栅极电极材料390与导电层945绝缘。替代地，可以使电介质层925仅部分凹陷(例如，利用定时的深蚀刻)以增大栅极电极材料390与下层导电层945之间的电介质的厚度。像这样，图9E中所示的垂直纳米线晶体管结构的顶表面被平面化，并提供了对晶体管的所有功能区的顶侧接入，以进行接触(例如，硅化)和互连金属化。
图10A、10B、10C、10D和10E示出了根据实施例的在执行图2B的方法中的操作时形成的单沟道结构的截面图。在该示例性实施例中，基于DSA材料来蚀刻包括两个源极/漏极层和沟道层的半导体材料的堆叠体。因此该实施例可以被视为图3A-3E、4A-4E所示实施例的特殊情况。图10A开始于将DSA材料分离成内部和外部聚合物区350A、350B。衬底包括半导体材料层堆叠体，其包括成分不同的(通过掺杂或不同晶格原子)材料层。对于示例性实施例，半导体材料堆叠体包括设置在衬底1003上的底部源极/漏极层1010、设置在底部源极/漏极层1010上的沟道层1015和设置在沟道层1015之上的顶部源极/漏极层1020。设置在半导体堆叠体之上的是电介质(硬掩模)层1030。
如图10B所示，相对于内部聚合物区350A和掩模340有选择地去除外部聚合物区350B。然后穿过堆叠体的大部分蚀刻环形沟槽，以暴露底部源极/漏极层1010，如图10C中所示。沿着半导体堆叠体的侧壁形成电介质间隔体1040(图10D)，并且在暴露的源极/漏极层1010上形成硅化物1050。然后在沟槽内沉积电介质材料1060，使其平面化并凹陷(深蚀刻)到足以重新暴露沟道区侧壁的z高度(厚度)。各向同性蚀刻去除了电介质间隔体1040并且在沟道半导体侧壁上的凹陷的电介质材料1060之上的沟槽中沉积栅极电介质380。然后在沟槽中沉积栅极电极材料，使其与电介质1030的顶表面成一平面，并且然后将其凹陷蚀刻到足以控制沟道区的z高度(厚度)。最后，在沟槽中沉积电介质1070，使其与电介质1030的顶表面成一平面。然后可以相对于电介质1070有选择地去除电介质1030以暴露顶部源极/漏极1020，为接触金属化做准备。因此，基于单个光刻掩模和DSA材料，以自对准方式制造了具有亚光刻线尺寸(例如，<15nm)的垂直取向的纳米线晶体管以及本地互连。
图11是根据本发明实施例的移动计算平台的SoC实施方式的功能框图。移动计算平台1100可以是被配置为用于电子数据显示、电子数据处理和无线电子数据传输中的每一个的任何便携式设备。例如，移动计算平台1100可以是平板电脑、智能电话、膝上型计算机等中的任何设备，并且包括显示屏1105、SOC 1110和电池1115。如图所示，SoC 1110的集成水平越高，移动计算设备1100内的由电池1115占用以获得充电之间的最长操作寿命、或由诸如固态驱动器、DRAM等的存储器(未示出)占用以获得最大平台功能的形状因子越大。
扩展视图1120中进一步示出了SoC 1110。根据实施例，SoC 1110包括硅衬底1160(即，芯片)的一部分，在该部分上有功率管理集成电路(PMIC)1115、包括RF发送器和/或接收器的RF集成电路(RFIC)1125、其控制器1111以及一个或多个中央处理器内核或存储器1177中的一个或多个。在实施例中，SoC 1110包括根据本文描述的一个或多个实施例的一个或多个垂直纳米线晶体管(FET)。在其它实施例中，SoC 1110的制造包括本文描述的用于制造垂直取向的纳米线晶体管(FET)的一种或多种方法。
图12是根据本发明的一个实施例的计算设备1200的功能框图。例如，计算设备1200可以在平台1100内部找到，并且还包括容纳许多部件的板1202，所述部件例如但不限于处理器1204(例如，应用处理器)和至少一个通信芯片1206。在实施例中，处理器1204至少包括具有根据本文中其它位置所描述的实施例的结构和/或根据本文中其它位置进一步描述的实施例所制造的垂直纳米线晶体管(FET)。处理器1204物理和电耦合到板1202。处理器1204包括封装在处理器1204内的集成电路管芯。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将这些电子数据转换成可以存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的一部分。
在一些实施方式中，至少一个通信芯片1206也物理和电耦合到板1202。在其它实施方式中，通信芯片1206是处理器1204的部分。取决于其应用，计算设备1200可以包括可以或可以不与板1202物理和电耦合的其它部件。这些其它部件包括但不限于：易失性存储器(例如，DRAM)、闪速存储器或STTM等形式的非易失性存储器(例如，RAM或ROM)、图形处理器、数字信号处理器、加密处理器、芯片集、天线、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、照相机、以及大容量存储设备(例如，硬盘驱动器、固态驱动器(SSD)、光盘(CD)等)。
通信芯片1206的至少其中之一可以实现用于来往于计算设备1200的数据传输的无线通信。术语“无线”及其衍生词可以用于描述电路、设备、系统、方法、技术、通信信道等等，其可以通过使用调制的电磁辐射而经由非固态介质传送数据。术语并不暗示相关联的设备不包含任何线路，尽管在一些实施例中相关联的设备可能不包含任何线路。通信芯片1206可以实施包括但不限于本文中的其它地方所描述的标准或协议的许多无线标准或协议中的任何一种。计算设备1200可以包括多个通信芯片1206。例如，第一通信芯片1206可以专用于较短范围的无线通信，例如，Wi-Fi和蓝牙，并且第二通信芯片1206可以专用于较长范围的无线通信，例如，GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
要理解，以上描述旨在进行说明，而非进行限制。例如，尽管附图中的流程图示出由本发明的特定实施例执行的操作的特定顺序，但是应该理解，并不要求这种顺序(例如，替代的实施例可以按照不同的顺序执行操作、组合某些操作、重叠某些操作等)。此外，本领域中的技术人员在阅读并理解以上描述后，许多其它实施例将是显而易见的。尽管已经参考具体示例性实施例对本发明进行了描述，但是应该认识到，本发明不限于所描述的实施例，而是可以在所附权利要求的精神和范围内利用修改和改变来实践本发明。因此，应该参考所附权利要求、以及为这种权利要求赋予权利的等同物的全部范围来确定本发明的范围。

Claims (15)

1.一种在衬底上形成纳米线场效应晶体管(FET)的方法，所述方法包括：
在设置在所述晶体管的源极/漏极半导体层之上的掩模层中以光刻方式对第一直径的引导开口进行图案化；
将定向自组装(DSA)材料沉积到所述引导开口中；
将所述定向自组装(DSA)材料分离成被所述引导开口内的外部聚合物区完全包围的内部聚合物区；
通过相对于彼此有选择地去除所述内部聚合物区和所述外部聚合物区的其中之一来在所述引导开口内限定所述晶体管的半导体沟道区，其中，所述半导体沟道区的直径以及与所述引导开口的边缘的间隔都由定向自组装(DSA)分离部来限定；
去除所述内部聚合物区和所述外部聚合物区中的另一个；
将栅极电介质沉积在所述半导体沟道区之上；以及
利用具有自对准到所述引导开口的外直径的环形栅极电极包围所述半导体沟道区。
2.根据权利要求1所述的方法，其中，限定所述半导体沟道区还包括：
去除所述外部聚合物区，同时保留所述内部聚合物区，以暴露沟道半导体层的一部分；以及
使所述沟道半导体层的暴露的部分凹陷以形成圆柱形沟槽，所述圆柱形沟槽具有与所述晶体管的与所述内部聚合物区的边缘对准的沟道长度相关联的沟道半导体侧壁。
3.根据权利要求2所述的方法，其中，所述凹陷暴露所述晶体管的源极/漏极半导体区，并且其中，所述栅极电介质将所述源极/漏极半导体区与所述栅极电极隔离。
4.根据权利要求2所述的方法，其中，将栅极电介质沉积在所述半导体沟道区之上还包括：将所述栅极电介质沉积到所述圆柱形沟槽中并且覆盖所述沟道半导体侧壁；并且
其中，利用所述栅极电极包围所述半导体沟道区包括：利用栅极电极材料填充所述圆柱形沟槽。
5.根据权利要求1所述的方法，其中，限定所述半导体沟道区还包括：
去除所述内部聚合物区，同时保留所述外部聚合物区，以暴露电介质层的下层的第一部分；
在所述电介质层的暴露的所述第一部分中蚀刻出沟槽以暴露晶体半导体表面；以及
从暴露的所述晶体半导体表面外延生长所述半导体沟道区；以及
使所述电介质层的与所述半导体沟道区相邻的第二部分凹陷以形成使所述半导体沟道区的侧壁暴露的圆柱形沟槽。
6.根据权利要求5所述的方法，其中，所述晶体半导体表面是所述晶体管的源极/漏极半导体区的表面。
7.根据权利要求5所述的方法，其中，所述晶体半导体表面是未掺杂或轻掺杂的半导体衬底的表面，并且其中，外延生长所述半导体沟道区还包括：首先从所述半导体衬底的所述表面生长所述晶体管的源极/漏极半导体区，并且然后从所述源极/漏极半导体区生长所述半导体沟道区。
8.根据权利要求5所述的方法，其中，将栅极电介质沉积在所述半导体沟道区之上还包括：将所述栅极电介质沉积到所述圆柱形沟槽中并且覆盖所述半导体沟道区的侧壁；并且
其中，利用所述栅极电极包围所述半导体沟道区包括：利用栅极电极材料填充所述圆柱形沟槽。
9.根据权利要求8所述的方法，其中，将所述栅极电介质沉积在所述电介质层的凹陷的所述第二部分之上。
10.根据权利要求1所述的方法，其中，以光刻方式对引导开口进行图案化还包括：印刷在第一维度上具有第一直径、在第二维度上具有第二直径的开口，所述第二直径至少是所述第一直径的两倍；
其中，将所述定向自组装(DSA)材料分离成被所述引导开口内的所述外部聚合物区完全包围的所述内部聚合物区还包括：形成第一聚合物区和第二聚合物区，每个聚合物区都被所述外部聚合物区完全包围；并且
其中，限定所述半导体沟道区还包括：形成第一沟道区和第二沟道区，每个沟道区都具有由所述定向自组装(DSA)分离部限定的直径以及与所述引导开口的边缘的间隔。
11.根据权利要求1所述的方法，其中，将所述定向自组装(DSA)材料沉积到所述引导开口中还包括：旋涂包括第一聚合物材料和第二聚合物材料的定向自组装(DSA)材料；并且
其中，分离所述定向自组装(DSA)材料还包括：在一定温度下并且在足以允许所述第一聚合物材料迁移到所述内部聚合物区中、而所述第二聚合物材料迁移到所述外部聚合物区中的持续时间内固化所述定向自组装(DSA)材料。
12.根据权利要求11所述的方法，其中，所述第一聚合物材料和所述第二聚合物材料的其中之一包括PMMA。
13.根据权利要求12所述的方法，其中，所述第一聚合物材料和所述第二聚合物材料中的另一种包括聚苯乙烯。
14.根据权利要求11所述的方法，其中，所述掩模层包括所述第一聚合物材料和所述第二聚合物材料的其中之一。
15.一种在衬底上形成纳米线场效应晶体管(FET)的方法，所述方法包括：
在设置在所述晶体管的源极/漏极半导体层之上的掩模层中以光刻方式对第一直径的引导开口进行图案化；
通过旋涂包括第一聚合物材料和第二聚合物材料的定向自组装(DSA)材料来将定向自组装(DSA)材料沉积到所述引导开口中；
通过在一定温度下并且在足以允许所述第一聚合物材料迁移到内部聚合物区中、而所述第二聚合物材料迁移到外部聚合物区中的持续时间内固化所述定向自组装(DSA)材料来将所述定向自组装(DSA)材料分离成被所述引导开口内的所述外部聚合物区完全包围的所述内部聚合物区；
相对于所述内部聚合物区有选择地去除所述外部聚合物区，以形成使下层硬掩模层暴露的圆柱形沟槽；
蚀刻穿过所述硬掩模层以推进所述沟槽并且暴露第一半导体源极/漏极区；
蚀刻穿过所述第一半导体源极/漏极区的暴露的部分以推进所述沟槽并且暴露设置于所述第一半导体源极/漏极区下方的半导体沟道层；
蚀刻所述半导体沟道层的暴露的部分以推进所述沟槽并且暴露设置于所述半导体沟道层下方的半导体层；
利用第一电介质材料填充所述沟槽并且相对于所述硬掩模层有选择地深蚀刻所述第一电介质材料，以暴露所述半导体沟道层的侧壁；
将栅极电介质沉积在所述侧壁之上；以及
利用栅极电极材料填充所述沟槽以利用具有自对准到所述引导开口的外直径的环形栅极电极来包围所述侧壁。
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