TW201541526A - 垂直奈米線電晶體通道的圖案化及具有定向自組裝的閘極 - Google Patents

垂直奈米線電晶體通道的圖案化及具有定向自組裝的閘極 Download PDF

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TW201541526A
TW201541526A TW104124535A TW104124535A TW201541526A TW 201541526 A TW201541526 A TW 201541526A TW 104124535 A TW104124535 A TW 104124535A TW 104124535 A TW104124535 A TW 104124535A TW 201541526 A TW201541526 A TW 201541526A
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TWI564967B (zh
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Paul A Nyhus
Swaminathan Sivakumar
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Intel Corp
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Abstract

定向自組裝(DSA)材料或雙嵌段共聚物係可基於微影操作來圖案化特徵，該等特徵最終界定一垂直奈米線電晶體之一通道區域及一閘極電極。在實施例中，DSA材料係被侷限於利用微影術圖案化之一導引開口中。在實施例中，通道區域與閘極電極材料係對準於在DSA材料中之分化區域的邊緣。

Description

垂直奈米線電晶體通道的圖案化及具有定向自組裝的閘極
本發明之實施例整體而言係關於用於微電子器件之電晶體製造，且更具體而言係關於使用定向自組裝(DSA)之一垂直奈米線電晶體之圖案化。
在垂直定向電晶體中，良好控制的材料層厚度界定功能性長度，諸如閘極長度(Lg)，且材料組份可有利地修改以達到能帶隙及遷移性差異。電流驅動亦可藉由通道寬度(Wg)之微影圖案化及奈米線之對應橫截面連續地縮放。然而，在特定申請案中，吾人可能需要印刷奈米線特徵(例如孔)之直徑大約為15nm或更小，且同時具有非常良好的臨界尺寸(CD)均勻度、良好的圓形度及對於最高密度之最小特徵間距。此外，通道圖案必須準確地對準閘極堆疊及接觸敷金屬。
小於15nm之孔之微影印刷具有足夠的CD均勻度、 圓形度及間距係超出已知的ArF或EUV光阻劑的能力。藉以將孔印刷成較大且接著收縮的技術仍未能達到所要的間距(例如<30nm)。此間距甚至係低於兩個遮罩圖案化技術之解析度，並因此將需要至少三個遮罩圖案化步驟與採用一昂貴微影工具組之一非常積極的收縮製程。
圖案化一垂直奈米線電晶體至尺寸低於15nm及間距低於30nm而可以較低成本製造的技術因此係有利的。
101‧‧‧垂直奈米線電晶體
105‧‧‧基板
111‧‧‧源極/汲極半導體
111A‧‧‧半導體材料層
111B‧‧‧半導體材料層
111C‧‧‧半導體材料層
111D‧‧‧半導體材料層
111E‧‧‧半導體材料層
120‧‧‧源極/汲極區域
120B‧‧‧源極/汲極區域
122B‧‧‧源極/汲極接觸
130B‧‧‧源極/汲極區域
132B‧‧‧源極/汲極接觸
135B‧‧‧外在源極/汲極區域
145B‧‧‧通道區域
150B‧‧‧閘極堆疊
156‧‧‧第二介電質間隔件
201‧‧‧方法
205‧‧‧操作
210‧‧‧操作
215‧‧‧操作
220‧‧‧操作
225‧‧‧操作
230‧‧‧操作
305‧‧‧開孔
306‧‧‧導引開口邊緣
310‧‧‧半導體層
315‧‧‧導引開口
315A‧‧‧半導體通道區域
315B‧‧‧周圍半導體材料
320‧‧‧源極/汲極半導體層
325‧‧‧通道半導體層
340‧‧‧遮罩
350‧‧‧DSA材料
350A‧‧‧內部聚合物區域
350B‧‧‧外部聚合物區域
375‧‧‧環形溝槽
380‧‧‧閘極介電質
380A‧‧‧溝槽側壁
380B‧‧‧側壁
390‧‧‧閘極電極材料
415‧‧‧介電層
903‧‧‧晶質半導體基板層
925‧‧‧介電層
945‧‧‧導電層
1003‧‧‧基板
1010‧‧‧底部源極/汲極層
1015‧‧‧通道層
1020‧‧‧頂部源極/汲極層
1030‧‧‧介電質(硬遮罩)層
1040‧‧‧介電質間隔件
1050‧‧‧矽化物
1060‧‧‧介電材料
1070‧‧‧介電質
1100‧‧‧行動運算平台
1105‧‧‧顯示螢幕
1110‧‧‧SOC
1111‧‧‧控制器
1115‧‧‧電源管理積體電路
1115‧‧‧電池
1120‧‧‧擴展視圖
1125‧‧‧RF積體電路
1160‧‧‧矽基板
1177‧‧‧記憶體
1200‧‧‧運算裝置
1202‧‧‧板
1204‧‧‧處理器
1206‧‧‧通信晶片
本發明之實施例係藉由在附圖之圖式中的實例且非限制性來繪示說明，其中：圖1係依照一實施例之一垂直奈米線電晶體的等角視圖；圖2繪示依照一實施例之形成一垂直奈米線電晶體之方法的流程圖；圖3A、3B、3C、3D及3E繪示依照一實施例當執行圖2之方法中的操作所形成之單一通道結構之平面圖；圖4A、4B、4C、4D及4E繪示依照一實施例在圖3A至3E中所示之結構的橫截面視圖；圖5A、5B、5C、5D、5E及5F繪示依照一實施例當執行圖2之方法中的操作所形成之單一通道結構之平面圖；圖6A、6B、6C、6D、6E及6F繪示依照一實施例在圖5A至5D中所示之結構之橫截面視圖； 圖7A、7B及7C繪示依照一實施例當執行圖2之方法中的操作所形成之雙通道結構之平面圖；圖8A、8B及8C繪示依照一實施例在圖7A至7C中所示之結構之橫截面視圖；圖9A、9B、9C、9D及9E繪示依照一實施例當執行圖2之方法中的操作所形成之單一通道結構之橫截面視圖；圖10A、10B、10C、10D、10E、10F、及10G繪示依照一實施例當執行圖2之方法中的操作所形成之單一通道結構之橫截面視圖；圖11係依照本發明之一實施例採用非平面電晶體之一行動運算平台之功能性方塊圖；及圖12繪示依照一實施例之運算裝置的一功能性方塊圖。
【發明內容及實施方式】
在以下的說明中，將陳述許多細節。然而，熟悉此項技術者應可瞭解，本發明在沒有這些具體細節的情況下仍可被實現。在一些情況中，已知方法及裝置係以方塊圖形式展示而非細節，以避免混淆本發明。在遍及說明書中所謂的「一實施例」或「在一個實施例中」意謂結合實施例所描述之一特定特徵、結構、功能或特性被包括在本發明之至少一個實施例中。因此，遍及此說明書在不同段落中術語「在一個實施例中」之出現並不一定係參照本發明之 相同實施例。再者，在一或多個實施例中，特定特徵、結構、功能或特性可以任何適當的方式組合。例如，一第一實施例可與一第二實施例在任何段落組合，兩個實施例在結構上或功能上係不包括另一者。
術語「耦合」及「連接」與其衍生詞可在本文中用來描述組件之間之結構關係。應瞭解，這些術語彼此並不意指為同義詞。再者，在特定實施例中，「連接」可被用於指示兩個或更多個元件彼此直接實體或電性接觸。「耦合」可被用於指示兩個或更多個元件彼此直接或間接(在其之間具有其他中介元件)實體或電性接觸，及/或兩個或更多個元件彼此協作或相互影響(例如為一因果關係)。
在本文中所用之術語「上方」、「下方」、「之間」及「上面」意指一材料層相對於其他層之一相對位置。因此，例如，一層設置在另一層之上方或下方可直接地接觸另一層或可具有一或多個中介層。再者，一層設置在兩個層之間可直接地接觸兩個層或可具有一或多個中介層。相較而言，一第一層在一第二層「上」係直接接觸該第二層。
圖1係一例示性垂直奈米線電晶體101之等角視圖，其可依照本發明之實施例來製造。對於垂直奈米線電晶體101，一半導體奈米線係相對於基板105垂直定向，使得縱向長度L係沿著z維度(垂直於基板105之一表面平面)，且寬度W界定由奈米線所佔用的基板105之一區域。至於一橫向定向電晶體，垂直電晶體101包括一或多 個半導體材料沿著縱向長度L對應至電晶體之功能性區域，其包含通道區域145B設置在一含雜質的源極/汲極區域135B、源極/汲極區域130B及源極/汲極區域120B之間。根據實施例，電晶體101之一汲極在基板105上可為在下，或電晶體可被倒置以具有「源極在下」。在垂直形式中，電晶體101具有臨界尺寸，諸如通道長度及Lg(亦即縱向長度L之部分)，其係藉由材料層厚度界定，其可以藉由磊晶生長製程、植入製程或沈積製程之任一製程被良好地控制(例如至5至10Å)。
一般而言，基板105及第一及第二半導體材料層111C、111B可以係任何業界習知的，包含IV族材料(例如Si、Ge、SiGe)、III-N材料(例如GaN、AlGaN等等)或III-V族材料(例如InAlAs、AlGaAs等等)。汲極/源極區域130B、120B係半導體材料層111A、111D，其可以係與通道區域145B相同之材料，或一不同材料。源極/汲極接觸122B可包含一半導體111E設置在源極/汲極區域120上，諸如一p+穿隧層及/或一高度摻雜(例如n+)低能帶隙覆蓋層。一低電阻率歐姆接觸金屬可進一步包含在源極接觸122B中。
電晶體101包含一閘極堆疊150B，其在通道區域145B內完全圍繞奈米線同軸纏繞。同樣地，源極/汲極接觸122B及132B亦被繪示為圍繞源極/汲極區域120B、130B同軸纏繞，雖然其等並不一定需要如此。設置在閘極堆疊150B之間，一第一介電質間隔件(未描繪)被設置 在源極/汲極接觸132B上，並且沿著一第一縱向長度完全圍繞外在源極/汲極區域135B同軸纏繞。一第二介電質間隔件156被設置在閘極堆疊150B上，並且沿著一第二縱向長度完全圍繞源極/汲極區域120B與設置在第二介電質間隔件上之源極/汲極接觸132B同軸纏繞。
圖2係依照一實施例繪示形成一垂直奈米線電晶體(諸如電晶體101)之方法201的流程圖。一般而言，方法201需要採用一定向自組裝(DSA)材料，諸如一雙嵌段共聚物，成為圖案特徵，其最後基於一個微影操作界定一垂直奈米線電晶體之一通道區域，且可能不需要一掃描器。
方法201開始於操作205在一遮罩層中微影圖案化一導引開口。該導引開口係提供讓DSA材料對準的一邊緣，且更特定地係一閉合的多邊形，且有利地呈彎曲狀，且更具體而言係呈圓形。在操作205中，任何數量的導引開口可同時地被印刷，例如導引開口之一1-D或2-D陣列可使用此項技術中已知任何習知的微影製程被印刷。如本文中所使用，一1-D陣列需要一列或行之導引開口在列或行維度中鄰近的導引開口之間具有最小間距且大於鄰近複數列或複數行之間之最小間距，且同時一2-D陣列需要導引開口之複數列及複數行與在列及行二者維度中所有開口之間具有最小間距。導引之尺寸及形狀可改變，以允許一個以上的通道開孔可在一給定導引層開口中被圖案化，例如圖7b。
圖3A至3D繪示依照一實施例在執行方法201中之 操作所形成之單一通道電晶體結構之平面圖。一圓形導引開口315係展示在圖3A中，並且表示用於在操作205中被印刷之一1-D或2-D陣列的一個重複單元。圖4A至4D繪示分別在圖3A至3D中所示之結構沿著圖3A中所描繪之線A-A’之橫截面視圖。在例示性實施例中，圓形導引開口315具有不超過20nm之一臨界尺寸(CD1)與多邊形邊緣306穿過遮罩340之厚度界定一開孔305(圖4A)，該遮罩可以係一光阻劑或硬遮罩材料。任何適於所採用的微影工具之習知的光阻劑配方可被用於光阻劑實施例中。遮罩340被設置在一半導體層上，其具有一z高度的厚度(T1)對應至一理想電晶體通道長度(Lg)，其係提供奈米線電晶體之通道區域。對於圖4A中所示之例示性實施例，雖然一介置材料層，諸如一硬遮罩材料層(例如SixNy、SiO2等等)，可被設置在光阻層340及通道半導體層315之間，但遮罩340係直接地設置在通道半導體層315(例如單晶矽、SiGe等等)上。
返回至圖2，方法201繼續進行至操作210，其中DSA材料被沈積至在操作205中所形成的導引開口中。在應用DSA材料之準備中，層315之表面可經處理，使得對於聚合物A及聚合物B係有同樣地吸引力/排斥力。如圖3B及4B中所示，一DSA材料350填滿導引開口315並且由導引開口邊緣306所容納。該DSA材料350一般包括至少第一及第二聚合物(亦即一聚合物A及一聚合物B)。當施加在基板上時，例如藉由旋轉塗覆，聚合物A及 B處在相互混合狀態。根據導引操作315之幾何圖形與CD及電晶體通道區域之所要CD，除了聚合物A及B之基本化學性質外，聚合物A及B可各自被選擇以具有所要的分子量分佈，且DSA材料350可被選擇以具有一所要的聚合物A相對聚合物B之比率(A：B)。雖可採用任何業界習知的DSA材料，在例示性實施例中，聚合物A及聚合物B之一者係存在於被採用作為遮罩340之一光阻劑中。例如，在遮罩340包括聚苯乙烯的情況下，聚合物A或聚合物聚合物B亦係聚苯乙烯。在此一實施例中，聚合物之另一者係PMMA(聚(甲基丙烯酸酯))。
方法201(圖2)繼續進行至操作215，其中DSA材料被分化成內部及外部聚合物區域。根據導引開口315之尺寸之功能及聚合物之分子量等等，當DSA材料350在一升高溫度於足以允許充分轉移聚合物之一持續時間下退火時，將發生聚合物A從聚合物B分離。隨著導引開口315圍住DSA材料350，分化可以被設計成一個聚合物(例如聚合物A)轉移遠離導引邊緣306，而同時聚合物之另一者(例如聚合物B)轉移朝向導引邊緣306。主要包括一第一聚合物之一內部聚合物區域350A接著藉由主要包括一第二聚合物之一外部聚合物區域350B被完全包圍。在圖3C及4C所示之例示性實施例中，內部聚合物區域350A從導引開口邊緣被隔開以具有從該CD1減少之一CD2的直徑。對於適當地選擇DSA組成物、底層及導引開口邊緣表面特性，內部聚合物區域350A形成整數個嵌入至外部 聚合物區域350B中之大致上相同的圓柱或球體。雖然在圖3A至3E中所示之例示性單一通道實施例中，一單一內部聚合物區域350A被形成，多個此種區域可被形成，只要導引開口在至少一個維度中尺寸係夠大的。由於分化機制係DSA材料之共聚物特性之一經良好控制的功能，因此內部聚合物區域彼此及距導引開口邊緣可維持一致的距離。因此，內部聚合物區域350A係有效地自對準於導引開口邊緣306。
接著在操作215執行烘烤及/或固化，方法201繼續進行至操作220，其中電晶體之一半導體通道區域藉由相對於另一者選擇性移除內部及外部聚合物區域之一者而被界定在導引開口之內部中。在圖3D及4D所示之例示性實施例中，外部聚合物區域350B相對於內部聚合物區域350A而選擇性地被移除(例如溶解)。如進一步所示，外部聚合物區域350B同樣相對於遮罩340選擇地被移除，使得在操作220界定兩個邊緣：內部聚合物區域350A之一邊緣；及導引開口邊緣306，具有內部聚合物區域350A之邊緣自對準至導引開口邊緣306。
一環形溝槽375接著被蝕刻穿過通道半導體層315而且內部聚合物區域350A與遮罩340一起被移除。通道半導體層315之曝露部分可針對給定的半導體材料(Si、SiGe等等)以業界習知的任何蝕刻製程被蝕凹，以形成與內部聚合物區域350A之一邊緣對準之與電晶體Lg相關聯之通道區域315A之一側壁。如本文中所使用，「對準」 容許被引起的一些垂直性蝕刻偏差(正或負)，其可使通道區域315A之CD不同於CD2的臨界尺寸，但通道區域315A之尺寸仍然係基於內部聚合物區域350A的尺寸，且因此明顯小於導引開口之尺寸(CD1)。例如，通道區域315A之側壁以一非等向性蝕刻穿過通道區域315A對準內部聚合物區域350A，接著藉由一等向性蝕刻相對於內部聚合物區域350A之CD來蝕凹通道區域315A之側壁。在其中導引開口CD1係小於20nm之一實施例中，通道區域315A具有小於15nm之CD2。基於組份蝕刻選擇性或例如基於一定時蝕刻，溝槽375可能被停止在一下部的半導體材料310(例如單晶Si、SiGe、Ge等等)上。根據實施例，下部的半導體材料310係已被重度摻雜至一特定導電類型、可在其曝露時被摻雜、或被部分地移除且再生長成一摻雜材料中的任一者。在圖3D及4D所示之實施例中，半導體材料310重度摻雜以充當一源極/汲極區域(例如圖1中源極/汲極區域111A及/或含雜質的源極/汲極區域111B)。
隨著半導體通道區域在操作220被界定，方法201繼續進行，在操作225中沈積一閘極材料至半導體通道區域之一側壁上。一般而言，可執行任何業界習知的閘極介電質沈積製程，包含一犧牲閘極介電質之沈積，其後續在之後的製程(例如在一習知的「閘極後製程」類型製程流)中被替換。然而，在例示性實施例中，在操作225中，一非犧牲高k(例如>9)閘極介電質380係沈積在曝露在溝槽 375底部之半導體表面上、及在溝槽側壁380A及380B上。舉例來說，一金屬氧化物(諸如HfO2或ZrO2，但不以此為限)在操作225藉由原子層沈積被沈積為閘極介電質380。
方法201接著在操作230中完成，其中半導體通道區域315A由一閘極電極材料所包圍。在例示性實施例中，操作230包括以一閘極電極材料390填充圓柱狀溝槽375。該閘極電極材料390可包含任何習知的閘極電極材料，諸如多晶矽、一功函數金屬及/或一填充金屬，但不以此為限。業界習知的技術(諸如沈積及拋光，但不以此為限)可用以平坦化具有該通道區域315A之閘極電極材料390或一上覆的硬遮罩層。如圖3E及4E中所示，閘極介電質380將閘極電極材料390與通道區域315A以及與下部的源極/汲極區域310及周圍半導體材料315B電分化。明顯地，閘極電極材料390之尺寸因此完全自對準於導引開口邊緣306，以及自對準於通道區域315A，僅保留閘極電極材料390之z高度厚度可根據所要的電晶體通道長度函數而改變。垂直電晶體可以接著藉由習知的技術(例如源極/汲極半導體111D在半導體通道區域315A之曝露表面上的沈積或磊晶生長、接觸敷金屬之沈積等等)而完成。
圖5A至5F繪示依照一替代實施例當執行方法201中之操作所形成之單一通道結構之平面圖。圖6A至6F繪示依照一實施例在圖5A至5F中所示之結構之橫截面 視圖。大體而言，在圖5A至5F所示實施例中，除了遮罩340係沈積在設置於半導體層310上之一介電層415(例如SixNy、SiON、SiO2)上之外，操作205至215係如同在圖3A至3D之背景中所描述的。隨著共聚物分化成內部聚合物區域350A及外部聚合物區域350B，在操作220中，相對於外部聚合物區域350B，內部聚合物區域350A選擇性地被移除，如圖5D及6D中所示。在此例示性實施例中，遮罩340亦被移除而留下由外部聚合物區域350B組成之一環形遮罩。介電層415接著被蝕刻以曝露半導體材料310之下部的結晶表面。如圖6E中所示，操作220進一步包含移除外部聚合物區域350B，且從曝露的晶質半導體表面磊晶生長(例如藉由MOCVD等等)該半導體通道區域315A且以介電層415充當一生長擋止硬遮罩。給定半導體通道區域315A之尺寸(例如<15nm)，生長半導體材料層可由於捕獲縱橫比而有利地具有良好的結晶度。在半導體通道區域315A形成之後，介電層415之第二部分被蝕凹以形成曝露半導體通道區域之一側壁的一圓柱狀溝槽。在所描繪的例示性實施例中，介電層415被完全移除而曝露半導體層310之一表面。對於此一實施例，半導體層310被適當地摻雜以作為奈米線電晶體之源極/汲極半導體區域，且通道區域315A接著直接地磊晶生長源極/汲極半導體區域之一表面。
如圖5F及6F中所示，方法201接著繼續進行，透過操作225在側壁380A上、在半導體材料層310上及在側 壁380B上形成閘極介電質，大致上如本文在其他段落中參考圖3E及4E所描述的。閘極電極材料390接著在操作230中再次沈積包圍該通道區域315A。
雖然圖3A至3E及4A至4E以及圖5A至5F及6A至6F係繪示方法201之單一通道實施例，然而圖7A至7C繪示依照一實施例執行在方法201中之操作所形成之雙通道結構之平面圖。圖8A至8C進一步繪示在圖7A至7C中所示結構之橫截面視圖。一般而言，方法201大致上以如在本文其他段落對於具有界定兩個(或更多)內部聚合物區域之DSA材料之單一通道實施例所述的方式被實施，每個內部聚合物區域變成用於界定一垂直奈米線電晶體之一半導體通道區域之基礎。對於此多通道實施例，將DSA材料善用於使通道區域自對準至一包圍閘極並同時相對於用於印刷導引開口的間距來減少鄰近通道區域之間的間距。在例示性實施例中，兩個鄰近通道區域之間距係低於使用於印刷導引開口之一掃描器之解析度限制。
圖7A及8A繪示導引開口315初始圖案化(例如，印刷或蝕刻)至遮罩340(例如，操作205)中在一第一維度(例如軸線B1)中係大於一第二維度(例如軸線A1)。一般而言，較長長度B1超過DSA材料之一臨限值特性(例如40nm)而較短長度A1則沒有超過(例如A1對於一單一通道實施例可大約係一導引開口之直徑(例如小於20nm)。在實施例中，較長長度B1係至少較短長度A1的兩倍。對於特定表面條件，此一細長導引開口315當充滿具有適當的 共聚物特性之DSA材料時係會退火至兩內部聚合物區域350A1及350A2，如在圖7B及8B所示。內部聚合物區域350A1及350A2兩者皆由一毗連的外部聚合物區域350B所包圍，其具有如本文中其他段落單一通道實施例之背景中所述之每個分化區域之材料特性。在分化之後，內部聚合物區域350A1及350A2基本上具有相同尺寸(例如圖8C中所示之CD3)。在例示性實施例中，其中導引開口具有至少一個維度係小於20nm、內部聚合物區域350A1及350A2各具有小於15nm之寬度；且在其它此類實施例中，內部聚合物區域350A1及350A2之間距亦係小於15nm。
在複數個內部聚合物區域350A1及350A2實質上與外部聚合物區域350B有區別的情況下，方法201透過操作220、225、230繼續進行，大致上如對於單一通道實施例(例如藉由圖3A至3E、4A至4E之任一者所示)所述以將通道半導體層315界定成兩個通道區域315A1及315A2，該兩個通道區域係分別經由閘極介電質350A1及350A2藉由一共用閘極電極390所控制。因此，可利用DSA材料之分化能力製成多導線垂直電晶體，其可針對最佳閘極控制(減少短通道效應)單獨地定尺寸，同時提供一所要之驅動電流量(由所形成之分立通道的數量所決定)。
在實施例中，不僅一垂直電晶體之通道區域及閘極係基於一DSA材料之分化界定，電晶體之其他功能性區域(諸如，源極汲極區域，但不以此為限)亦是如此，如由圖 9A至9E及10A至10G所示。圖9A、9B、9C、9D及9E繪示依照一實施例當執行圖2B之方法中的操作所形成之單一通道結構之橫截面視圖。一般而言，在此例示性實施例中，一垂直奈米線電晶體之源極/汲極區域以及通道區域係在藉由一DSA材料之分化界定之區域中重新生長。
圖9A在操作215完成後開始，其中DSA材料已經被分化在內部聚合物區域350A及外部聚合物區域350B。在本實施例中之基板包含被設置在一退化性摻雜半導體層945上之一介電層925，半導體層945係進一步設置在一晶質半導體基板層903上。內部聚合物區域350A如本文中其他段落所述，相對於外部聚合物區域350B選擇性地被移除，並且同樣相對於遮罩340選擇性地被移除，如圖9B中所示。一內部溝槽接著被蝕刻穿過在內部聚合物區域350A被移除之區域中之介電層925及層945，使半導體903曝露。隨著遮罩340接著被移除，介電層925之周圍部分被移除而留下包圍內部溝槽之介電質925之環形周邊。接著採用一選擇性磊晶製程以從內部溝槽及周圍區域內之曝露半導體基板層903之種晶表面形成奈米線電晶體。如圖9D所示，一第一(底部)晶體源極/汲極半導體層310係從半導體基板層903及從半導體層945生長。由於可在源極/汲極半導體層310中發生有利的缺陷捕獲，因此源極/汲極半導體層310之重新生長可在後續生長之通道區域中改良結晶度。再者，源極/汲極半導體層310之重新生長用於可選擇地形成一連接至新嵌入之導電性半導 體層945與形成在半導體層945上方之晶體或多晶體半導體。一半導體通道區域315接著從源極/汲極半導體層310磊晶生長。一第二(頂部)源極/汲極半導體層320進一步在半導體通道區域315上生長。重新生長之薄膜被回拋光以抵靠作為一拋光擋止件之介電層925來予以平坦化。由於在內部溝槽及周圍之間之初始非平面性，平坦化製程在周圍中移除重新生長半導體返回至底部源極/汲極半導體層310，而同時頂部源極/汲極半導體層320被保留在內部區域中作為垂直奈米線電晶體之一部分。
閘極介電質在操作220中之藉由首先蝕凹原本設置該外部聚合物區域350B之餘留的介電層925之環形部分而形成。此曝露半導體通道區域315之一側壁。介電層925可藉由對下部導電層945選擇性的蝕刻而完全地蝕凹，在此情況中在操作225形成的閘極介電質用於隔絕導電層945與閘極電極材料390。或者，介電層925可只有部分地蝕凹(例如用一定時回蝕)以增加閘極電極材料390及下部的導電層945之間之介電質之厚度。因此，在圖9E中所示之垂直奈米線電晶體之頂表面結構被平坦化並且提供可由頂側接達至電晶體用於接觸(例如矽化)及互連敷金屬的所有作用區域。
圖10A、10B、10C、10D及10E繪示依照一實施例當執行圖2B之方法中的操作所形成之單一通道結構之橫截面視圖。在此例示性實施例中，基於一DSA材料蝕刻之半導體材料堆疊包含兩個源極/汲極層及一通道層。因 此，此實施例可被視為藉由圖3A至3E、4A至4E所示實施例之一特例。圖10A開始於DSA材料分化成內部及外部聚合物區域350A、350B。基板包含一半導體材料層堆疊，其包含在組成上不同的(透過摻雜或不同晶格原子)材料層。對於例示性實施例，半導體材料堆疊包含設置在一基板1003上之一底部源極/汲極層1010、設置在底部源極/汲極層1010上之一通道層1015及設置在通道層1015上方之一頂部源極/汲極層1020。一介電質(硬遮罩)層1030係設置在半導體堆疊上方。
如圖10B中所示，外部聚合物區域350B相對於內部聚合物區域350A及遮罩340選擇性地被移除。一環形溝槽接著被蝕刻穿過該堆疊的大部分以曝露底部源極/汲極層1010，如圖10C中所示。一介電質間隔件1040(圖10D)沿著半導體堆疊之側壁形成且一矽化物1050形成在兩個曝露源極/汲極層1010上。介電材料1060接著在溝槽內沈積、平坦化及蝕凹(回蝕)至足以再曝露通道區域側壁的一z高度(厚度)。一等向性蝕刻移除介電質間隔件1040且閘極介電質380被沈積在該蝕凹之介電材料1060上方之溝槽中及該通道半導體側壁上。閘極電極材料接著被沈積在溝槽中，與介電質1030之一頂表面一起平坦化，然後被蝕刻蝕凹至足以控制通道區域之一z高度(厚度)。最後，一介電質1070被沈積在溝槽中，與介電質1030之頂表面一起平坦化。該介電質1030然後可相對於介電質1070選擇性地被移除以曝露頂部源極/汲極1020 以準備用於接觸敷金屬。因此，具有次微影導線尺寸(例如<15nm)之垂直定向奈米線電晶體與局部互連基於一單一微影遮罩及DSA材料被自對準地製造。
圖11係依照本發明之一實施例之一行動運算平台的SOC實施方案之功能性方塊圖。行動運算平台1100可以係組態成用於每個電子資料顯示、電子資料處理及無線電子資料傳輸之任何可攜式裝置。例如，行動運算平台1100可以係平板、智慧型電話、膝上型電腦等等之任何行動運算平台，而且包含一顯示螢幕1105、SOC 1110及一電池1115。如圖所示，SOC 1110之整合程度越大，則在行動運算裝置1100中之更多形狀因數可由在充電之間能以最長操作壽命之電池1115所佔用，或由記憶體(未描繪)，諸如一固態驅動器、DRAM等等所佔用以最佳化平台功能。
SOC 1110進一步被繪示在擴展視圖1120中。根據實施例，SOC 1110包含一矽基板1160(即一晶片)之一部分，在其上有一或多個電源管理積體電路(PMIC)1115、包含一RF傳輸器及/或接收器之RF積體電路(RFIC)1125、其控制器1111及一或多個中心處理器核心或記憶體1177。在實施例中，SOC 1110包含與在本文中所述之一或多個實施例一致之一或多個垂直奈米線電晶體(FETs)。在進一步的實施例中，SOC 1110之製造包含在本文中所述用於製造一垂直定向奈米線電晶體(FETs)之一或多種方法。
圖12依照本發明之一個實施例係一運算裝置1200之功能性方塊圖。該運算裝置1200可例如出現在平台1100中，且進一步包含主控許多個組件之一板1202，諸如一處理器1204(例如一應用處理器)及至少一個通信晶片1206，但不以此為限。在實施例中，至少該處理器1204包含具有依照本文中其他段落所述實施例之結構及/或依照在本文中其他段落進一步所述實施例而製成之一垂直奈米線電晶體(FET)。處理器1204係實體地及電性地耦合至板1202。該處理器1204包含在處理器1204內封裝之一積體電路晶粒。術語「處理器」可指稱任何裝置或一裝置之部分，其係處理來自於暫存器及/或記憶體之電子資料以電子資料轉換成可被儲存在暫存器及/或記憶體中之其他電子資料。
在一些實施方案中，至少一個通信晶片1206亦被實體地及電性地耦合至板1202。在其它實作中，通信晶片1206係處理器1204之部分。根據其應用，運算裝置1200可包含其他組件，其可以或可不被實體地及電性地耦合至板1202。這些其他組件包含揮發性記憶體(例如DRAM)、呈快閃記憶體或STTM等等的形式之非揮發性記憶體(例如RAM或ROM)、圖像處理器、數位信號處理器、加密處理器、晶片組、天線、觸控顯示器、觸控控制器、電池、音訊編解碼器、視訊編解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、迴轉儀、揚聲器、攝像機及大容量儲存裝置(諸如硬碟機、固態驅動器(SSD)、 光碟片(CD)等等)，但不以此述為限。
至少一個通信晶片1206能夠無線通信以傳送資料往返於運算裝置1200。術語「無線」及其衍生詞可用於描述電路、裝置、系統、方法、技術、通信通道等等，其可透過通過一非固態媒體之調變電磁輻射之使用來傳達資料。該術語並不意味相關的裝置不包含任何導線，儘管在一些實施例可能是沒有。通信晶片1206可實施任何許多無線標準或協定，包含在本文中其他段落所述者，但不以此為限。運算裝置1200可包含複數個通信晶片1206。例如，一第一通信晶片1206可以係專用於較短程無線通信，諸如Wi-Fi及藍芽，且一第二通信晶片1206可以係專用於較長程無線通信，諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等等。
應瞭解，上面的描述旨在說明而非限制。例如，當在圖式中之流程圖展示藉由本發明之某些實施例執行之一特定順序的操作時，應瞭解，此順序並非係必要的(例如替代的實施例可以不同順序執行該操作、組合特定操作、重覆特定操作等等)。再者，在閱讀及瞭解上面的描述後，熟悉此項技術者應可瞭解許多其他的實施例。雖然本發明已經參照指定的例示性實施例來描述，但應瞭解，本發明並不限於所描述的實施例，而是可以由在隨附申請專利範圍之精神及範疇內之修改及替代來實現。因此，本發明之範圍應藉由參照後附之申請專利範圍及授予此等申請專利範圍等效事物的完整範圍來決定。
101‧‧‧垂直奈米線電晶體
105‧‧‧基板
111A‧‧‧半導體材料層
111B‧‧‧半導體材料層
111C‧‧‧半導體材料層
111D‧‧‧半導體材料層
111E‧‧‧半導體材料層
120B‧‧‧源極/汲極區域
122B‧‧‧源極/汲極接觸
130B‧‧‧源極/汲極區域
132B‧‧‧源極/汲極接觸
135B‧‧‧外在源極/汲極區域
145B‧‧‧通道區域
150B‧‧‧閘極堆疊

Claims (20)

  1. 一種在基板上形成奈米線電晶體之方法，該方法包括：在設置於該電晶體之一源極/汲極半導體層之上的一遮罩層中微影圖案化一導引開口；將一定向自組裝(DSA)材料沈積於該導引開口中；在該導引開口中，將該DSA材料分化至由一外部聚合物區域完全包圍之一內部聚合物區域中，該內部聚合物區域具有圓柱幾何形狀，該圓柱幾何形狀具有直徑；藉由相對於另一者選擇性地移除該內部聚合物區域及該外部聚合物區域之一者而在該導引開口中界定該電晶體之一半導體通道區域，其中該半導體通道區域具有由該內部聚合物區域的該圓柱幾何形狀的該直徑所界定的直徑；移除該內部聚合物區域與該外部聚合物區域之另一者；沈積一閘極介電質於該半導體通道區域之上；且以具有自對準於該導引開口之外直徑的一環形閘極電極來包圍該半導體通道區域。
  2. 如申請專利範圍第1項之方法，其中微影圖案化該導引開口包含微影圖案化彎曲的導引開口。
  3. 如申請專利範圍第1項之方法，其中微影圖案化該導引開口包含微影圖案化圓形的導引開口。
  4. 如申請專利範圍第1項之方法，其中分化該DSA材料包含烘烤及/或固化該DSA材料。
  5. 如申請專利範圍第1項之方法，其中界定該半導體通道區域進一步包括：移除該外部聚合物區域且同時保留該內部聚合物區域以曝露一通道半導體層之一部分；且蝕凹該通道半導體層之該曝露部分以形成一圓柱狀溝槽，該圓柱狀溝槽具有與該內部聚合物區域之一邊緣對準之該電晶體的一通道長度相關聯的通道半導體側壁。
  6. 如申請專利範圍第5項之方法，其中該蝕凹係曝露該電晶體之一源極/汲極半導體區域，且其中該閘極介電質將該源極/汲極半導體區域與該閘極電極材料隔離。
  7. 如申請專利範圍第5項之方法，其中將一閘極介電質沈積於該半導體通道區域之上係進一步包括將該閘極介電質沈積於該圓柱狀溝槽中且覆蓋該通道半導體側壁；且其中以該閘極電極包圍該半導體通道區域係包括以一閘極電極材料填充該圓柱狀溝槽。
  8. 如申請專利範圍第1項之方法，其中界定該半導體通道區域進一步包括：移除該內部聚合物區域且同時保留該外部聚合物區域以曝露一介電層的一下部的第一部分；在該介電層之已曝露的第一部分中蝕刻一溝槽以曝露一晶質半導體表面；且從該已曝露的晶質半導體表面磊晶生長該半導體通道區域；且蝕凹鄰近於該半導體通道區域之該介電層的一第二部 分以形成曝露該半導體通道區域之一側壁的一圓柱狀溝槽。
  9. 如申請專利範圍第8項之方法，其中該晶質半導體表面係該電晶體之一源極/汲極半導體區域的一表面。
  10. 如申請專利範圍第8項之方法，其中該晶質半導體表面係一未摻雜或輕度摻雜之半導體基板的一表面，且其中磊晶生長該半導體通道區域係進一步包括首先從該半導體基板之該表面生長該電晶體之一源極/汲極半導體區域，然後從該源極/汲極半導體區域生長該半導體通道區域。
  11. 如申請專利範圍第8項之方法，其中將一閘極介電質沈積於該半導體通道區域之上係進一步包括將該閘極介電質沈積於該圓柱狀溝槽中且覆蓋該通道半導體側壁；且其中以該閘極電極包圍該半導體通道區域係包括以一閘極電極材料填充該圓柱狀溝槽。
  12. 如申請專利範圍第11項之方法，其中該閘極介電質係沈積於該介電層之該蝕凹的第二部分之上。
  13. 如申請專利範圍第1項之方法，其中微影圖案化一導引開口進一步包括印刷在第一維度中具有第一直徑及在第二維度中具有第二直徑之一開口，該第二直徑係至少為該第一直徑的兩倍；其中在該導引開口中將該DSA材料分化至由該外部聚合物區域完全包圍之該內部聚合物區域中係進一步包括 形成由該外部聚合物區域完全包圍之第二內部聚合物區域，該第二內部聚合物區域具有圓柱幾何形狀，該圓柱幾何形狀具有直徑；且其中界定該半導體通道區域係進一步包括形成第二通道區域，其中該第二通道區域具有由該第二內部聚合物區域的該圓柱幾何形狀的該直徑所界定的直徑。
  14. 如申請專利範圍第1項之方法，其中沈積該DSA材料於該導引開口中係進一步包括旋轉塗覆包括第一聚合材料及第二聚合材料之DSA材料；且其中分化該DSA材料進一步包括以足以允許該第一聚合材料轉移至該內部聚合物部分中且同時允許該第二聚合材料轉移至該外部聚合物部分中之溫度及持續時間來固化該DSA材料。
  15. 如申請專利範圍第14項之方法，其中該第一聚合材料及第二聚合材料之一者包括PMMA。
  16. 如申請專利範圍第15項之方法，其中該第一聚合材料及第二聚合材料之另一者包括聚苯乙烯。
  17. 如申請專利範圍第14項之方法，其中該遮罩層包括該第一聚合材料及第二聚合材料之一者。
  18. 一種在基板上形成奈米線電晶體的方法，該方法包括：在設置於該電晶體之一源極/汲極半導體層之上的一遮罩層中微影圖案化一導引開口；將一定向自組裝(DSA)材料沈積於該導引開口中； 在該導引開口中將該DSA材料分化至由一外部聚合物區域完全包圍之一內部聚合物區域中，該內部聚合物區域具有圓柱幾何形狀，該圓柱幾何形狀具有直徑；相對於該內部聚合物區域選擇性地移除該外部聚合物區域以形成曝露一下部的硬遮罩層的一圓柱狀溝槽；蝕刻穿過該硬遮罩層以更深入該溝槽且曝露一第一半導體源極/汲極區域；蝕刻穿過該第一半導體源極/汲極區域之該曝露部分以更深入該溝槽且曝露被設置於該源極/汲極區域下方的一半導體通道層；蝕刻該半導體通道層之該曝露部分以更深入該溝槽且曝露被設置於該半導體通道層下方的一半導體層；以一第一介電材料填充該溝槽且相對於該硬遮罩層選擇性地回蝕該第一介電材料以曝露該半導體通道層之一側壁；沈積一閘極介電質於該側壁上；且以一閘極電極材料填充該溝槽，俾以具有自對準於該導引開口之外直徑的一環形閘極電極來包圍該側壁。
  19. 如申請專利範圍第18項之方法，其中微影圖案化該導引開口包含微影圖案化彎曲的導引開口。
  20. 如申請專利範圍第18項之方法，其中分化該DSA材料包含烘烤及/或固化該DSA材料。
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